pax_global_header00006660000000000000000000000064132260064620014513gustar00rootroot0000000000000052 comment=ae78724247a01560164d607ed66db111c74d8df0 arm-trusted-firmware-1.0-aw-6/000077500000000000000000000000001322600646200162045ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/.gitignore000066400000000000000000000002651322600646200201770ustar00rootroot00000000000000# Ignore miscellaneous files cscope.* *.swp *.patch .project .cproject # Ignore build directory build/ # Ignore build products from tools tools/**/*.o tools/fip_create/fip_create arm-trusted-firmware-1.0-aw-6/Makefile000066400000000000000000000352601322600646200176520ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # # Trusted Firmware Version # VERSION_MAJOR := 1 VERSION_MINOR := 0 # # Default values for build configurations # # Build verbosity V := 0 # Debug build DEBUG := 0 # Build architecture ARCH := aarch64 # Build platform DEFAULT_PLAT := fvp PLAT := ${DEFAULT_PLAT} # SPD choice SPD := none # Base commit to perform code check on BASE_COMMIT := origin/master # NS timer register save and restore NS_TIMER_SWITCH := 0 # By default, Bl1 acts as the reset handler, not BL31 RESET_TO_BL31 := 0 # Include FP registers in cpu context CTX_INCLUDE_FPREGS := 0 # Determine the version of ARM GIC architecture to use for interrupt management # in EL3. The platform port can change this value if needed. ARM_GIC_ARCH := 2 # Flag used to indicate if ASM_ASSERTION should be enabled for the build. # This defaults to being present in DEBUG builds only. ASM_ASSERTION := ${DEBUG} # Checkpatch ignores CHECK_IGNORE = --ignore COMPLEX_MACRO CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE} CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE} ifeq (${V},0) Q=@ CHECKCODE_ARGS += --no-summary --terse else Q= endif export Q ifneq (${DEBUG}, 0) BUILD_TYPE := debug # Use LOG_LEVEL_INFO by default for debug builds LOG_LEVEL := 40 else BUILD_TYPE := release # Use LOG_LEVEL_NOTICE by default for release builds LOG_LEVEL := 20 endif # Default build string (git branch and commit) ifeq (${BUILD_STRING},) BUILD_STRING := $(shell git log -n 1 --pretty=format:"%h") endif VERSION_STRING := v${VERSION_MAJOR}.${VERSION_MINOR}(${BUILD_TYPE}):${BUILD_STRING} BL_COMMON_SOURCES := common/bl_common.c \ common/tf_printf.c \ common/aarch64/debug.S \ lib/aarch64/cache_helpers.S \ lib/aarch64/misc_helpers.S \ lib/aarch64/xlat_helpers.c \ lib/stdlib/std.c \ plat/common/aarch64/platform_helpers.S BUILD_BASE := ./build BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${BUILD_TYPE} PLATFORMS := $(shell ls -I common plat/) SPDS := $(shell ls -I none services/spd) HELP_PLATFORMS := $(shell echo ${PLATFORMS} | sed 's/ /|/g') # Convenience function for adding build definitions # $(eval $(call add_define,FOO)) will have: # -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise define add_define DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) endef # Convenience function for verifying option has a boolean value # $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1 define assert_boolean $(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean)) endef ifeq (${PLAT},) $(error "Error: Unknown platform. Please use PLAT= to specify the platform.") endif ifeq ($(findstring ${PLAT},${PLATFORMS}),) $(error "Error: Invalid platform. The following platforms are available: ${PLATFORMS}") endif all: msg_start msg_start: @echo "Building ${PLAT}" include plat/${PLAT}/platform.mk # By default all CPU errata workarounds are disabled. This can be # overridden by the platform. include lib/cpus/cpu-errata.mk ifdef BL1_SOURCES NEED_BL1 := yes include bl1/bl1.mk endif ifdef BL2_SOURCES NEED_BL2 := yes include bl2/bl2.mk endif ifdef BL31_SOURCES NEED_BL31 := yes include bl31/bl31.mk endif # Include SPD Makefile if one has been specified ifneq (${SPD},none) # We expect to locate an spd.mk under the specified SPD directory SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m") ifeq (${SPD_MAKE},) $(error Error: No services/spd/${SPD}/${SPD}.mk located) endif $(info Including ${SPD_MAKE}) include ${SPD_MAKE} # If there's BL32 companion for the chosen SPD, and the SPD wants to build the # BL2 from source, we expect that the SPD's Makefile would set NEED_BL32 # variable to "yes" endif .PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip .SUFFIXES: INCLUDES += -Iinclude/bl31 \ -Iinclude/bl31/services \ -Iinclude/common \ -Iinclude/drivers \ -Iinclude/drivers/arm \ -Iinclude/drivers/io \ -Iinclude/lib \ -Iinclude/lib/aarch64 \ -Iinclude/lib/cpus/aarch64 \ -Iinclude/plat/common \ -Iinclude/stdlib \ -Iinclude/stdlib/sys \ ${PLAT_INCLUDES} \ ${SPD_INCLUDES} # Process DEBUG flag $(eval $(call assert_boolean,DEBUG)) $(eval $(call add_define,DEBUG)) ifeq (${DEBUG},0) $(eval $(call add_define,NDEBUG)) else CFLAGS += -g ASFLAGS += -g -Wa,--gdwarf-2 endif # Process NS_TIMER_SWITCH flag $(eval $(call assert_boolean,NS_TIMER_SWITCH)) $(eval $(call add_define,NS_TIMER_SWITCH)) # Process RESET_TO_BL31 flag $(eval $(call assert_boolean,RESET_TO_BL31)) $(eval $(call add_define,RESET_TO_BL31)) # Process CTX_INCLUDE_FPREGS flag $(eval $(call assert_boolean,CTX_INCLUDE_FPREGS)) $(eval $(call add_define,CTX_INCLUDE_FPREGS)) # Process ARM_GIC_ARCH flag $(eval $(call add_define,ARM_GIC_ARCH)) # Process ASM_ASSERTION flag $(eval $(call assert_boolean,ASM_ASSERTION)) $(eval $(call add_define,ASM_ASSERTION)) # Process LOG_LEVEL flag $(eval $(call add_define,LOG_LEVEL)) ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \ -Werror -Wmissing-include-dirs \ -mgeneral-regs-only -D__ASSEMBLY__ \ ${DEFINES} ${INCLUDES} CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \ -Werror -Wmissing-include-dirs \ -mgeneral-regs-only -std=c99 -c -Os \ ${DEFINES} ${INCLUDES} CFLAGS += -ffunction-sections -fdata-sections LDFLAGS += --fatal-warnings -O1 LDFLAGS += --gc-sections LDFLAGS += $(if $(shell $(LD) -v --fix-cortex-a53-843419 > /dev/null 2>&1 && echo 1),--fix-cortex-a53-843419) CC := ${CROSS_COMPILE}gcc CPP := ${CROSS_COMPILE}cpp AS := ${CROSS_COMPILE}gcc AR := ${CROSS_COMPILE}ar LD := ${CROSS_COMPILE}ld OC := ${CROSS_COMPILE}objcopy OD := ${CROSS_COMPILE}objdump NM := ${CROSS_COMPILE}nm PP := ${CROSS_COMPILE}gcc -E ${CFLAGS} # Variables for use with Firmware Image Package FIPTOOLPATH ?= tools/fip_create FIPTOOL ?= ${FIPTOOLPATH}/fip_create fiptool: ${FIPTOOL} fip: ${BUILD_PLAT}/fip.bin locate-checkpatch: ifndef CHECKPATCH $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl") else ifeq (,$(wildcard ${CHECKPATCH})) $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl") endif endif clean: @echo " CLEAN" ${Q}rm -rf ${BUILD_PLAT} ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean realclean distclean: @echo " REALCLEAN" ${Q}rm -rf ${BUILD_BASE} ${Q}rm -f ${CURDIR}/cscope.* ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean checkcodebase: locate-checkpatch @echo " CHECKING STYLE" @if test -d .git ; then \ git ls-files | grep -v stdlib | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \ else \ find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -not -iwholename "*stdlib*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \ fi checkpatch: locate-checkpatch @echo " CHECKING STYLE" @git format-patch --stdout ${BASE_COMMIT} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true ${FIPTOOL}: ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} @echo @echo "Built $@ successfully" @echo define match_goals $(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS)))) endef # List of rules that involve building things BUILD_TARGETS := all bl1 bl2 bl31 bl32 fip # Does the list of goals specified on the command line include a build target? ifneq ($(call match_goals,${BUILD_TARGETS}),) IS_ANYTHING_TO_BUILD := 1 endif define MAKE_C $(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) $(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) $(OBJ) : $(2) @echo " CC $$<" $$(Q)$$(CC) $$(CFLAGS) -DIMAGE_BL$(3) -c $$< -o $$@ $(PREREQUISITES) : $(2) @echo " DEPS $$@" @mkdir -p $(1) $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$< ifdef IS_ANYTHING_TO_BUILD -include $(PREREQUISITES) endif endef define MAKE_S $(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2)))) $(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) $(OBJ) : $(2) @echo " AS $$<" $$(Q)$$(AS) $$(ASFLAGS) -DIMAGE_BL$(3) -c $$< -o $$@ $(PREREQUISITES) : $(2) @echo " DEPS $$@" @mkdir -p $(1) $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$< ifdef IS_ANYTHING_TO_BUILD -include $(PREREQUISITES) endif endef define MAKE_LD $(eval PREREQUISITES := $(1).d) $(1) : $(2) @echo " PP $$<" $$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$< $(PREREQUISITES) : $(2) @echo " DEPS $$@" @mkdir -p $$(dir $$@) $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$< ifdef IS_ANYTHING_TO_BUILD -include $(PREREQUISITES) endif endef define MAKE_OBJS $(eval C_OBJS := $(filter %.c,$(2))) $(eval REMAIN := $(filter-out %.c,$(2))) $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj),$(3)))) $(eval S_OBJS := $(filter %.S,$(REMAIN))) $(eval REMAIN := $(filter-out %.S,$(REMAIN))) $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj),$(3)))) $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN))) endef # NOTE: The line continuation '\' is required in the next define otherwise we # end up with a line-feed characer at the end of the last c filename. # Also bare this issue in mind if extending the list of supported filetypes. define SOURCES_TO_OBJS $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \ $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1)))) endef define MAKE_BL $(eval BUILD_DIR := ${BUILD_PLAT}/bl$(1)) $(eval SOURCES := $(BL$(1)_SOURCES) $(BL_COMMON_SOURCES) $(PLAT_BL_COMMON_SOURCES)) $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES)))) $(eval LINKERFILE := $(BUILD_DIR)/bl$(1).ld) $(eval MAPFILE := $(BUILD_DIR)/bl$(1).map) $(eval ELF := $(BUILD_DIR)/bl$(1).elf) $(eval DUMP := $(BUILD_DIR)/bl$(1).dump) $(eval BIN := $(BUILD_PLAT)/bl$(1).bin) $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES),$(1))) $(eval $(call MAKE_LD,$(LINKERFILE),$(BL$(1)_LINKERFILE))) $(BUILD_DIR) : $$(Q)mkdir -p "$$@" $(ELF) : $(OBJS) $(LINKERFILE) @echo " LD $$@" @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__; \ const char version_string[] = "${VERSION_STRING}";' | \ $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \ $(BUILD_DIR)/build_message.o $(OBJS) $(DUMP) : $(ELF) @echo " OD $$@" $${Q}$${OD} -dx $$< > $$@ $(BIN) : $(ELF) @echo " BIN $$@" $$(Q)$$(OC) -O binary $$< $$@ @echo @echo "Built $$@ successfully" @echo .PHONY : bl$(1) bl$(1) : $(BUILD_DIR) $(BIN) $(DUMP) all : bl$(1) $(eval FIP_DEPS += $(if $2,$(BIN),)) $(eval FIP_ARGS += $(if $2,--bl$(1) $(BIN),)) endef ifeq (${NEED_BL1},yes) $(eval $(call MAKE_BL,1)) endif ifeq (${NEED_BL2},yes) $(eval $(call MAKE_BL,2,in_fip)) endif ifeq (${NEED_BL31},yes) BL31_SOURCES += ${SPD_SOURCES} $(eval $(call MAKE_BL,31,in_fip)) endif ifeq (${NEED_BL32},yes) $(eval $(call MAKE_BL,32,in_fip)) endif ifeq (${NEED_BL30},yes) FIP_DEPS += ${BL30} FIP_ARGS += --bl30 ${BL30} endif ifeq (${NEED_BL30},yes) # If BL3-0 is needed by the platform then 'BL30' variable must be defined. check_bl30: $(if ${BL30},,$(error "To build a FIP for platform ${PLAT}, please set BL30 to point to the SCP firmware")) else # If BL3-0 is not needed by the platform but the user still specified the path # to a BL3-0 image then warn him that it will be ignored. check_bl30: $(if ${BL30},$(warning "BL3-0 is not supported on platform ${PLAT}, it will just be ignored"),) endif ${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${BL33} ${FIPTOOL} check_bl30 $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd")) ${Q}${FIPTOOL} --dump \ ${FIP_ARGS} \ --bl33 ${BL33} \ $@ @echo @echo "Built $@ successfully" @echo cscope: @echo " CSCOPE" ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files ${Q}cscope -b -q -k ctag: ctags -R --c++-kinds=+p --fields=+iaS --extra=+q -w -o ctags `find $(CURDIR) \ -name '*.[chS]' -print` help: @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> " @echo "" @echo "PLAT is used to specify which platform you wish to build." @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}" @echo "" @echo "Supported Targets:" @echo " all Build the BL1, BL2 and BL31 binaries" @echo " bl1 Build the BL1 binary" @echo " bl2 Build the BL2 binary" @echo " bl31 Build the BL31 binary" @echo " checkcodebase Check the coding style of the entire source tree" @echo " checkpatch Check the coding style on changes in the current" @echo " branch against BASE_COMMIT (default origin/master)" @echo " clean Clean the build for the selected platform" @echo " cscope Generate cscope index" @echo " distclean Remove all build artifacts for all platforms" @echo " fiptool Build the Firmware Image Package(FIP) creation tool" @echo "" @echo "note: most build targets require PLAT to be set to a specific platform." @echo "" @echo "example: build all targets for the FVP platform:" @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all" arm-trusted-firmware-1.0-aw-6/acknowledgements.md000066400000000000000000000001671322600646200220640ustar00rootroot00000000000000Contributor Acknowledgements ============================ Companies --------- Linaro Limited Individuals ----------- arm-trusted-firmware-1.0-aw-6/bl1/000077500000000000000000000000001322600646200166625ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/bl1/aarch64/000077500000000000000000000000001322600646200201125ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/bl1/aarch64/bl1_arch_setup.c000066400000000000000000000046461322600646200231630ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include /******************************************************************************* * Function that does the first bit of architectural setup that affects * execution in the non-secure address space. ******************************************************************************/ void bl1_arch_setup(void) { /* Set the next EL to be AArch64 */ write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT); } /******************************************************************************* * Set the Secure EL1 required architectural state ******************************************************************************/ void bl1_arch_next_el_setup(void) { unsigned long next_sctlr; /* Use the same endianness than the current BL */ next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT); /* Set SCTLR Secure EL1 */ next_sctlr |= SCTLR_EL1_RES1; write_sctlr_el1(next_sctlr); } arm-trusted-firmware-1.0-aw-6/bl1/aarch64/bl1_entrypoint.S000066400000000000000000000136761322600646200232240ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include .globl bl1_entrypoint /* ----------------------------------------------------- * bl1_entrypoint() is the entry point into the trusted * firmware code when a cpu is released from warm or * cold reset. * ----------------------------------------------------- */ func bl1_entrypoint /* --------------------------------------------- * Set the CPU endianness before doing anything * that might involve memory reads or writes. * --------------------------------------------- */ mrs x0, sctlr_el3 bic x0, x0, #SCTLR_EE_BIT msr sctlr_el3, x0 isb /* --------------------------------------------- * Perform any processor specific actions upon * reset e.g. cache, tlb invalidations etc. * --------------------------------------------- */ bl reset_handler /* --------------------------------------------- * Enable the instruction cache, stack pointer * and data access alignment checks * --------------------------------------------- */ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el3 orr x0, x0, x1 msr sctlr_el3, x0 isb /* --------------------------------------------- * Set the exception vector to something sane. * --------------------------------------------- */ adr x0, bl1_exceptions msr vbar_el3, x0 isb /* --------------------------------------------- * Enable the SError interrupt now that the * exception vectors have been setup. * --------------------------------------------- */ msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------------------------------- * The initial state of the Architectural feature trap register * (CPTR_EL3) is unknown and it must be set to a known state. All * feature traps are disabled. Some bits in this register are marked as * Reserved and should not be modified. * * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. * CPTR_EL3.TTA: This causes access to the Trace functionality to trap * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register * access to trace functionality is not supported, this bit is RES0. * CPTR_EL3.TFP: This causes instructions that access the registers * associated with Floating Point and Advanced SIMD execution to trap * to EL3 when executed from any exception level, unless trapped to EL1 * or EL2. * --------------------------------------------------------------------- */ mrs x0, cptr_el3 bic w0, w0, #TCPAC_BIT bic w0, w0, #TTA_BIT bic w0, w0, #TFP_BIT msr cptr_el3, x0 /* ------------------------------------------------------- * Will not return from this macro if it is a warm boot. * ------------------------------------------------------- */ wait_for_entrypoint bl platform_mem_init /* --------------------------------------------- * Init C runtime environment. * - Zero-initialise the NOBITS sections. * There are 2 of them: * - the .bss section; * - the coherent memory section. * - Copy the data section from BL1 image * (stored in ROM) to the correct location * in RAM. * --------------------------------------------- */ ldr x0, =__BSS_START__ ldr x1, =__BSS_SIZE__ bl zeromem16 ldr x0, =__COHERENT_RAM_START__ ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ bl zeromem16 ldr x0, =__DATA_RAM_START__ ldr x1, =__DATA_ROM_START__ ldr x2, =__DATA_SIZE__ bl memcpy16 /* -------------------------------------------- * Allocate a stack whose memory will be marked * as Normal-IS-WBWA when the MMU is enabled. * There is no risk of reading stale stack * memory after enabling the MMU as only the * primary cpu is running at the moment. * -------------------------------------------- */ mrs x0, mpidr_el1 bl platform_set_stack /* --------------------------------------------- * Architectural init. can be generic e.g. * enabling stack alignment and platform spec- * ific e.g. MMU & page table setup as per the * platform memory map. Perform the latter here * and the former in bl1_main. * --------------------------------------------- */ bl bl1_early_platform_setup bl bl1_plat_arch_setup /* -------------------------------------------------- * Initialize platform and jump to our c-entry point * for this type of reset. Panic if it returns * -------------------------------------------------- */ bl bl1_main panic: b panic arm-trusted-firmware-1.0-aw-6/bl1/aarch64/bl1_exceptions.S000066400000000000000000000126571322600646200231700ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include .globl bl1_exceptions .section .vectors, "ax"; .align 11 /* ----------------------------------------------------- * Very simple stackless exception handlers used by BL1. * ----------------------------------------------------- */ .align 7 bl1_exceptions: /* ----------------------------------------------------- * Current EL with SP0 : 0x0 - 0x200 * ----------------------------------------------------- */ SynchronousExceptionSP0: mov x0, #SYNC_EXCEPTION_SP_EL0 bl plat_report_exception b SynchronousExceptionSP0 check_vector_size SynchronousExceptionSP0 .align 7 IrqSP0: mov x0, #IRQ_SP_EL0 bl plat_report_exception b IrqSP0 check_vector_size IrqSP0 .align 7 FiqSP0: mov x0, #FIQ_SP_EL0 bl plat_report_exception b FiqSP0 check_vector_size FiqSP0 .align 7 SErrorSP0: mov x0, #SERROR_SP_EL0 bl plat_report_exception b SErrorSP0 check_vector_size SErrorSP0 /* ----------------------------------------------------- * Current EL with SPx: 0x200 - 0x400 * ----------------------------------------------------- */ .align 7 SynchronousExceptionSPx: mov x0, #SYNC_EXCEPTION_SP_ELX bl plat_report_exception b SynchronousExceptionSPx check_vector_size SynchronousExceptionSPx .align 7 IrqSPx: mov x0, #IRQ_SP_ELX bl plat_report_exception b IrqSPx check_vector_size IrqSPx .align 7 FiqSPx: mov x0, #FIQ_SP_ELX bl plat_report_exception b FiqSPx check_vector_size FiqSPx .align 7 SErrorSPx: mov x0, #SERROR_SP_ELX bl plat_report_exception b SErrorSPx check_vector_size SErrorSPx /* ----------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x600 * ----------------------------------------------------- */ .align 7 SynchronousExceptionA64: /* Enable the SError interrupt */ msr daifclr, #DAIF_ABT_BIT /* ------------------------------------------------ * Only a single SMC exception from BL2 to ask * BL1 to pass EL3 control to BL31 is expected * here. * It expects X0 with RUN_IMAGE SMC function id * X1 with address of a entry_point_info_t structure * describing the BL3-1 entrypoint * ------------------------------------------------ */ mov x19, x0 mov x20, x1 mrs x0, esr_el3 ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH cmp x1, #EC_AARCH64_SMC b.ne panic mov x0, #RUN_IMAGE cmp x19, x0 b.ne panic mov x0, x20 bl display_boot_progress ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] msr elr_el3, x0 msr spsr_el3, x1 ubfx x0, x1, #MODE_EL_SHIFT, #2 cmp x0, #MODE_EL3 b.ne panic bl disable_mmu_icache_el3 tlbi alle3 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] eret panic: mov x0, #SYNC_EXCEPTION_AARCH64 bl plat_report_exception wfi b panic check_vector_size SynchronousExceptionA64 .align 7 IrqA64: mov x0, #IRQ_AARCH64 bl plat_report_exception b IrqA64 check_vector_size IrqA64 .align 7 FiqA64: mov x0, #FIQ_AARCH64 bl plat_report_exception b FiqA64 check_vector_size FiqA64 .align 7 SErrorA64: mov x0, #SERROR_AARCH64 bl plat_report_exception b SErrorA64 check_vector_size SErrorA64 /* ----------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x800 * ----------------------------------------------------- */ .align 7 SynchronousExceptionA32: mov x0, #SYNC_EXCEPTION_AARCH32 bl plat_report_exception b SynchronousExceptionA32 check_vector_size SynchronousExceptionA32 .align 7 IrqA32: mov x0, #IRQ_AARCH32 bl plat_report_exception b IrqA32 check_vector_size IrqA32 .align 7 FiqA32: mov x0, #FIQ_AARCH32 bl plat_report_exception b FiqA32 check_vector_size FiqA32 .align 7 SErrorA32: mov x0, #SERROR_AARCH32 bl plat_report_exception b SErrorA32 check_vector_size SErrorA32 arm-trusted-firmware-1.0-aw-6/bl1/bl1.ld.S000066400000000000000000000114711322600646200200660ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) ENTRY(bl1_entrypoint) MEMORY { ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT } SECTIONS { . = BL1_RO_BASE; ASSERT(. == ALIGN(4096), "BL1_RO_BASE address is not aligned on a page boundary.") ro . : { __RO_START__ = .; *bl1_entrypoint.o(.text*) *(.text*) *(.rodata*) /* * Ensure 8-byte alignment for cpu_ops so that its fields are also * aligned. Also ensure cpu_ops inclusion. */ . = ALIGN(8); __CPU_OPS_START__ = .; KEEP(*(cpu_ops)) __CPU_OPS_END__ = .; *(.vectors) __RO_END__ = .; } >ROM ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") /* * The .data section gets copied from ROM to RAM at runtime. * Its LMA must be 16-byte aligned. * Its VMA must be page-aligned as it marks the first read/write page. */ . = BL1_RW_BASE; ASSERT(. == ALIGN(4096), "BL1_RW_BASE address is not aligned on a page boundary.") .data . : ALIGN(16) { __DATA_RAM_START__ = .; *(.data*) __DATA_RAM_END__ = .; } >RAM AT>ROM stacks . (NOLOAD) : { __STACKS_START__ = .; *(tzfw_normal_stacks) __STACKS_END__ = .; } >RAM /* * The .bss section gets initialised to 0 at runtime. * Its base address must be 16-byte aligned. */ .bss : ALIGN(16) { __BSS_START__ = .; *(.bss*) *(COMMON) __BSS_END__ = .; } >RAM /* * The xlat_table section is for full, aligned page tables (4K). * Removing them from .bss avoids forcing 4K alignment on * the .bss section and eliminates the unecessary zero init */ xlat_table (NOLOAD) : { *(xlat_table) } >RAM /* * The base address of the coherent memory section must be page-aligned (4K) * to guarantee that the coherent data are stored on their own pages and * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ coherent_ram (NOLOAD) : ALIGN(4096) { __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ . = NEXT(4096); __COHERENT_RAM_END__ = .; } >RAM __BL1_RAM_START__ = ADDR(.data); __BL1_RAM_END__ = .; __DATA_ROM_START__ = LOADADDR(.data); __DATA_SIZE__ = SIZEOF(.data); /* * The .data section is the last PROGBITS section so its end marks the end * of the read-only part of BL1's binary. */ ASSERT(__DATA_ROM_START__ + __DATA_SIZE__ <= BL1_RO_LIMIT, "BL1's RO section has exceeded its limit.") __BSS_SIZE__ = SIZEOF(.bss); __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") } arm-trusted-firmware-1.0-aw-6/bl1/bl1.mk000066400000000000000000000033211322600646200176700ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # BL1_SOURCES += bl1/bl1_main.c \ bl1/aarch64/bl1_arch_setup.c \ bl1/aarch64/bl1_entrypoint.S \ bl1/aarch64/bl1_exceptions.S \ lib/cpus/aarch64/cpu_helpers.S BL1_LINKERFILE := bl1/bl1.ld.S arm-trusted-firmware-1.0-aw-6/bl1/bl1_main.c000066400000000000000000000160631322600646200205160ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include "bl1_private.h" /******************************************************************************* * Runs BL2 from the given entry point. It results in dropping the * exception level ******************************************************************************/ static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep) { bl1_arch_next_el_setup(); /* Tell next EL what we want done */ bl2_ep->args.arg0 = RUN_IMAGE; if (GET_SECURITY_STATE(bl2_ep->h.attr) == NON_SECURE) change_security_state(GET_SECURITY_STATE(bl2_ep->h.attr)); write_spsr_el3(bl2_ep->spsr); write_elr_el3(bl2_ep->pc); eret(bl2_ep->args.arg0, bl2_ep->args.arg1, bl2_ep->args.arg2, bl2_ep->args.arg3, bl2_ep->args.arg4, bl2_ep->args.arg5, bl2_ep->args.arg6, bl2_ep->args.arg7); } /******************************************************************************* * The next function has a weak definition. Platform specific code can override * it if it wishes to. ******************************************************************************/ #pragma weak bl1_init_bl2_mem_layout /******************************************************************************* * Function that takes a memory layout into which BL2 has been loaded and * populates a new memory layout for BL2 that ensures that BL1's data sections * resident in secure RAM are not visible to BL2. ******************************************************************************/ void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, meminfo_t *bl2_mem_layout) { const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; assert(bl1_mem_layout != NULL); assert(bl2_mem_layout != NULL); /* Check that BL1's memory is lying outside of the free memory */ assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || (BL1_RAM_BASE >= bl1_mem_layout->free_base + bl1_mem_layout->free_size)); /* Remove BL1 RW data from the scope of memory visible to BL2 */ *bl2_mem_layout = *bl1_mem_layout; reserve_mem(&bl2_mem_layout->total_base, &bl2_mem_layout->total_size, BL1_RAM_BASE, bl1_size); flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); } /******************************************************************************* * Function to perform late architectural and platform specific initialization. * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only * called by the primary cpu after a cold boot. * TODO: Add support for alternative image load mechanism e.g using virtio/elf * loader etc. ******************************************************************************/ void bl1_main(void) { /* Announce our arrival */ NOTICE(FIRMWARE_WELCOME_STR); NOTICE("BL1: %s\n", version_string); NOTICE("BL1: %s\n", build_message); INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT); #if DEBUG unsigned long sctlr_el3 = read_sctlr_el3(); #endif image_info_t bl2_image_info = { {0} }; entry_point_info_t bl2_ep = { {0} }; meminfo_t *bl1_tzram_layout; meminfo_t *bl2_tzram_layout = 0x0; int err; /* * Ensure that MMU/Caches and coherency are turned on */ assert(sctlr_el3 | SCTLR_M_BIT); assert(sctlr_el3 | SCTLR_C_BIT); assert(sctlr_el3 | SCTLR_I_BIT); /* Perform remaining generic architectural setup from EL3 */ bl1_arch_setup(); /* Perform platform setup in BL1. */ bl1_platform_setup(); SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0); /* Find out how much free trusted ram remains after BL1 load */ bl1_tzram_layout = bl1_plat_sec_mem_layout(); /* Load the BL2 image */ err = load_image(bl1_tzram_layout, BL2_IMAGE_NAME, BL2_BASE, &bl2_image_info, &bl2_ep); if (err) { /* * TODO: print failure to load BL2 but also add a tzwdog timer * which will reset the system eventually. */ ERROR("Failed to load BL2 firmware.\n"); panic(); } /* * Create a new layout of memory for BL2 as seen by BL1 i.e. * tell it the amount of total and free memory available. * This layout is created at the first free address visible * to BL2. BL2 will read the memory layout before using its * memory for other purposes. */ bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep); bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout; NOTICE("BL1: Booting BL2\n"); INFO("BL1: BL2 address = 0x%llx\n", (unsigned long long) bl2_ep.pc); INFO("BL1: BL2 spsr = 0x%x\n", bl2_ep.spsr); VERBOSE("BL1: BL2 memory layout address = 0x%llx\n", (unsigned long long) bl2_tzram_layout); bl1_run_bl2(&bl2_ep); return; } /******************************************************************************* * Temporary function to print the fact that BL2 has done its job and BL31 is * about to be loaded. This is needed as long as printfs cannot be used ******************************************************************************/ void display_boot_progress(entry_point_info_t *bl31_ep_info) { NOTICE("BL1: Booting BL3-1\n"); INFO("BL1: BL3-1 address = 0x%llx\n", (unsigned long long)bl31_ep_info->pc); INFO("BL1: BL3-1 spsr = 0x%llx\n", (unsigned long long)bl31_ep_info->spsr); INFO("BL1: BL3-1 params address = 0x%llx\n", (unsigned long long)bl31_ep_info->args.arg0); INFO("BL1: BL3-1 plat params address = 0x%llx\n", (unsigned long long)bl31_ep_info->args.arg1); } arm-trusted-firmware-1.0-aw-6/bl1/bl1_private.h000066400000000000000000000043121322600646200212430ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __BL1_PRIVATE_H__ #define __BL1_PRIVATE_H__ /******************************************************************************* * Declarations of linker defined symbols which will tell us where BL1 lives * in Trusted RAM ******************************************************************************/ extern uint64_t __BL1_RAM_START__; extern uint64_t __BL1_RAM_END__; #define BL1_RAM_BASE (uint64_t)(&__BL1_RAM_START__) #define BL1_RAM_LIMIT (uint64_t)(&__BL1_RAM_END__) /****************************************** * Function prototypes *****************************************/ void bl1_arch_setup(void); void bl1_arch_next_el_setup(void); #endif /* __BL1_PRIVATE_H__ */ arm-trusted-firmware-1.0-aw-6/bl2/000077500000000000000000000000001322600646200166635ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/bl2/aarch64/000077500000000000000000000000001322600646200201135ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/bl2/aarch64/bl2_arch_setup.c000066400000000000000000000037331322600646200231610ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include /******************************************************************************* * Place holder function to perform any S-EL1 specific architectural setup. At * the moment there is nothing to do. ******************************************************************************/ void bl2_arch_setup(void) { /* Give access to FP/SIMD registers */ write_cpacr(CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE)); } arm-trusted-firmware-1.0-aw-6/bl2/aarch64/bl2_entrypoint.S000066400000000000000000000077031322600646200232200ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include .globl bl2_entrypoint func bl2_entrypoint /*--------------------------------------------- * Store the extents of the tzram available to * BL2 for future use. Use the opcode param to * allow implement other functions if needed. * --------------------------------------------- */ mov x20, x0 mov x21, x1 /* --------------------------------------------- * Set the exception vector to something sane. * --------------------------------------------- */ adr x0, early_exceptions msr vbar_el1, x0 isb /* --------------------------------------------- * Enable the SError interrupt now that the * exception vectors have been setup. * --------------------------------------------- */ msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer * and data access alignment checks * --------------------------------------------- */ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el1 orr x0, x0, x1 msr sctlr_el1, x0 isb /* --------------------------------------------- * Check the opcodes out of paranoia. * --------------------------------------------- */ mov x0, #RUN_IMAGE cmp x0, x20 b.ne _panic /* --------------------------------------------- * Zero out NOBITS sections. There are 2 of them: * - the .bss section; * - the coherent memory section. * --------------------------------------------- */ ldr x0, =__BSS_START__ ldr x1, =__BSS_SIZE__ bl zeromem16 ldr x0, =__COHERENT_RAM_START__ ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ bl zeromem16 /* -------------------------------------------- * Allocate a stack whose memory will be marked * as Normal-IS-WBWA when the MMU is enabled. * There is no risk of reading stale stack * memory after enabling the MMU as only the * primary cpu is running at the moment. * -------------------------------------------- */ mrs x0, mpidr_el1 bl platform_set_stack /* --------------------------------------------- * Perform early platform setup & platform * specific early arch. setup e.g. mmu setup * --------------------------------------------- */ mov x0, x21 bl bl2_early_platform_setup bl bl2_plat_arch_setup /* --------------------------------------------- * Jump to main function. * --------------------------------------------- */ bl bl2_main _panic: b _panic arm-trusted-firmware-1.0-aw-6/bl2/bl2.ld.S000066400000000000000000000077571322600646200201040ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) ENTRY(bl2_entrypoint) MEMORY { RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT } SECTIONS { . = BL2_BASE; ASSERT(. == ALIGN(4096), "BL2_BASE address is not aligned on a page boundary.") ro . : { __RO_START__ = .; *bl2_entrypoint.o(.text*) *(.text*) *(.rodata*) *(.vectors) __RO_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked as * read-only, executable. No RW data from the next section must * creep in. Ensure the rest of the current memory page is unused. */ . = NEXT(4096); __RO_END__ = .; } >RAM .data . : { __DATA_START__ = .; *(.data*) __DATA_END__ = .; } >RAM stacks (NOLOAD) : { __STACKS_START__ = .; *(tzfw_normal_stacks) __STACKS_END__ = .; } >RAM /* * The .bss section gets initialised to 0 at runtime. * Its base address must be 16-byte aligned. */ .bss : ALIGN(16) { __BSS_START__ = .; *(SORT_BY_ALIGNMENT(.bss*)) *(COMMON) __BSS_END__ = .; } >RAM /* * The xlat_table section is for full, aligned page tables (4K). * Removing them from .bss avoids forcing 4K alignment on * the .bss section and eliminates the unecessary zero init */ xlat_table (NOLOAD) : { *(xlat_table) } >RAM /* * The base address of the coherent memory section must be page-aligned (4K) * to guarantee that the coherent data are stored on their own pages and * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ coherent_ram (NOLOAD) : ALIGN(4096) { __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ . = NEXT(4096); __COHERENT_RAM_END__ = .; } >RAM __BL2_END__ = .; __BSS_SIZE__ = SIZEOF(.bss); __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") } arm-trusted-firmware-1.0-aw-6/bl2/bl2.mk000066400000000000000000000033251322600646200176760ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # BL2_SOURCES += bl2/bl2_main.c \ bl2/aarch64/bl2_entrypoint.S \ bl2/aarch64/bl2_arch_setup.c \ common/aarch64/early_exceptions.S \ lib/locks/exclusive/spinlock.S BL2_LINKERFILE := bl2/bl2.ld.S arm-trusted-firmware-1.0-aw-6/bl2/bl2_main.c000066400000000000000000000171711322600646200205210ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include "bl2_private.h" /******************************************************************************* * Load the BL3-0 image if there's one. * If a platform does not want to attempt to load BL3-0 image it must leave * BL30_BASE undefined. * Return 0 on success or if there's no BL3-0 image to load, a negative error * code otherwise. ******************************************************************************/ static int load_bl30(void) { int e = 0; #ifdef BL30_BASE meminfo_t bl30_mem_info; image_info_t bl30_image_info; /* * It is up to the platform to specify where BL3-0 should be loaded if * it exists. It could create space in the secure sram or point to a * completely different memory. * * The entry point information is not relevant in this case as the AP * won't execute the BL3-0 image. */ INFO("BL2: Loading BL3-0\n"); bl2_plat_get_bl30_meminfo(&bl30_mem_info); e = load_image(&bl30_mem_info, BL30_IMAGE_NAME, BL30_BASE, &bl30_image_info, NULL); if (e == 0) { /* The subsequent handling of BL3-0 is platform specific */ bl2_plat_handle_bl30(&bl30_image_info); } #endif /* BL30_BASE */ return e; } /******************************************************************************* * Load the BL3-1 image. * The bl2_to_bl31_params and bl31_ep_info params will be updated with the * relevant BL3-1 information. * Return 0 on success, a negative error code otherwise. ******************************************************************************/ static int load_bl31(bl31_params_t *bl2_to_bl31_params, entry_point_info_t *bl31_ep_info) { meminfo_t *bl2_tzram_layout; int e; INFO("BL2: Loading BL3-1\n"); assert(bl2_to_bl31_params != NULL); assert(bl31_ep_info != NULL); /* Find out how much free trusted ram remains after BL2 load */ bl2_tzram_layout = bl2_plat_sec_mem_layout(); /* Set the X0 parameter to BL3-1 */ bl31_ep_info->args.arg0 = (unsigned long)bl2_to_bl31_params; /* Load the BL3-1 image */ e = load_image(bl2_tzram_layout, BL31_IMAGE_NAME, BL31_BASE, bl2_to_bl31_params->bl31_image_info, bl31_ep_info); if (e == 0) bl2_plat_set_bl31_ep_info(bl2_to_bl31_params->bl31_image_info, bl31_ep_info); return e; } /******************************************************************************* * Load the BL3-2 image if there's one. * The bl2_to_bl31_params param will be updated with the relevant BL3-2 * information. * If a platform does not want to attempt to load BL3-2 image it must leave * BL32_BASE undefined. * Return 0 on success or if there's no BL3-2 image to load, a negative error * code otherwise. ******************************************************************************/ static int load_bl32(bl31_params_t *bl2_to_bl31_params) { int e = 0; #ifdef BL32_BASE meminfo_t bl32_mem_info; INFO("BL2: Loading BL3-2\n"); assert(bl2_to_bl31_params != NULL); /* * It is up to the platform to specify where BL3-2 should be loaded if * it exists. It could create space in the secure sram or point to a * completely different memory. */ bl2_plat_get_bl32_meminfo(&bl32_mem_info); e = load_image(&bl32_mem_info, BL32_IMAGE_NAME, BL32_BASE, bl2_to_bl31_params->bl32_image_info, bl2_to_bl31_params->bl32_ep_info); if (e == 0) { bl2_plat_set_bl32_ep_info( bl2_to_bl31_params->bl32_image_info, bl2_to_bl31_params->bl32_ep_info); } #endif /* BL32_BASE */ return e; } /******************************************************************************* * Load the BL3-3 image. * The bl2_to_bl31_params param will be updated with the relevant BL3-3 * information. * Return 0 on success, a negative error code otherwise. ******************************************************************************/ static int load_bl33(bl31_params_t *bl2_to_bl31_params) { meminfo_t bl33_mem_info; int e; INFO("BL2: Loading BL3-3\n"); assert(bl2_to_bl31_params != NULL); bl2_plat_get_bl33_meminfo(&bl33_mem_info); /* Load the BL3-3 image in non-secure memory provided by the platform */ e = load_image(&bl33_mem_info, BL33_IMAGE_NAME, plat_get_ns_image_entrypoint(), bl2_to_bl31_params->bl33_image_info, bl2_to_bl31_params->bl33_ep_info); if (e == 0) bl2_plat_set_bl33_ep_info(bl2_to_bl31_params->bl33_image_info, bl2_to_bl31_params->bl33_ep_info); return e; } /******************************************************************************* * The only thing to do in BL2 is to load further images and pass control to * BL3-1. The memory occupied by BL2 will be reclaimed by BL3-x stages. BL2 runs * entirely in S-EL1. ******************************************************************************/ void bl2_main(void) { bl31_params_t *bl2_to_bl31_params; entry_point_info_t *bl31_ep_info; int e; NOTICE("BL2: %s\n", version_string); NOTICE("BL2: %s\n", build_message); /* Perform remaining generic architectural setup in S-EL1 */ bl2_arch_setup(); /* Perform platform setup in BL2 */ bl2_platform_setup(); /* * Load the subsequent bootloader images */ e = load_bl30(); if (e) { ERROR("Failed to load BL3-0 (%i)\n", e); panic(); } /* * Get a pointer to the memory the platform has set aside to pass * information to BL3-1. */ bl2_to_bl31_params = bl2_plat_get_bl31_params(); bl31_ep_info = bl2_plat_get_bl31_ep_info(); e = load_bl31(bl2_to_bl31_params, bl31_ep_info); if (e) { ERROR("Failed to load BL3-1 (%i)\n", e); panic(); } e = load_bl32(bl2_to_bl31_params); if (e) WARN("Failed to load BL3-2 (%i)\n", e); e = load_bl33(bl2_to_bl31_params); if (e) { ERROR("Failed to load BL3-3 (%i)\n", e); panic(); } /* Flush the params to be passed to memory */ bl2_plat_flush_bl31_params(); /* * Run BL3-1 via an SMC to BL1. Information on how to pass control to * the BL3-2 (if present) and BL3-3 software images will be passed to * BL3-1 as an argument. */ smc(RUN_IMAGE, (unsigned long)bl31_ep_info, 0, 0, 0, 0, 0, 0); } arm-trusted-firmware-1.0-aw-6/bl2/bl2_private.h000066400000000000000000000033721322600646200212520ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __BL2_PRIVATE_H__ #define __BL2_PRIVATE_H__ /****************************************** * Function prototypes *****************************************/ void bl2_arch_setup(void); #endif /* __BL2_PRIVATE_H__ */ arm-trusted-firmware-1.0-aw-6/bl31/000077500000000000000000000000001322600646200167455ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/bl31/aarch64/000077500000000000000000000000001322600646200201755ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/bl31/aarch64/bl31_arch_setup.c000066400000000000000000000043301322600646200233170ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include /******************************************************************************* * This duplicates what the primary cpu did after a cold boot in BL1. The same * needs to be done when a cpu is hotplugged in. This function could also over- * ride any EL3 setup done by BL1 as this code resides in rw memory. ******************************************************************************/ void bl31_arch_setup(void) { /* Set the RES1 bits in the SCR_EL3 */ write_scr_el3(SCR_RES1_BITS); /* Program the counter frequency */ write_cntfrq_el0(plat_get_syscnt_freq()); } arm-trusted-firmware-1.0-aw-6/bl31/aarch64/bl31_entrypoint.S000066400000000000000000000155261322600646200233660ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include .globl bl31_entrypoint /* ----------------------------------------------------- * bl31_entrypoint() is the cold boot entrypoint, * executed only by the primary cpu. * ----------------------------------------------------- */ func bl31_entrypoint b code_start nop /* align to 8 bytes */ .byte 0x05, 0x00, 0x00, 0xe0, 0x00, 0x04, 0x02, 0xa8 /* l.xor r0, r0, r0 l.ori r1, r0, 0xc0 */ .byte 0x00, 0x80, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x15 /* l.mtspr r0, r1, 0x4000 l.nop */ /* --------------------------------------------------------------- * Preceding bootloader has populated x0 with a pointer to a * 'bl31_params' structure & x1 with a pointer to platform * specific structure * --------------------------------------------------------------- */ code_start: #if !RESET_TO_BL31 mov w20, w0 mov w21, w1 #else /* --------------------------------------------- * Set the CPU endianness before doing anything * that might involve memory reads or writes. * --------------------------------------------- */ mrs x0, sctlr_el3 bic x0, x0, #SCTLR_EE_BIT msr sctlr_el3, x0 isb /* ----------------------------------------------------- * Perform any processor specific actions upon reset * e.g. cache, tlb invalidations etc. Override the * Boot ROM(BL0) programming sequence * ----------------------------------------------------- */ bl reset_handler #endif /* --------------------------------------------- * Enable the instruction cache, stack pointer * and data access alignment checks * --------------------------------------------- */ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el3 orr x0, x0, x1 msr sctlr_el3, x0 isb /* --------------------------------------------- * Initialise cpu_data early to enable crash * reporting to have access to crash stack. * Since crash reporting depends on cpu_data to * report the unhandled exception, not * doing so can lead to recursive exceptions due * to a NULL TPIDR_EL3 * --------------------------------------------- */ bl init_cpu_data_ptr /* --------------------------------------------- * Set the exception vector. * --------------------------------------------- */ adr x1, runtime_exceptions msr vbar_el3, x1 isb /* --------------------------------------------- * Enable the SError interrupt now that the * exception vectors have been setup. * --------------------------------------------- */ msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------------------------------- * The initial state of the Architectural feature trap register * (CPTR_EL3) is unknown and it must be set to a known state. All * feature traps are disabled. Some bits in this register are marked as * Reserved and should not be modified. * * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. * CPTR_EL3.TTA: This causes access to the Trace functionality to trap * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register * access to trace functionality is not supported, this bit is RES0. * CPTR_EL3.TFP: This causes instructions that access the registers * associated with Floating Point and Advanced SIMD execution to trap * to EL3 when executed from any exception level, unless trapped to EL1 * or EL2. * --------------------------------------------------------------------- */ mrs x1, cptr_el3 bic w1, w1, #TCPAC_BIT bic w1, w1, #TTA_BIT bic w1, w1, #TFP_BIT msr cptr_el3, x1 #if RESET_TO_BL31 /* ------------------------------------------------------- * Will not return from this macro if it is a warm boot. * ------------------------------------------------------- */ wait_for_entrypoint bl platform_mem_init #endif /* --------------------------------------------- * Zero out NOBITS sections. There are 2 of them: * - the .bss section; * - the coherent memory section. * --------------------------------------------- */ ldr x0, =__BSS_START__ ldr x1, =__BSS_SIZE__ bl zeromem16 ldr x0, =__COHERENT_RAM_START__ ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ bl zeromem16 /* --------------------------------------------- * Initialize the cpu_ops pointer. * --------------------------------------------- */ bl init_cpu_ops /* --------------------------------------------- * Use SP_EL0 for the C runtime stack. * --------------------------------------------- */ msr spsel, #0 /* -------------------------------------------- * Allocate a stack whose memory will be marked * as Normal-IS-WBWA when the MMU is enabled. * There is no risk of reading stale stack * memory after enabling the MMU as only the * primary cpu is running at the moment. * -------------------------------------------- */ mrs x0, mpidr_el1 bl platform_set_stack /* --------------------------------------------- * Perform platform specific early arch. setup * --------------------------------------------- */ #if RESET_TO_BL31 mov x0, 0 mov x1, 0 #else mov x0, x20 mov x1, x21 #endif bl bl31_early_platform_setup bl bl31_plat_arch_setup /* --------------------------------------------- * Jump to main function. * --------------------------------------------- */ bl bl31_main b el3_exit arm-trusted-firmware-1.0-aw-6/bl31/aarch64/context.S000066400000000000000000000200701322600646200220040ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include /* ----------------------------------------------------- * The following function strictly follows the AArch64 * PCS to use x9-x17 (temporary caller-saved registers) * to save EL1 system register context. It assumes that * 'x0' is pointing to a 'el1_sys_regs' structure where * the register context will be saved. * ----------------------------------------------------- */ .global el1_sysregs_context_save func el1_sysregs_context_save mrs x9, spsr_el1 mrs x10, elr_el1 stp x9, x10, [x0, #CTX_SPSR_EL1] mrs x11, spsr_abt mrs x12, spsr_und stp x11, x12, [x0, #CTX_SPSR_ABT] mrs x13, spsr_irq mrs x14, spsr_fiq stp x13, x14, [x0, #CTX_SPSR_IRQ] mrs x15, sctlr_el1 mrs x16, actlr_el1 stp x15, x16, [x0, #CTX_SCTLR_EL1] mrs x17, cpacr_el1 mrs x9, csselr_el1 stp x17, x9, [x0, #CTX_CPACR_EL1] mrs x10, sp_el1 mrs x11, esr_el1 stp x10, x11, [x0, #CTX_SP_EL1] mrs x12, ttbr0_el1 mrs x13, ttbr1_el1 stp x12, x13, [x0, #CTX_TTBR0_EL1] mrs x14, mair_el1 mrs x15, amair_el1 stp x14, x15, [x0, #CTX_MAIR_EL1] mrs x16, tcr_el1 mrs x17, tpidr_el1 stp x16, x17, [x0, #CTX_TCR_EL1] mrs x9, tpidr_el0 mrs x10, tpidrro_el0 stp x9, x10, [x0, #CTX_TPIDR_EL0] mrs x11, dacr32_el2 mrs x12, ifsr32_el2 stp x11, x12, [x0, #CTX_DACR32_EL2] mrs x13, par_el1 mrs x14, far_el1 stp x13, x14, [x0, #CTX_PAR_EL1] mrs x15, afsr0_el1 mrs x16, afsr1_el1 stp x15, x16, [x0, #CTX_AFSR0_EL1] mrs x17, contextidr_el1 mrs x9, vbar_el1 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] /* Save NS timer registers if the build has instructed so */ #if NS_TIMER_SWITCH mrs x10, cntp_ctl_el0 mrs x11, cntp_cval_el0 stp x10, x11, [x0, #CTX_CNTP_CTL_EL0] mrs x12, cntv_ctl_el0 mrs x13, cntv_cval_el0 stp x12, x13, [x0, #CTX_CNTV_CTL_EL0] mrs x14, cntkctl_el1 str x14, [x0, #CTX_CNTKCTL_EL1] #endif mrs x15, fpexc32_el2 str x15, [x0, #CTX_FP_FPEXC32_EL2] ret /* ----------------------------------------------------- * The following function strictly follows the AArch64 * PCS to use x9-x17 (temporary caller-saved registers) * to restore EL1 system register context. It assumes * that 'x0' is pointing to a 'el1_sys_regs' structure * from where the register context will be restored * ----------------------------------------------------- */ .global el1_sysregs_context_restore func el1_sysregs_context_restore ldp x9, x10, [x0, #CTX_SPSR_EL1] msr spsr_el1, x9 msr elr_el1, x10 ldp x11, x12, [x0, #CTX_SPSR_ABT] msr spsr_abt, x11 msr spsr_und, x12 ldp x13, x14, [x0, #CTX_SPSR_IRQ] msr spsr_irq, x13 msr spsr_fiq, x14 ldp x15, x16, [x0, #CTX_SCTLR_EL1] msr sctlr_el1, x15 msr actlr_el1, x16 ldp x17, x9, [x0, #CTX_CPACR_EL1] msr cpacr_el1, x17 msr csselr_el1, x9 ldp x10, x11, [x0, #CTX_SP_EL1] msr sp_el1, x10 msr esr_el1, x11 ldp x12, x13, [x0, #CTX_TTBR0_EL1] msr ttbr0_el1, x12 msr ttbr1_el1, x13 ldp x14, x15, [x0, #CTX_MAIR_EL1] msr mair_el1, x14 msr amair_el1, x15 ldp x16, x17, [x0, #CTX_TCR_EL1] msr tcr_el1, x16 msr tpidr_el1, x17 ldp x9, x10, [x0, #CTX_TPIDR_EL0] msr tpidr_el0, x9 msr tpidrro_el0, x10 ldp x11, x12, [x0, #CTX_DACR32_EL2] msr dacr32_el2, x11 msr ifsr32_el2, x12 ldp x13, x14, [x0, #CTX_PAR_EL1] msr par_el1, x13 msr far_el1, x14 ldp x15, x16, [x0, #CTX_AFSR0_EL1] msr afsr0_el1, x15 msr afsr1_el1, x16 ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] msr contextidr_el1, x17 msr vbar_el1, x9 /* Restore NS timer registers if the build has instructed so */ #if NS_TIMER_SWITCH ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] msr cntp_ctl_el0, x10 msr cntp_cval_el0, x11 ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0] msr cntv_ctl_el0, x12 msr cntv_cval_el0, x13 ldr x14, [x0, #CTX_CNTKCTL_EL1] msr cntkctl_el1, x14 #endif ldr x15, [x0, #CTX_FP_FPEXC32_EL2] msr fpexc32_el2, x15 /* No explict ISB required here as ERET covers it */ ret /* ----------------------------------------------------- * The following function follows the aapcs_64 strictly * to use x9-x17 (temporary caller-saved registers * according to AArch64 PCS) to save floating point * register context. It assumes that 'x0' is pointing to * a 'fp_regs' structure where the register context will * be saved. * * Access to VFP registers will trap if CPTR_EL3.TFP is * set. However currently we don't use VFP registers * nor set traps in Trusted Firmware, and assume it's * cleared * * TODO: Revisit when VFP is used in secure world * ----------------------------------------------------- */ #if CTX_INCLUDE_FPREGS .global fpregs_context_save func fpregs_context_save stp q0, q1, [x0, #CTX_FP_Q0] stp q2, q3, [x0, #CTX_FP_Q2] stp q4, q5, [x0, #CTX_FP_Q4] stp q6, q7, [x0, #CTX_FP_Q6] stp q8, q9, [x0, #CTX_FP_Q8] stp q10, q11, [x0, #CTX_FP_Q10] stp q12, q13, [x0, #CTX_FP_Q12] stp q14, q15, [x0, #CTX_FP_Q14] stp q16, q17, [x0, #CTX_FP_Q16] stp q18, q19, [x0, #CTX_FP_Q18] stp q20, q21, [x0, #CTX_FP_Q20] stp q22, q23, [x0, #CTX_FP_Q22] stp q24, q25, [x0, #CTX_FP_Q24] stp q26, q27, [x0, #CTX_FP_Q26] stp q28, q29, [x0, #CTX_FP_Q28] stp q30, q31, [x0, #CTX_FP_Q30] mrs x9, fpsr str x9, [x0, #CTX_FP_FPSR] mrs x10, fpcr str x10, [x0, #CTX_FP_FPCR] ret /* ----------------------------------------------------- * The following function follows the aapcs_64 strictly * to use x9-x17 (temporary caller-saved registers * according to AArch64 PCS) to restore floating point * register context. It assumes that 'x0' is pointing to * a 'fp_regs' structure from where the register context * will be restored. * * Access to VFP registers will trap if CPTR_EL3.TFP is * set. However currently we don't use VFP registers * nor set traps in Trusted Firmware, and assume it's * cleared * * TODO: Revisit when VFP is used in secure world * ----------------------------------------------------- */ .global fpregs_context_restore func fpregs_context_restore ldp q0, q1, [x0, #CTX_FP_Q0] ldp q2, q3, [x0, #CTX_FP_Q2] ldp q4, q5, [x0, #CTX_FP_Q4] ldp q6, q7, [x0, #CTX_FP_Q6] ldp q8, q9, [x0, #CTX_FP_Q8] ldp q10, q11, [x0, #CTX_FP_Q10] ldp q12, q13, [x0, #CTX_FP_Q12] ldp q14, q15, [x0, #CTX_FP_Q14] ldp q16, q17, [x0, #CTX_FP_Q16] ldp q18, q19, [x0, #CTX_FP_Q18] ldp q20, q21, [x0, #CTX_FP_Q20] ldp q22, q23, [x0, #CTX_FP_Q22] ldp q24, q25, [x0, #CTX_FP_Q24] ldp q26, q27, [x0, #CTX_FP_Q26] ldp q28, q29, [x0, #CTX_FP_Q28] ldp q30, q31, [x0, #CTX_FP_Q30] ldr x9, [x0, #CTX_FP_FPSR] msr fpsr, x9 str x10, [x0, #CTX_FP_FPCR] msr fpcr, x10 /* * No explict ISB required here as ERET to * swtich to secure EL1 or non-secure world * covers it */ ret #endif /* CTX_INCLUDE_FPREGS */ arm-trusted-firmware-1.0-aw-6/bl31/aarch64/cpu_data.S000066400000000000000000000060431322600646200221040ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include .globl init_cpu_data_ptr .globl _cpu_data_by_mpidr .globl _cpu_data_by_index /* ----------------------------------------------------------------- * void init_cpu_data_ptr(void) * * Initialise the TPIDR_EL3 register to refer to the cpu_data_t * for the calling CPU. This must be called before cm_get_cpu_data() * * This can be called without a valid stack. * clobbers: x0, x1, x9, x10 * ----------------------------------------------------------------- */ func init_cpu_data_ptr mov x10, x30 mrs x0, mpidr_el1 bl _cpu_data_by_mpidr msr tpidr_el3, x0 ret x10 /* ----------------------------------------------------------------- * cpu_data_t *_cpu_data_by_mpidr(uint64_t mpidr) * * Return the cpu_data structure for the CPU with given MPIDR * * This can be called without a valid stack. It assumes that * platform_get_core_pos() does not clobber register x9. * clobbers: x0, x1, x9 * ----------------------------------------------------------------- */ func _cpu_data_by_mpidr mov x9, x30 bl platform_get_core_pos mov x30, x9 b _cpu_data_by_index /* ----------------------------------------------------------------- * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index) * * Return the cpu_data structure for the CPU with given linear index * * This can be called without a valid stack. * clobbers: x0, x1 * ----------------------------------------------------------------- */ func _cpu_data_by_index adr x1, percpu_data add x0, x1, x0, LSL #CPU_DATA_LOG2SIZE ret arm-trusted-firmware-1.0-aw-6/bl31/aarch64/crash_reporting.S000066400000000000000000000256621322600646200235250ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include .globl report_unhandled_exception .globl report_unhandled_interrupt .globl el3_panic #if CRASH_REPORTING #define REG_SIZE 0x8 /* ------------------------------------------------------ * The below section deals with dumping the system state * when an unhandled exception is taken in EL3. * The layout and the names of the registers which will * be dumped during a unhandled exception is given below. * ------------------------------------------------------ */ .section .rodata.crash_prints, "aS" print_spacer: .asciz " =\t\t0x" gp_regs: .asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",\ "x16", "x17", "x18", "x19", "x20", "x21", "x22",\ "x23", "x24", "x25", "x26", "x27", "x28", "x29", "" el3_sys_regs: .asciz "scr_el3", "sctlr_el3", "cptr_el3", "tcr_el3",\ "daif", "mair_el3", "spsr_el3", "elr_el3", "ttbr0_el3",\ "esr_el3", "far_el3", "" non_el3_sys_regs: .asciz "spsr_el1", "elr_el1", "spsr_abt", "spsr_und",\ "spsr_irq", "spsr_fiq", "sctlr_el1", "actlr_el1", "cpacr_el1",\ "csselr_el1", "sp_el1", "esr_el1", "ttbr0_el1", "ttbr1_el1",\ "mair_el1", "amair_el1", "tcr_el1", "tpidr_el1", "tpidr_el0",\ "tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\ "mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\ "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\ "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0", "" panic_msg: .asciz "PANIC in EL3 at x30 = 0x" excpt_msg: .asciz "Unhandled Exception in EL3.\nx30 =\t\t0x" intr_excpt_msg: .asciz "Unhandled Interrupt Exception in EL3.\nx30 =\t\t0x" /* * Helper function to print newline to console. */ func print_newline mov x0, '\n' b plat_crash_console_putc /* * Helper function to print from crash buf. * The print loop is controlled by the buf size and * ascii reg name list which is passed in x6. The * function returns the crash buf address in x0. * Clobbers : x0 - x7, sp */ func size_controlled_print /* Save the lr */ mov sp, x30 /* load the crash buf address */ mrs x7, tpidr_el3 test_size_list: /* Calculate x5 always as it will be clobbered by asm_print_hex */ mrs x5, tpidr_el3 add x5, x5, #CPU_DATA_CRASH_BUF_SIZE /* Test whether we have reached end of crash buf */ cmp x7, x5 b.eq exit_size_print ldrb w4, [x6] /* Test whether we are at end of list */ cbz w4, exit_size_print mov x4, x6 /* asm_print_str updates x4 to point to next entry in list */ bl asm_print_str /* update x6 with the updated list pointer */ mov x6, x4 adr x4, print_spacer bl asm_print_str ldr x4, [x7], #REG_SIZE bl asm_print_hex bl print_newline b test_size_list exit_size_print: mov x30, sp ret /* * Helper function to store x8 - x15 registers to * the crash buf. The system registers values are * copied to x8 to x15 by the caller which are then * copied to the crash buf by this function. * x0 points to the crash buf. It then calls * size_controlled_print to print to console. * Clobbers : x0 - x7, sp */ func str_in_crash_buf_print /* restore the crash buf address in x0 */ mrs x0, tpidr_el3 stp x8, x9, [x0] stp x10, x11, [x0, #REG_SIZE * 2] stp x12, x13, [x0, #REG_SIZE * 4] stp x14, x15, [x0, #REG_SIZE * 6] b size_controlled_print /* ------------------------------------------------------ * This macro calculates the offset to crash buf from * cpu_data and stores it in tpidr_el3. It also saves x0 * and x1 in the crash buf by using sp as a temporary * register. * ------------------------------------------------------ */ .macro prepare_crash_buf_save_x0_x1 /* we can corrupt this reg to free up x0 */ mov sp, x0 /* tpidr_el3 contains the address to cpu_data structure */ mrs x0, tpidr_el3 /* Calculate the Crash buffer offset in cpu_data */ add x0, x0, #CPU_DATA_CRASH_BUF_OFFSET /* Store crash buffer address in tpidr_el3 */ msr tpidr_el3, x0 str x1, [x0, #REG_SIZE] mov x1, sp str x1, [x0] .endm /* ----------------------------------------------------- * This function allows to report a crash (if crash * reporting is enabled) when an unhandled exception * occurs. It prints the CPU state via the crash console * making use of the crash buf. This function will * not return. * ----------------------------------------------------- */ func report_unhandled_exception prepare_crash_buf_save_x0_x1 adr x0, excpt_msg mov sp, x0 /* This call will not return */ b do_crash_reporting /* ----------------------------------------------------- * This function allows to report a crash (if crash * reporting is enabled) when an unhandled interrupt * occurs. It prints the CPU state via the crash console * making use of the crash buf. This function will * not return. * ----------------------------------------------------- */ func report_unhandled_interrupt prepare_crash_buf_save_x0_x1 adr x0, intr_excpt_msg mov sp, x0 /* This call will not return */ b do_crash_reporting /* ----------------------------------------------------- * This function allows to report a crash (if crash * reporting is enabled) when panic() is invoked from * C Runtime. It prints the CPU state via the crash * console making use of the crash buf. This function * will not return. * ----------------------------------------------------- */ func el3_panic msr spsel, #1 prepare_crash_buf_save_x0_x1 adr x0, panic_msg mov sp, x0 /* This call will not return */ b do_crash_reporting /* ------------------------------------------------------------ * The common crash reporting functionality. It requires x0 * and x1 has already been stored in crash buf, sp points to * crash message and tpidr_el3 contains the crash buf address. * The function does the following: * - Retrieve the crash buffer from tpidr_el3 * - Store x2 to x6 in the crash buffer * - Initialise the crash console. * - Print the crash message by using the address in sp. * - Print x30 value to the crash console. * - Print x0 - x7 from the crash buf to the crash console. * - Print x8 - x29 (in groups of 8 registers) using the * crash buf to the crash console. * - Print el3 sys regs (in groups of 8 registers) using the * crash buf to the crash console. * - Print non el3 sys regs (in groups of 8 registers) using * the crash buf to the crash console. * ------------------------------------------------------------ */ func do_crash_reporting /* Retrieve the crash buf from tpidr_el3 */ mrs x0, tpidr_el3 /* Store x2 - x6, x30 in the crash buffer */ stp x2, x3, [x0, #REG_SIZE * 2] stp x4, x5, [x0, #REG_SIZE * 4] stp x6, x30, [x0, #REG_SIZE * 6] /* Initialize the crash console */ bl plat_crash_console_init /* Verify the console is initialized */ cbz x0, crash_panic /* Print the crash message. sp points to the crash message */ mov x4, sp bl asm_print_str /* load the crash buf address */ mrs x0, tpidr_el3 /* report x30 first from the crash buf */ ldr x4, [x0, #REG_SIZE * 7] bl asm_print_hex bl print_newline /* Load the crash buf address */ mrs x0, tpidr_el3 /* Now mov x7 into crash buf */ str x7, [x0, #REG_SIZE * 7] /* Report x0 - x29 values stored in crash buf*/ /* Store the ascii list pointer in x6 */ adr x6, gp_regs /* Print x0 to x7 from the crash buf */ bl size_controlled_print /* Store x8 - x15 in crash buf and print */ bl str_in_crash_buf_print /* Load the crash buf address */ mrs x0, tpidr_el3 /* Store the rest of gp regs and print */ stp x16, x17, [x0] stp x18, x19, [x0, #REG_SIZE * 2] stp x20, x21, [x0, #REG_SIZE * 4] stp x22, x23, [x0, #REG_SIZE * 6] bl size_controlled_print /* Load the crash buf address */ mrs x0, tpidr_el3 stp x24, x25, [x0] stp x26, x27, [x0, #REG_SIZE * 2] stp x28, x29, [x0, #REG_SIZE * 4] bl size_controlled_print /* Print the el3 sys registers */ adr x6, el3_sys_regs mrs x8, scr_el3 mrs x9, sctlr_el3 mrs x10, cptr_el3 mrs x11, tcr_el3 mrs x12, daif mrs x13, mair_el3 mrs x14, spsr_el3 mrs x15, elr_el3 bl str_in_crash_buf_print mrs x8, ttbr0_el3 mrs x9, esr_el3 mrs x10, far_el3 bl str_in_crash_buf_print /* Print the non el3 sys registers */ adr x6, non_el3_sys_regs mrs x8, spsr_el1 mrs x9, elr_el1 mrs x10, spsr_abt mrs x11, spsr_und mrs x12, spsr_irq mrs x13, spsr_fiq mrs x14, sctlr_el1 mrs x15, actlr_el1 bl str_in_crash_buf_print mrs x8, cpacr_el1 mrs x9, csselr_el1 mrs x10, sp_el1 mrs x11, esr_el1 mrs x12, ttbr0_el1 mrs x13, ttbr1_el1 mrs x14, mair_el1 mrs x15, amair_el1 bl str_in_crash_buf_print mrs x8, tcr_el1 mrs x9, tpidr_el1 mrs x10, tpidr_el0 mrs x11, tpidrro_el0 mrs x12, dacr32_el2 mrs x13, ifsr32_el2 mrs x14, par_el1 mrs x15, mpidr_el1 bl str_in_crash_buf_print mrs x8, afsr0_el1 mrs x9, afsr1_el1 mrs x10, contextidr_el1 mrs x11, vbar_el1 mrs x12, cntp_ctl_el0 mrs x13, cntp_cval_el0 mrs x14, cntv_ctl_el0 mrs x15, cntv_cval_el0 bl str_in_crash_buf_print mrs x8, cntkctl_el1 mrs x9, fpexc32_el2 mrs x10, sp_el0 bl str_in_crash_buf_print /* Get the cpu specific registers to report */ bl do_cpu_reg_dump bl str_in_crash_buf_print /* Print the gic registers */ plat_print_gic_regs /* Print the interconnect registers */ plat_print_interconnect_regs /* Done reporting */ b crash_panic #else /* CRASH_REPORTING */ func report_unhandled_exception report_unhandled_interrupt: b crash_panic #endif /* CRASH_REPORING */ func crash_panic b crash_panic arm-trusted-firmware-1.0-aw-6/bl31/aarch64/runtime_exceptions.S000066400000000000000000000416351322600646200242560ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include .globl runtime_exceptions .globl el3_exit /* ----------------------------------------------------- * Handle SMC exceptions separately from other sync. * exceptions. * ----------------------------------------------------- */ .macro handle_sync_exception /* Enable the SError interrupt */ msr daifclr, #DAIF_ABT_BIT str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] mrs x30, esr_el3 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH cmp x30, #EC_AARCH32_SMC b.eq smc_handler32 cmp x30, #EC_AARCH64_SMC b.eq smc_handler64 /* ----------------------------------------------------- * The following code handles any synchronous exception * that is not an SMC. * ----------------------------------------------------- */ bl report_unhandled_exception .endm /* ----------------------------------------------------- * This macro handles FIQ or IRQ interrupts i.e. EL3, * S-EL1 and NS interrupts. * ----------------------------------------------------- */ .macro handle_interrupt_exception label /* Enable the SError interrupt */ msr daifclr, #DAIF_ABT_BIT str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] bl save_gp_registers /* Switch to the runtime stack i.e. SP_EL0 */ ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] mov x20, sp msr spsel, #0 mov sp, x2 /* * Find out whether this is a valid interrupt type. If the * interrupt controller reports a spurious interrupt then * return to where we came from. */ bl plat_ic_get_pending_interrupt_type cmp x0, #INTR_TYPE_INVAL b.eq interrupt_exit_\label /* * Get the registered handler for this interrupt type. A * NULL return value implies that an interrupt was generated * for which there is no handler registered or the interrupt * was routed incorrectly. This is a problem of the framework * so report it as an error. */ bl get_interrupt_type_handler cbz x0, interrupt_error_\label mov x21, x0 mov x0, #INTR_ID_UNAVAILABLE #if IMF_READ_INTERRUPT_ID /* * Read the id of the highest priority pending interrupt. If * no interrupt is asserted then return to where we came from. */ mov x19, #INTR_ID_UNAVAILABLE bl plat_ic_get_pending_interrupt_id cmp x19, x0 b.eq interrupt_exit_\label #endif /* * Save the EL3 system registers needed to return from * this exception. */ mrs x3, spsr_el3 mrs x4, elr_el3 stp x3, x4, [x20, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] /* Set the current security state in the 'flags' parameter */ mrs x2, scr_el3 ubfx x1, x2, #0, #1 /* Restore the reference to the 'handle' i.e. SP_EL3 */ mov x2, x20 /* x3 will point to a cookie (not used now) */ mov x3, xzr /* Call the interrupt type handler */ blr x21 interrupt_exit_\label: /* Return from exception, possibly in a different security state */ b el3_exit /* * This label signifies a problem with the interrupt management * framework where it is not safe to go back to the instruction * where the interrupt was generated. */ interrupt_error_\label: bl report_unhandled_interrupt .endm .macro save_x18_to_x29_sp_el0 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] mrs x18, sp_el0 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] .endm .section .vectors, "ax"; .align 11 .align 7 runtime_exceptions: /* ----------------------------------------------------- * Current EL with _sp_el0 : 0x0 - 0x200 * ----------------------------------------------------- */ sync_exception_sp_el0: /* ----------------------------------------------------- * We don't expect any synchronous exceptions from EL3 * ----------------------------------------------------- */ bl report_unhandled_exception check_vector_size sync_exception_sp_el0 .align 7 /* ----------------------------------------------------- * EL3 code is non-reentrant. Any asynchronous exception * is a serious error. Loop infinitely. * ----------------------------------------------------- */ irq_sp_el0: bl report_unhandled_interrupt check_vector_size irq_sp_el0 .align 7 fiq_sp_el0: bl report_unhandled_interrupt check_vector_size fiq_sp_el0 .align 7 serror_sp_el0: bl report_unhandled_exception check_vector_size serror_sp_el0 /* ----------------------------------------------------- * Current EL with SPx: 0x200 - 0x400 * ----------------------------------------------------- */ .align 7 sync_exception_sp_elx: /* ----------------------------------------------------- * This exception will trigger if anything went wrong * during a previous exception entry or exit or while * handling an earlier unexpected synchronous exception. * There is a high probability that SP_EL3 is corrupted. * ----------------------------------------------------- */ bl report_unhandled_exception check_vector_size sync_exception_sp_elx .align 7 irq_sp_elx: bl report_unhandled_interrupt check_vector_size irq_sp_elx .align 7 fiq_sp_elx: bl report_unhandled_interrupt check_vector_size fiq_sp_elx .align 7 serror_sp_elx: bl report_unhandled_exception check_vector_size serror_sp_elx /* ----------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x600 * ----------------------------------------------------- */ .align 7 sync_exception_aarch64: /* ----------------------------------------------------- * This exception vector will be the entry point for * SMCs and traps that are unhandled at lower ELs most * commonly. SP_EL3 should point to a valid cpu context * where the general purpose and system register state * can be saved. * ----------------------------------------------------- */ handle_sync_exception check_vector_size sync_exception_aarch64 .align 7 /* ----------------------------------------------------- * Asynchronous exceptions from lower ELs are not * currently supported. Report their occurrence. * ----------------------------------------------------- */ irq_aarch64: handle_interrupt_exception irq_aarch64 check_vector_size irq_aarch64 .align 7 fiq_aarch64: handle_interrupt_exception fiq_aarch64 check_vector_size fiq_aarch64 .align 7 serror_aarch64: bl report_unhandled_exception check_vector_size serror_aarch64 /* ----------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x800 * ----------------------------------------------------- */ .align 7 sync_exception_aarch32: /* ----------------------------------------------------- * This exception vector will be the entry point for * SMCs and traps that are unhandled at lower ELs most * commonly. SP_EL3 should point to a valid cpu context * where the general purpose and system register state * can be saved. * ----------------------------------------------------- */ handle_sync_exception check_vector_size sync_exception_aarch32 .align 7 /* ----------------------------------------------------- * Asynchronous exceptions from lower ELs are not * currently supported. Report their occurrence. * ----------------------------------------------------- */ irq_aarch32: handle_interrupt_exception irq_aarch32 check_vector_size irq_aarch32 .align 7 fiq_aarch32: handle_interrupt_exception fiq_aarch32 check_vector_size fiq_aarch32 .align 7 serror_aarch32: bl report_unhandled_exception check_vector_size serror_aarch32 .align 7 /* ----------------------------------------------------- * The following code handles secure monitor calls. * Depending upon the execution state from where the SMC * has been invoked, it frees some general purpose * registers to perform the remaining tasks. They * involve finding the runtime service handler that is * the target of the SMC & switching to runtime stacks * (SP_EL0) before calling the handler. * * Note that x30 has been explicitly saved and can be * used here * ----------------------------------------------------- */ func smc_handler smc_handler32: /* Check whether aarch32 issued an SMC64 */ tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited /* ----------------------------------------------------- * Since we're are coming from aarch32, x8-x18 need to * be saved as per SMC32 calling convention. If a lower * EL in aarch64 is making an SMC32 call then it must * have saved x8-x17 already therein. * ----------------------------------------------------- */ stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] /* x4-x7, x18, sp_el0 are saved below */ smc_handler64: /* ----------------------------------------------------- * Populate the parameters for the SMC handler. We * already have x0-x4 in place. x5 will point to a * cookie (not used now). x6 will point to the context * structure (SP_EL3) and x7 will contain flags we need * to pass to the handler Hence save x5-x7. Note that x4 * only needs to be preserved for AArch32 callers but we * do it for AArch64 callers as well for convenience * ----------------------------------------------------- */ stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] /* Save rest of the gpregs and sp_el0*/ save_x18_to_x29_sp_el0 mov x5, xzr mov x6, sp /* Get the unique owning entity number */ ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) /* Load descriptor index from array of indices */ adr x14, rt_svc_descs_indices ldrb w15, [x14, x16] /* ----------------------------------------------------- * Restore the saved C runtime stack value which will * become the new SP_EL0 i.e. EL3 runtime stack. It was * saved in the 'cpu_context' structure prior to the last * ERET from EL3. * ----------------------------------------------------- */ ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] /* * Any index greater than 127 is invalid. Check bit 7 for * a valid index */ tbnz w15, 7, smc_unknown /* Switch to SP_EL0 */ msr spsel, #0 /* ----------------------------------------------------- * Get the descriptor using the index * x11 = (base + off), x15 = index * * handler = (base + off) + (index << log2(size)) * ----------------------------------------------------- */ lsl w10, w15, #RT_SVC_SIZE_LOG2 ldr x15, [x11, w10, uxtw] /* ----------------------------------------------------- * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there * is a world switch during SMC handling. * TODO: Revisit if all system registers can be saved * later. * ----------------------------------------------------- */ mrs x16, spsr_el3 mrs x17, elr_el3 mrs x18, scr_el3 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ bfi x7, x18, #0, #1 mov sp, x12 /* ----------------------------------------------------- * Call the Secure Monitor Call handler and then drop * directly into el3_exit() which will program any * remaining architectural state prior to issuing the * ERET to the desired lower EL. * ----------------------------------------------------- */ #if DEBUG cbz x15, rt_svc_fw_critical_error #endif blr x15 /* ----------------------------------------------------- * This routine assumes that the SP_EL3 is pointing to * a valid context structure from where the gp regs and * other special registers can be retrieved. * * Keep it in the same section as smc_handler as this * function uses a fall-through to el3_exit * ----------------------------------------------------- */ el3_exit: ; .type el3_exit, %function /* ----------------------------------------------------- * Save the current SP_EL0 i.e. the EL3 runtime stack * which will be used for handling the next SMC. Then * switch to SP_EL3 * ----------------------------------------------------- */ mov x17, sp msr spsel, #1 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] /* ----------------------------------------------------- * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET * ----------------------------------------------------- */ ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] msr scr_el3, x18 msr spsr_el3, x16 msr elr_el3, x17 /* Restore saved general purpose registers and return */ b restore_gp_registers_eret smc_unknown: /* * Here we restore x4-x18 regardless of where we came from. AArch32 * callers will find the registers contents unchanged, but AArch64 * callers will find the registers modified (with stale earlier NS * content). Either way, we aren't leaking any secure information * through them */ mov w0, #SMC_UNK b restore_gp_registers_callee_eret smc_prohibited: ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] mov w0, #SMC_UNK eret rt_svc_fw_critical_error: msr spsel, #1 /* Switch to SP_ELx */ bl report_unhandled_exception /* ----------------------------------------------------- * The following functions are used to saved and restore * all the general pupose registers. Ideally we would * only save and restore the callee saved registers when * a world switch occurs but that type of implementation * is more complex. So currently we will always save and * restore these registers on entry and exit of EL3. * These are not macros to ensure their invocation fits * within the 32 instructions per exception vector. * ----------------------------------------------------- */ func save_gp_registers stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] save_x18_to_x29_sp_el0 ret func restore_gp_registers_eret ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] restore_gp_registers_callee_eret: ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] ldp x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] msr sp_el0, x17 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] eret arm-trusted-firmware-1.0-aw-6/bl31/bl31.ld.S000066400000000000000000000112011322600646200202230ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) MEMORY { RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE } SECTIONS { . = BL31_BASE; ASSERT(. == ALIGN(4096), "BL31_BASE address is not aligned on a page boundary.") ro . : { __RO_START__ = .; KEEP(*bl31_entrypoint.o(.text*)) *(.text*) *(.rodata*) /* Ensure 8-byte alignment for descriptors and ensure inclusion */ . = ALIGN(8); __RT_SVC_DESCS_START__ = .; KEEP(*(rt_svc_descs)) __RT_SVC_DESCS_END__ = .; /* * Ensure 8-byte alignment for cpu_ops so that its fields are also * aligned. Also ensure cpu_ops inclusion. */ . = ALIGN(8); __CPU_OPS_START__ = .; KEEP(*(cpu_ops)) __CPU_OPS_END__ = .; *(.vectors) __RO_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked as read-only, * executable. No RW data from the next section must creep in. * Ensure the rest of the current memory page is unused. */ . = NEXT(4096); __RO_END__ = .; } >RAM ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") .data . : { __DATA_START__ = .; *(.data*) __DATA_END__ = .; } >RAM #ifdef BL31_PROGBITS_LIMIT ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.") #endif stacks (NOLOAD) : { __STACKS_START__ = .; *(tzfw_normal_stacks) __STACKS_END__ = .; } >RAM /* * The .bss section gets initialised to 0 at runtime. * Its base address must be 16-byte aligned. */ .bss : ALIGN(16) { __BSS_START__ = .; *(.bss*) *(COMMON) __BSS_END__ = .; } >RAM /* * The xlat_table section is for full, aligned page tables (4K). * Removing them from .bss avoids forcing 4K alignment on * the .bss section and eliminates the unecessary zero init */ xlat_table (NOLOAD) : { *(xlat_table) } >RAM /* * The base address of the coherent memory section must be page-aligned (4K) * to guarantee that the coherent data are stored on their own pages and * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ coherent_ram (NOLOAD) : ALIGN(4096) { __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ . = NEXT(4096); __COHERENT_RAM_END__ = .; } >RAM __BL31_END__ = .; __BSS_SIZE__ = SIZEOF(.bss); __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.") } arm-trusted-firmware-1.0-aw-6/bl31/bl31.mk000066400000000000000000000060051322600646200200400ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # BL31_SOURCES+= bl31/bl31_main.c \ bl31/context_mgmt.c \ bl31/cpu_data_array.c \ bl31/runtime_svc.c \ bl31/interrupt_mgmt.c \ bl31/aarch64/bl31_arch_setup.c \ bl31/aarch64/bl31_entrypoint.S \ bl31/aarch64/context.S \ bl31/aarch64/cpu_data.S \ bl31/aarch64/runtime_exceptions.S \ bl31/aarch64/crash_reporting.S \ lib/cpus/aarch64/cpu_helpers.S \ lib/locks/bakery/bakery_lock.c \ lib/locks/exclusive/spinlock.S \ services/std_svc/std_svc_setup.c \ services/std_svc/psci/psci_afflvl_off.c \ services/std_svc/psci/psci_afflvl_on.c \ services/std_svc/psci/psci_afflvl_suspend.c \ services/std_svc/psci/psci_common.c \ services/std_svc/psci/psci_entry.S \ services/std_svc/psci/psci_helpers.S \ services/std_svc/psci/psci_main.c \ services/std_svc/psci/psci_setup.c \ services/std_svc/psci/psci_system_off.c BL31_LINKERFILE := bl31/bl31.ld.S # Flag used by the generic interrupt management framework to determine if # upon the assertion of an interrupt, it should pass the interrupt id or not IMF_READ_INTERRUPT_ID := 0 $(eval $(call assert_boolean,IMF_READ_INTERRUPT_ID)) $(eval $(call add_define,IMF_READ_INTERRUPT_ID)) # Flag used to inidicate if Crash reporting via console should be included # in BL3-1. This defaults to being present in DEBUG builds only ifndef CRASH_REPORTING CRASH_REPORTING := $(DEBUG) endif $(eval $(call assert_boolean,CRASH_REPORTING)) $(eval $(call add_define,CRASH_REPORTING)) arm-trusted-firmware-1.0-aw-6/bl31/bl31_main.c000066400000000000000000000154411322600646200206630ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include /******************************************************************************* * This function pointer is used to initialise the BL32 image. It's initialized * by SPD calling bl31_register_bl32_init after setting up all things necessary * for SP execution. In cases where both SPD and SP are absent, or when SPD * finds it impossible to execute SP, this pointer is left as NULL ******************************************************************************/ static int32_t (*bl32_init)(void); /******************************************************************************* * Variable to indicate whether next image to execute after BL31 is BL33 * (non-secure & default) or BL32 (secure). ******************************************************************************/ static uint32_t next_image_type = NON_SECURE; /******************************************************************************* * Simple function to initialise all BL31 helper libraries. ******************************************************************************/ void bl31_lib_init(void) { cm_init(); } /******************************************************************************* * BL31 is responsible for setting up the runtime services for the primary cpu * before passing control to the bootloader or an Operating System. This * function calls runtime_svc_init() which initializes all registered runtime * services. The run time services would setup enough context for the core to * swtich to the next exception level. When this function returns, the core will * switch to the programmed exception level via. an ERET. ******************************************************************************/ void bl31_main(void) { NOTICE("BL3-1: %s\n", version_string); NOTICE("BL3-1: %s\n", build_message); /* Perform remaining generic architectural setup from EL3 */ bl31_arch_setup(); /* Perform platform setup in BL1 */ bl31_platform_setup(); /* Initialise helper libraries */ bl31_lib_init(); /* Initialize the runtime services e.g. psci */ INFO("BL3-1: Initializing runtime services\n"); runtime_svc_init(); /* Clean caches before re-entering normal world */ dcsw_op_all(DCCSW); /* * All the cold boot actions on the primary cpu are done. We now need to * decide which is the next image (BL32 or BL33) and how to execute it. * If the SPD runtime service is present, it would want to pass control * to BL32 first in S-EL1. In that case, SPD would have registered a * function to intialize bl32 where it takes responsibility of entering * S-EL1 and returning control back to bl31_main. Once this is done we * can prepare entry into BL33 as normal. */ /* * If SPD had registerd an init hook, invoke it. */ if (bl32_init) { INFO("BL3-1: Initializing BL3-2\n"); (*bl32_init)(); } /* * We are ready to enter the next EL. Prepare entry into the image * corresponding to the desired security state after the next ERET. */ bl31_prepare_next_image_entry(); } /******************************************************************************* * Accessor functions to help runtime services decide which image should be * executed after BL31. This is BL33 or the non-secure bootloader image by * default but the Secure payload dispatcher could override this by requesting * an entry into BL32 (Secure payload) first. If it does so then it should use * the same API to program an entry into BL33 once BL32 initialisation is * complete. ******************************************************************************/ void bl31_set_next_image_type(uint32_t security_state) { assert(sec_state_is_valid(security_state)); next_image_type = security_state; } uint32_t bl31_get_next_image_type(void) { return next_image_type; } /******************************************************************************* * This function programs EL3 registers and performs other setup to enable entry * into the next image after BL31 at the next ERET. ******************************************************************************/ void bl31_prepare_next_image_entry(void) { entry_point_info_t *next_image_info; uint32_t image_type; /* Determine which image to execute next */ image_type = bl31_get_next_image_type(); /* Program EL3 registers to enable entry into the next EL */ next_image_info = bl31_plat_get_next_image_ep_info(image_type); assert(next_image_info); assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr)); INFO("BL3-1: Preparing for EL3 exit to %s world\n", (image_type == SECURE) ? "secure" : "normal"); INFO("BL3-1: Next image address: 0x%lx, SPSR: 0x%x\n", next_image_info->pc, next_image_info->spsr); cm_init_context(read_mpidr_el1(), next_image_info); cm_prepare_el3_exit(image_type); } /******************************************************************************* * This function initializes the pointer to BL32 init function. This is expected * to be called by the SPD after it finishes all its initialization ******************************************************************************/ void bl31_register_bl32_init(int32_t (*func)(void)) { bl32_init = func; } arm-trusted-firmware-1.0-aw-6/bl31/context_mgmt.c000066400000000000000000000335441322600646200216320ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include /******************************************************************************* * Context management library initialisation routine. This library is used by * runtime services to share pointers to 'cpu_context' structures for the secure * and non-secure states. Management of the structures and their associated * memory is not done by the context management library e.g. the PSCI service * manages the cpu context used for entry from and exit to the non-secure state. * The Secure payload dispatcher service manages the context(s) corresponding to * the secure state. It also uses this library to get access to the non-secure * state cpu context pointers. * Lastly, this library provides the api to make SP_EL3 point to the cpu context * which will used for programming an entry into a lower EL. The same context * will used to save state upon exception entry from that EL. ******************************************************************************/ void cm_init(void) { /* * The context management library has only global data to intialize, but * that will be done when the BSS is zeroed out */ } /******************************************************************************* * This function returns a pointer to the most recent 'cpu_context' structure * for the CPU identified by MPIDR that was set as the context for the specified * security state. NULL is returned if no such structure has been specified. ******************************************************************************/ void *cm_get_context_by_mpidr(uint64_t mpidr, uint32_t security_state) { assert(sec_state_is_valid(security_state)); return get_cpu_data_by_mpidr(mpidr, cpu_context[security_state]); } /******************************************************************************* * This function sets the pointer to the current 'cpu_context' structure for the * specified security state for the CPU identified by MPIDR ******************************************************************************/ void cm_set_context_by_mpidr(uint64_t mpidr, void *context, uint32_t security_state) { assert(sec_state_is_valid(security_state)); set_cpu_data_by_mpidr(mpidr, cpu_context[security_state], context); } /******************************************************************************* * This function is used to program the context that's used for exception * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for * the required security state ******************************************************************************/ static inline void cm_set_next_context(void *context) { #if DEBUG uint64_t sp_mode; /* * Check that this function is called with SP_EL0 as the stack * pointer */ __asm__ volatile("mrs %0, SPSel\n" : "=r" (sp_mode)); assert(sp_mode == MODE_SP_EL0); #endif __asm__ volatile("msr spsel, #1\n" "mov sp, %0\n" "msr spsel, #0\n" : : "r" (context)); } /******************************************************************************* * The following function initializes a cpu_context for the current CPU for * first use, and sets the initial entrypoint state as specified by the * entry_point_info structure. * * The security state to initialize is determined by the SECURE attribute * of the entry_point_info. The function returns a pointer to the initialized * context and sets this as the next context to return to. * * The EE and ST attributes are used to configure the endianess and secure * timer availability for the new excution context. * * To prepare the register state for entry call cm_prepare_el3_exit() and * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to * cm_e1_sysreg_context_restore(). ******************************************************************************/ void cm_init_context(uint64_t mpidr, const entry_point_info_t *ep) { uint32_t security_state; cpu_context_t *ctx; uint32_t scr_el3; el3_state_t *state; gp_regs_t *gp_regs; unsigned long sctlr_elx; security_state = GET_SECURITY_STATE(ep->h.attr); ctx = cm_get_context_by_mpidr(mpidr, security_state); assert(ctx); /* Clear any residual register values from the context */ memset(ctx, 0, sizeof(*ctx)); /* * Base the context SCR on the current value, adjust for entry point * specific requirements and set trap bits from the IMF * TODO: provide the base/global SCR bits using another mechanism? */ scr_el3 = read_scr(); scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | SCR_ST_BIT | SCR_HCE_BIT); if (security_state != SECURE) scr_el3 |= SCR_NS_BIT; if (GET_RW(ep->spsr) == MODE_RW_64) scr_el3 |= SCR_RW_BIT; if (EP_GET_ST(ep->h.attr)) scr_el3 |= SCR_ST_BIT; scr_el3 |= get_scr_el3_from_routing_model(security_state); /* * Set up SCTLR_ELx for the target exception level: * EE bit is taken from the entrpoint attributes * M, C and I bits must be zero (as required by PSCI specification) * * The target exception level is based on the spsr mode requested. * If execution is requested to EL2 or hyp mode, HVC is enabled * via SCR_EL3.HCE. * * Always compute the SCTLR_EL1 value and save in the cpu_context * - the EL2 registers are set up by cm_preapre_ns_entry() as they * are not part of the stored cpu_context * * TODO: In debug builds the spsr should be validated and checked * against the CPU support, security state, endianess and pc */ sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; sctlr_elx |= SCTLR_EL1_RES1; //if use AA32 SVC if(GET_M32(ep->spsr) == MODE32_svc) { sctlr_elx |= 1<<5;//AArch32 CP15 barrier operations enabled } write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); if ((GET_RW(ep->spsr) == MODE_RW_64 && GET_EL(ep->spsr) == MODE_EL2) || (GET_RW(ep->spsr) != MODE_RW_64 && GET_M32(ep->spsr) == MODE32_hyp)) { scr_el3 |= SCR_HCE_BIT; } /* Populate EL3 state so that we've the right context before doing ERET */ state = get_el3state_ctx(ctx); write_ctx_reg(state, CTX_SCR_EL3, scr_el3); write_ctx_reg(state, CTX_ELR_EL3, ep->pc); write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); /* * Store the X0-X7 value from the entrypoint into the context * Use memcpy as we are in control of the layout of the structures */ gp_regs = get_gpregs_ctx(ctx); memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); } /******************************************************************************* * Prepare the CPU system registers for first entry into secure or normal world * * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized * If execution is requested to non-secure EL1 or svc mode, and the CPU supports * EL2 then EL2 is disabled by configuring all necessary EL2 registers. * For all entries, the EL1 registers are initialized from the cpu_context ******************************************************************************/ void cm_prepare_el3_exit(uint32_t security_state) { uint32_t sctlr_elx, scr_el3, cptr_el2; cpu_context_t *ctx = cm_get_context(security_state); assert(ctx); if (security_state == NON_SECURE) { scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); if (scr_el3 & SCR_HCE_BIT) { /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); sctlr_elx &= ~SCTLR_EE_BIT; sctlr_elx |= SCTLR_EL2_RES1; write_sctlr_el2(sctlr_elx); } else if (read_id_aa64pfr0_el1() & (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) { /* EL2 present but unused, need to disable safely */ /* HCR_EL2 = 0, except RW bit set to match SCR_EL3 */ write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); /* SCTLR_EL2 : can be ignored when bypassing */ /* CPTR_EL2 : disable all traps TCPAC, TTA, TFP */ cptr_el2 = read_cptr_el2(); cptr_el2 &= ~(TCPAC_BIT | TTA_BIT | TFP_BIT); write_cptr_el2(cptr_el2); /* Enable EL1 access to timer */ write_cnthctl_el2(EL1PCEN_BIT | EL1PCTEN_BIT); /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ write_vpidr_el2(read_midr_el1()); write_vmpidr_el2(read_mpidr_el1()); } } el1_sysregs_context_restore(get_sysregs_ctx(ctx)); cm_set_next_context(ctx); } /******************************************************************************* * The next four functions are used by runtime services to save and restore * EL1 context on the 'cpu_context' structure for the specified security * state. ******************************************************************************/ void cm_el1_sysregs_context_save(uint32_t security_state) { cpu_context_t *ctx; ctx = cm_get_context(security_state); assert(ctx); el1_sysregs_context_save(get_sysregs_ctx(ctx)); } void cm_el1_sysregs_context_restore(uint32_t security_state) { cpu_context_t *ctx; ctx = cm_get_context(security_state); assert(ctx); el1_sysregs_context_restore(get_sysregs_ctx(ctx)); } /******************************************************************************* * This function populates ELR_EL3 member of 'cpu_context' pertaining to the * given security state with the given entrypoint ******************************************************************************/ void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint) { cpu_context_t *ctx; el3_state_t *state; ctx = cm_get_context(security_state); assert(ctx); /* Populate EL3 state so that ERET jumps to the correct entry */ state = get_el3state_ctx(ctx); write_ctx_reg(state, CTX_ELR_EL3, entrypoint); } /******************************************************************************* * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' * pertaining to the given security state ******************************************************************************/ void cm_set_elr_spsr_el3(uint32_t security_state, uint64_t entrypoint, uint32_t spsr) { cpu_context_t *ctx; el3_state_t *state; ctx = cm_get_context(security_state); assert(ctx); /* Populate EL3 state so that ERET jumps to the correct entry */ state = get_el3state_ctx(ctx); write_ctx_reg(state, CTX_ELR_EL3, entrypoint); write_ctx_reg(state, CTX_SPSR_EL3, spsr); } /******************************************************************************* * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' * pertaining to the given security state using the value and bit position * specified in the parameters. It preserves all other bits. ******************************************************************************/ void cm_write_scr_el3_bit(uint32_t security_state, uint32_t bit_pos, uint32_t value) { cpu_context_t *ctx; el3_state_t *state; uint32_t scr_el3; ctx = cm_get_context(security_state); assert(ctx); /* Ensure that the bit position is a valid one */ assert((1 << bit_pos) & SCR_VALID_BIT_MASK); /* Ensure that the 'value' is only a bit wide */ assert(value <= 1); /* * Get the SCR_EL3 value from the cpu context, clear the desired bit * and set it to its new value. */ state = get_el3state_ctx(ctx); scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); scr_el3 &= ~(1 << bit_pos); scr_el3 |= value << bit_pos; write_ctx_reg(state, CTX_SCR_EL3, scr_el3); } /******************************************************************************* * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the * given security state. ******************************************************************************/ uint32_t cm_get_scr_el3(uint32_t security_state) { cpu_context_t *ctx; el3_state_t *state; ctx = cm_get_context(security_state); assert(ctx); /* Populate EL3 state so that ERET jumps to the correct entry */ state = get_el3state_ctx(ctx); return read_ctx_reg(state, CTX_SCR_EL3); } /******************************************************************************* * This function is used to program the context that's used for exception * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for * the required security state ******************************************************************************/ void cm_set_next_eret_context(uint32_t security_state) { cpu_context_t *ctx; ctx = cm_get_context(security_state); assert(ctx); cm_set_next_context(ctx); } arm-trusted-firmware-1.0-aw-6/bl31/cpu_data_array.c000066400000000000000000000032701322600646200220710ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include /* The per_cpu_ptr_cache_t space allocation */ cpu_data_t percpu_data[PLATFORM_CORE_COUNT]; arm-trusted-firmware-1.0-aw-6/bl31/interrupt_mgmt.c000066400000000000000000000175121322600646200221770ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include /******************************************************************************* * Local structure and corresponding array to keep track of the state of the * registered interrupt handlers for each interrupt type. * The field descriptions are: * * 'flags' : Bit[0], Routing model for this interrupt type when execution is * not in EL3 in the secure state. '1' implies that this * interrupt will be routed to EL3. '0' implies that this * interrupt will be routed to the current exception level. * * Bit[1], Routing model for this interrupt type when execution is * not in EL3 in the non-secure state. '1' implies that this * interrupt will be routed to EL3. '0' implies that this * interrupt will be routed to the current exception level. * * All other bits are reserved and SBZ. * * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the * value of the SCR_EL3.IRQ or FIQ bit for each security state. * There are two instances of this field corresponding to the * two security states. ******************************************************************************/ typedef struct intr_type_desc { interrupt_type_handler_t handler; uint32_t flags; uint32_t scr_el3[2]; } intr_type_desc_t; static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES]; /******************************************************************************* * This function validates the interrupt type. EL3 interrupts are currently not * supported. ******************************************************************************/ static int32_t validate_interrupt_type(uint32_t type) { if (type == INTR_TYPE_EL3) return -ENOTSUP; if (type != INTR_TYPE_S_EL1 && type != INTR_TYPE_NS) return -EINVAL; return 0; } /******************************************************************************* * This function validates the routing model for this type of interrupt ******************************************************************************/ static int32_t validate_routing_model(uint32_t type, uint32_t flags) { flags >>= INTR_RM_FLAGS_SHIFT; flags &= INTR_RM_FLAGS_MASK; if (type == INTR_TYPE_S_EL1) return validate_sel1_interrupt_rm(flags); if (type == INTR_TYPE_NS) return validate_ns_interrupt_rm(flags); return -EINVAL; } /******************************************************************************* * This function returns the cached copy of the SCR_EL3 which contains the * routing model (expressed through the IRQ and FIQ bits) for a security state * which was stored through a call to 'set_routing_model()' earlier. ******************************************************************************/ uint32_t get_scr_el3_from_routing_model(uint32_t security_state) { uint32_t scr_el3; assert(sec_state_is_valid(security_state)); scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; scr_el3 |= intr_type_descs[INTR_TYPE_S_EL1].scr_el3[security_state]; scr_el3 |= intr_type_descs[INTR_TYPE_EL3].scr_el3[security_state]; return scr_el3; } /******************************************************************************* * This function uses the 'interrupt_type_flags' parameter to obtain the value * of the trap bit (IRQ/FIQ) in the SCR_EL3 for a security state for this * interrupt type. It uses it to update the SCR_EL3 in the cpu context and the * 'intr_type_desc' for that security state. ******************************************************************************/ static void set_scr_el3_from_rm(uint32_t type, uint32_t interrupt_type_flags, uint32_t security_state) { uint32_t flag, bit_pos; flag = get_interrupt_rm_flag(interrupt_type_flags, security_state); bit_pos = plat_interrupt_type_to_line(type, security_state); intr_type_descs[type].scr_el3[security_state] = flag << bit_pos; cm_write_scr_el3_bit(security_state, bit_pos, flag); } /******************************************************************************* * This function validates the routing model specified in the 'flags' and * updates internal data structures to reflect the new routing model. It also * updates the copy of SCR_EL3 for each security state with the new routing * model in the 'cpu_context' structure for this cpu. ******************************************************************************/ int32_t set_routing_model(uint32_t type, uint32_t flags) { int32_t rc; rc = validate_interrupt_type(type); if (rc) return rc; rc = validate_routing_model(type, flags); if (rc) return rc; /* Update the routing model in internal data structures */ intr_type_descs[type].flags = flags; set_scr_el3_from_rm(type, flags, SECURE); set_scr_el3_from_rm(type, flags, NON_SECURE); return 0; } /******************************************************************************* * This function registers a handler for the 'type' of interrupt specified. It * also validates the routing model specified in the 'flags' for this type of * interrupt. ******************************************************************************/ int32_t register_interrupt_type_handler(uint32_t type, interrupt_type_handler_t handler, uint32_t flags) { int32_t rc; /* Validate the 'handler' parameter */ if (!handler) return -EINVAL; /* Validate the 'flags' parameter */ if (flags & INTR_TYPE_FLAGS_MASK) return -EINVAL; /* Check if a handler has already been registered */ if (intr_type_descs[type].handler) return -EALREADY; rc = set_routing_model(type, flags); if (rc) return rc; /* Save the handler */ intr_type_descs[type].handler = handler; return 0; } /******************************************************************************* * This function is called when an interrupt is generated and returns the * handler for the interrupt type (if registered). It returns NULL if the * interrupt type is not supported or its handler has not been registered. ******************************************************************************/ interrupt_type_handler_t get_interrupt_type_handler(uint32_t type) { if (validate_interrupt_type(type)) return NULL; return intr_type_descs[type].handler; } arm-trusted-firmware-1.0-aw-6/bl31/runtime_svc.c000066400000000000000000000130751322600646200214550ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include /******************************************************************************* * The 'rt_svc_descs' array holds the runtime service descriptors exported by * services by placing them in the 'rt_svc_descs' linker section. * The 'rt_svc_descs_indices' array holds the index of a descriptor in the * 'rt_svc_descs' array. When an SMC arrives, the OEN[29:24] bits and the call * type[31] bit in the function id are combined to get an index into the * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the * 'rt_svc_descs' array which contains the SMC handler. ******************************************************************************/ #define RT_SVC_DESCS_START ((uint64_t) (&__RT_SVC_DESCS_START__)) #define RT_SVC_DESCS_END ((uint64_t) (&__RT_SVC_DESCS_END__)) uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; static rt_svc_desc_t *rt_svc_descs; /******************************************************************************* * Simple routine to sanity check a runtime service descriptor before using it ******************************************************************************/ static int32_t validate_rt_svc_desc(rt_svc_desc_t *desc) { if (desc == NULL) return -EINVAL; if (desc->start_oen > desc->end_oen) return -EINVAL; if (desc->end_oen >= OEN_LIMIT) return -EINVAL; if (desc->call_type != SMC_TYPE_FAST && desc->call_type != SMC_TYPE_STD) return -EINVAL; /* A runtime service having no init or handle function doesn't make sense */ if (desc->init == NULL && desc->handle == NULL) return -EINVAL; return 0; } /******************************************************************************* * This function calls the initialisation routine in the descriptor exported by * a runtime service. Once a descriptor has been validated, its start & end * owning entity numbers and the call type are combined to form a unique oen. * The unique oen is used as an index into the 'rt_svc_descs_indices' array. * The index of the runtime service descriptor is stored at this index. ******************************************************************************/ void runtime_svc_init(void) { int32_t rc = 0; uint32_t index, start_idx, end_idx; uint64_t rt_svc_descs_num; /* If no runtime services are implemented then simply bail out */ rt_svc_descs_num = RT_SVC_DESCS_END - RT_SVC_DESCS_START; rt_svc_descs_num /= sizeof(rt_svc_desc_t); if (rt_svc_descs_num == 0) return; /* Initialise internal variables to invalid state */ memset(rt_svc_descs_indices, -1, sizeof(rt_svc_descs_indices)); rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START; for (index = 0; index < rt_svc_descs_num; index++) { /* * An invalid descriptor is an error condition since it is * difficult to predict the system behaviour in the absence * of this service. */ rc = validate_rt_svc_desc(&rt_svc_descs[index]); if (rc) { ERROR("Invalid runtime service descriptor 0x%x (%s)\n", &rt_svc_descs[index], rt_svc_descs[index].name); goto error; } /* * The runtime service may have seperate rt_svc_desc_t * for its fast smc and standard smc. Since the service itself * need to be initialized only once, only one of them will have * an initialisation routine defined. Call the initialisation * routine for this runtime service, if it is defined. */ if (rt_svc_descs[index].init) { rc = rt_svc_descs[index].init(); if (rc) { ERROR("Error initializing runtime service %s\n", rt_svc_descs[index].name); continue; } } /* * Fill the indices corresponding to the start and end * owning entity numbers with the index of the * descriptor which will handle the SMCs for this owning * entity range. */ start_idx = get_unique_oen(rt_svc_descs[index].start_oen, rt_svc_descs[index].call_type); end_idx = get_unique_oen(rt_svc_descs[index].end_oen, rt_svc_descs[index].call_type); for (; start_idx <= end_idx; start_idx++) rt_svc_descs_indices[start_idx] = index; } return; error: panic(); } arm-trusted-firmware-1.0-aw-6/bl32/000077500000000000000000000000001322600646200167465ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/bl32/tsp/000077500000000000000000000000001322600646200175545ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/bl32/tsp/aarch64/000077500000000000000000000000001322600646200210045ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/bl32/tsp/aarch64/tsp_entrypoint.S000066400000000000000000000304351322600646200242360ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include "../tsp_private.h" .globl tsp_entrypoint .globl tsp_vector_table /* --------------------------------------------- * Populate the params in x0-x7 from the pointer * to the smc args structure in x0. * --------------------------------------------- */ .macro restore_args_call_smc ldp x6, x7, [x0, #TSP_ARG6] ldp x4, x5, [x0, #TSP_ARG4] ldp x2, x3, [x0, #TSP_ARG2] ldp x0, x1, [x0, #TSP_ARG0] smc #0 .endm .macro save_eret_context reg1 reg2 mrs \reg1, elr_el1 mrs \reg2, spsr_el1 stp \reg1, \reg2, [sp, #-0x10]! stp x30, x18, [sp, #-0x10]! .endm .macro restore_eret_context reg1 reg2 ldp x30, x18, [sp], #0x10 ldp \reg1, \reg2, [sp], #0x10 msr elr_el1, \reg1 msr spsr_el1, \reg2 .endm .section .text, "ax" .align 3 func tsp_entrypoint /* --------------------------------------------- * Set the exception vector to something sane. * --------------------------------------------- */ adr x0, tsp_exceptions msr vbar_el1, x0 isb /* --------------------------------------------- * Enable the SError interrupt now that the * exception vectors have been setup. * --------------------------------------------- */ msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer * and data access alignment checks * --------------------------------------------- */ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el1 orr x0, x0, x1 msr sctlr_el1, x0 isb /* --------------------------------------------- * Zero out NOBITS sections. There are 2 of them: * - the .bss section; * - the coherent memory section. * --------------------------------------------- */ ldr x0, =__BSS_START__ ldr x1, =__BSS_SIZE__ bl zeromem16 ldr x0, =__COHERENT_RAM_START__ ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ bl zeromem16 /* -------------------------------------------- * Allocate a stack whose memory will be marked * as Normal-IS-WBWA when the MMU is enabled. * There is no risk of reading stale stack * memory after enabling the MMU as only the * primary cpu is running at the moment. * -------------------------------------------- */ mrs x0, mpidr_el1 bl platform_set_stack /* --------------------------------------------- * Perform early platform setup & platform * specific early arch. setup e.g. mmu setup * --------------------------------------------- */ bl tsp_early_platform_setup bl tsp_plat_arch_setup /* --------------------------------------------- * Jump to main function. * --------------------------------------------- */ bl tsp_main /* --------------------------------------------- * Tell TSPD that we are done initialising * --------------------------------------------- */ mov x1, x0 mov x0, #TSP_ENTRY_DONE smc #0 tsp_entrypoint_panic: b tsp_entrypoint_panic /* ------------------------------------------- * Table of entrypoint vectors provided to the * TSPD for the various entrypoints * ------------------------------------------- */ func tsp_vector_table b tsp_std_smc_entry b tsp_fast_smc_entry b tsp_cpu_on_entry b tsp_cpu_off_entry b tsp_cpu_resume_entry b tsp_cpu_suspend_entry b tsp_fiq_entry b tsp_system_off_entry b tsp_system_reset_entry /*--------------------------------------------- * This entrypoint is used by the TSPD when this * cpu is to be turned off through a CPU_OFF * psci call to ask the TSP to perform any * bookeeping necessary. In the current * implementation, the TSPD expects the TSP to * re-initialise its state so nothing is done * here except for acknowledging the request. * --------------------------------------------- */ func tsp_cpu_off_entry bl tsp_cpu_off_main restore_args_call_smc /*--------------------------------------------- * This entrypoint is used by the TSPD when the * system is about to be switched off (through * a SYSTEM_OFF psci call) to ask the TSP to * perform any necessary bookkeeping. * --------------------------------------------- */ func tsp_system_off_entry bl tsp_system_off_main restore_args_call_smc /*--------------------------------------------- * This entrypoint is used by the TSPD when the * system is about to be reset (through a * SYSTEM_RESET psci call) to ask the TSP to * perform any necessary bookkeeping. * --------------------------------------------- */ func tsp_system_reset_entry bl tsp_system_reset_main restore_args_call_smc /*--------------------------------------------- * This entrypoint is used by the TSPD when this * cpu is turned on using a CPU_ON psci call to * ask the TSP to initialise itself i.e. setup * the mmu, stacks etc. Minimal architectural * state will be initialised by the TSPD when * this function is entered i.e. Caches and MMU * will be turned off, the execution state * will be aarch64 and exceptions masked. * --------------------------------------------- */ func tsp_cpu_on_entry /* --------------------------------------------- * Set the exception vector to something sane. * --------------------------------------------- */ adr x0, tsp_exceptions msr vbar_el1, x0 isb /* Enable the SError interrupt */ msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer * and data access alignment checks * --------------------------------------------- */ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el1 orr x0, x0, x1 msr sctlr_el1, x0 isb /* -------------------------------------------- * Give ourselves a stack whose memory will be * marked as Normal-IS-WBWA when the MMU is * enabled. * -------------------------------------------- */ mrs x0, mpidr_el1 bl platform_set_stack /* -------------------------------------------- * Enable the MMU with the DCache disabled. It * is safe to use stacks allocated in normal * memory as a result. All memory accesses are * marked nGnRnE when the MMU is disabled. So * all the stack writes will make it to memory. * All memory accesses are marked Non-cacheable * when the MMU is enabled but D$ is disabled. * So used stack memory is guaranteed to be * visible immediately after the MMU is enabled * Enabling the DCache at the same time as the * MMU can lead to speculatively fetched and * possibly stale stack memory being read from * other caches. This can lead to coherency * issues. * -------------------------------------------- */ mov x0, #DISABLE_DCACHE bl bl32_plat_enable_mmu /* --------------------------------------------- * Enable the Data cache now that the MMU has * been enabled. The stack has been unwound. It * will be written first before being read. This * will invalidate any stale cache lines resi- * -dent in other caches. We assume that * interconnect coherency has been enabled for * this cluster by EL3 firmware. * --------------------------------------------- */ mrs x0, sctlr_el1 orr x0, x0, #SCTLR_C_BIT msr sctlr_el1, x0 isb /* --------------------------------------------- * Enter C runtime to perform any remaining * book keeping * --------------------------------------------- */ bl tsp_cpu_on_main restore_args_call_smc /* Should never reach here */ tsp_cpu_on_entry_panic: b tsp_cpu_on_entry_panic /*--------------------------------------------- * This entrypoint is used by the TSPD when this * cpu is to be suspended through a CPU_SUSPEND * psci call to ask the TSP to perform any * bookeeping necessary. In the current * implementation, the TSPD saves and restores * the EL1 state. * --------------------------------------------- */ func tsp_cpu_suspend_entry bl tsp_cpu_suspend_main restore_args_call_smc /*--------------------------------------------- * This entrypoint is used by the TSPD to pass * control for handling a pending S-EL1 FIQ. * 'x0' contains a magic number which indicates * this. TSPD expects control to be handed back * at the end of FIQ processing. This is done * through an SMC. The handover agreement is: * * 1. PSTATE.DAIF are set upon entry. 'x1' has * the ELR_EL3 from the non-secure state. * 2. TSP has to preserve the callee saved * general purpose registers, SP_EL1/EL0 and * LR. * 3. TSP has to preserve the system and vfp * registers (if applicable). * 4. TSP can use 'x0-x18' to enable its C * runtime. * 5. TSP returns to TSPD using an SMC with * 'x0' = TSP_HANDLED_S_EL1_FIQ * --------------------------------------------- */ func tsp_fiq_entry #if DEBUG mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) cmp x0, x2 b.ne tsp_fiq_entry_panic #endif /*--------------------------------------------- * Save any previous context needed to perform * an exception return from S-EL1 e.g. context * from a previous IRQ. Update statistics and * handle the FIQ before returning to the TSPD. * IRQ/FIQs are not enabled since that will * complicate the implementation. Execution * will be transferred back to the normal world * in any case. A non-zero return value from the * fiq handler is an error. * --------------------------------------------- */ save_eret_context x2 x3 bl tsp_update_sync_fiq_stats bl tsp_fiq_handler cbnz x0, tsp_fiq_entry_panic restore_eret_context x2 x3 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) smc #0 tsp_fiq_entry_panic: b tsp_fiq_entry_panic /*--------------------------------------------- * This entrypoint is used by the TSPD when this * cpu resumes execution after an earlier * CPU_SUSPEND psci call to ask the TSP to * restore its saved context. In the current * implementation, the TSPD saves and restores * EL1 state so nothing is done here apart from * acknowledging the request. * --------------------------------------------- */ func tsp_cpu_resume_entry bl tsp_cpu_resume_main restore_args_call_smc tsp_cpu_resume_panic: b tsp_cpu_resume_panic /*--------------------------------------------- * This entrypoint is used by the TSPD to ask * the TSP to service a fast smc request. * --------------------------------------------- */ func tsp_fast_smc_entry bl tsp_smc_handler restore_args_call_smc tsp_fast_smc_entry_panic: b tsp_fast_smc_entry_panic /*--------------------------------------------- * This entrypoint is used by the TSPD to ask * the TSP to service a std smc request. * We will enable preemption during execution * of tsp_smc_handler. * --------------------------------------------- */ func tsp_std_smc_entry msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT bl tsp_smc_handler msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT restore_args_call_smc tsp_std_smc_entry_panic: b tsp_std_smc_entry_panic arm-trusted-firmware-1.0-aw-6/bl32/tsp/aarch64/tsp_exceptions.S000066400000000000000000000126421322600646200242040ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include /* ---------------------------------------------------- * The caller-saved registers x0-x18 and LR are saved * here. * ---------------------------------------------------- */ #define SCRATCH_REG_SIZE #(20 * 8) .macro save_caller_regs_and_lr sub sp, sp, SCRATCH_REG_SIZE stp x0, x1, [sp] stp x2, x3, [sp, #0x10] stp x4, x5, [sp, #0x20] stp x6, x7, [sp, #0x30] stp x8, x9, [sp, #0x40] stp x10, x11, [sp, #0x50] stp x12, x13, [sp, #0x60] stp x14, x15, [sp, #0x70] stp x16, x17, [sp, #0x80] stp x18, x30, [sp, #0x90] .endm .macro restore_caller_regs_and_lr ldp x0, x1, [sp] ldp x2, x3, [sp, #0x10] ldp x4, x5, [sp, #0x20] ldp x6, x7, [sp, #0x30] ldp x8, x9, [sp, #0x40] ldp x10, x11, [sp, #0x50] ldp x12, x13, [sp, #0x60] ldp x14, x15, [sp, #0x70] ldp x16, x17, [sp, #0x80] ldp x18, x30, [sp, #0x90] add sp, sp, SCRATCH_REG_SIZE .endm .globl tsp_exceptions /* ----------------------------------------------------- * TSP exception handlers. * ----------------------------------------------------- */ .section .vectors, "ax"; .align 11 .align 7 tsp_exceptions: /* ----------------------------------------------------- * Current EL with _sp_el0 : 0x0 - 0x180. No exceptions * are expected and treated as irrecoverable errors. * ----------------------------------------------------- */ sync_exception_sp_el0: wfi b sync_exception_sp_el0 check_vector_size sync_exception_sp_el0 .align 7 irq_sp_el0: b irq_sp_el0 check_vector_size irq_sp_el0 .align 7 fiq_sp_el0: b fiq_sp_el0 check_vector_size fiq_sp_el0 .align 7 serror_sp_el0: b serror_sp_el0 check_vector_size serror_sp_el0 /* ----------------------------------------------------- * Current EL with SPx: 0x200 - 0x380. Only IRQs/FIQs * are expected and handled * ----------------------------------------------------- */ .align 7 sync_exception_sp_elx: wfi b sync_exception_sp_elx check_vector_size sync_exception_sp_elx .align 7 irq_sp_elx: /* Enable the SError interrupt */ msr daifclr, #DAIF_ABT_BIT save_caller_regs_and_lr /* We just update some statistics in the handler */ bl tsp_irq_received /* Hand over control to the normal world to handle the IRQ */ smc #0 /* The resume std smc starts from here */ restore_caller_regs_and_lr eret check_vector_size irq_sp_elx .align 7 fiq_sp_elx: /* Enable the SError interrupt */ msr daifclr, #DAIF_ABT_BIT save_caller_regs_and_lr bl tsp_fiq_handler cbz x0, fiq_sp_elx_done /* * This FIQ was not targetted to S-EL1 so send it to * the monitor and wait for execution to resume. */ smc #0 fiq_sp_elx_done: restore_caller_regs_and_lr eret check_vector_size fiq_sp_elx .align 7 serror_sp_elx: b serror_sp_elx check_vector_size serror_sp_elx /* ----------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x580. No exceptions * are handled since TSP does not implement a lower EL * ----------------------------------------------------- */ .align 7 sync_exception_aarch64: wfi b sync_exception_aarch64 check_vector_size sync_exception_aarch64 .align 7 irq_aarch64: b irq_aarch64 check_vector_size irq_aarch64 .align 7 fiq_aarch64: b fiq_aarch64 check_vector_size fiq_aarch64 .align 7 serror_aarch64: b serror_aarch64 check_vector_size serror_aarch64 /* ----------------------------------------------------- * Lower EL using AArch32 : 0x600 - 0x780. No exceptions * handled since the TSP does not implement a lower EL. * ----------------------------------------------------- */ .align 7 sync_exception_aarch32: wfi b sync_exception_aarch32 check_vector_size sync_exception_aarch32 .align 7 irq_aarch32: b irq_aarch32 check_vector_size irq_aarch32 .align 7 fiq_aarch32: b fiq_aarch32 check_vector_size fiq_aarch32 .align 7 serror_aarch32: b serror_aarch32 check_vector_size serror_aarch32 .align 7 arm-trusted-firmware-1.0-aw-6/bl32/tsp/aarch64/tsp_request.S000066400000000000000000000041441322600646200235110ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include .globl tsp_get_magic /* * This function raises an SMC to retrieve arguments from secure * monitor/dispatcher, saves the returned arguments the array received in x0, * and then returns to the caller */ func tsp_get_magic /* Save address to stack */ stp x0, xzr, [sp, #-16]! /* Load arguments */ ldr w0, _tsp_fid_get_magic /* Raise SMC */ smc #0 /* Restore address from stack */ ldp x4, xzr, [sp], #16 /* Store returned arguments to the array */ stp x0, x1, [x4, #0] ret .align 2 _tsp_fid_get_magic: .word TSP_GET_ARGS arm-trusted-firmware-1.0-aw-6/bl32/tsp/tsp.ld.S000066400000000000000000000101631322600646200211050ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) ENTRY(tsp_entrypoint) MEMORY { RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE } SECTIONS { . = BL32_BASE; ASSERT(. == ALIGN(4096), "BL32_BASE address is not aligned on a page boundary.") ro . : { __RO_START__ = .; *tsp_entrypoint.o(.text*) *(.text*) *(.rodata*) *(.vectors) __RO_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked as * read-only, executable. No RW data from the next section must * creep in. Ensure the rest of the current memory page is unused. */ . = NEXT(4096); __RO_END__ = .; } >RAM .data . : { __DATA_START__ = .; *(.data*) __DATA_END__ = .; } >RAM #ifdef TSP_PROGBITS_LIMIT ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.") #endif stacks (NOLOAD) : { __STACKS_START__ = .; *(tzfw_normal_stacks) __STACKS_END__ = .; } >RAM /* * The .bss section gets initialised to 0 at runtime. * Its base address must be 16-byte aligned. */ .bss : ALIGN(16) { __BSS_START__ = .; *(SORT_BY_ALIGNMENT(.bss*)) *(COMMON) __BSS_END__ = .; } >RAM /* * The xlat_table section is for full, aligned page tables (4K). * Removing them from .bss avoids forcing 4K alignment on * the .bss section and eliminates the unecessary zero init */ xlat_table (NOLOAD) : { *(xlat_table) } >RAM /* * The base address of the coherent memory section must be page-aligned (4K) * to guarantee that the coherent data are stored on their own pages and * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ coherent_ram (NOLOAD) : ALIGN(4096) { __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ . = NEXT(4096); __COHERENT_RAM_END__ = .; } >RAM __BL32_END__ = .; __BSS_SIZE__ = SIZEOF(.bss); __COHERENT_RAM_UNALIGNED_SIZE__ = __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; ASSERT(. <= BL32_LIMIT, "BL3-2 image has exceeded its limit.") } arm-trusted-firmware-1.0-aw-6/bl32/tsp/tsp.mk000066400000000000000000000047441322600646200207240ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # INCLUDES += -Iinclude/bl32/tsp BL32_SOURCES += bl32/tsp/tsp_main.c \ bl32/tsp/aarch64/tsp_entrypoint.S \ bl32/tsp/aarch64/tsp_exceptions.S \ bl32/tsp/aarch64/tsp_request.S \ bl32/tsp/tsp_interrupt.c \ bl32/tsp/tsp_timer.c \ common/aarch64/early_exceptions.S \ lib/locks/exclusive/spinlock.S BL32_LINKERFILE := bl32/tsp/tsp.ld.S # This flag determines if the TSPD initializes BL3-2 in tspd_init() (synchronous # method) or configures BL3-1 to pass control to BL3-2 instead of BL3-3 # (asynchronous method). TSP_INIT_ASYNC := 0 $(eval $(call assert_boolean,TSP_INIT_ASYNC)) $(eval $(call add_define,TSP_INIT_ASYNC)) # Include the platform-specific TSP Makefile # If no platform-specific TSP Makefile exists, it means TSP is not supported # on this platform. TSP_PLAT_MAKEFILE := plat/${PLAT}/tsp/tsp-${PLAT}.mk ifeq (,$(wildcard ${TSP_PLAT_MAKEFILE})) $(error TSP is not supported on platform ${PLAT}) else include ${TSP_PLAT_MAKEFILE} endif arm-trusted-firmware-1.0-aw-6/bl32/tsp/tsp_interrupt.c000066400000000000000000000120231322600646200226400ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include "tsp_private.h" /******************************************************************************* * This function updates the TSP statistics for FIQs handled synchronously i.e * the ones that have been handed over by the TSPD. It also keeps count of the * number of times control was passed back to the TSPD after handling an FIQ. * In the future it will be possible that the TSPD hands over an FIQ to the TSP * but does not expect it to return execution. This statistic will be useful to * distinguish between these two models of synchronous FIQ handling. * The 'elr_el3' parameter contains the address of the instruction in normal * world where this FIQ was generated. ******************************************************************************/ void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); tsp_stats[linear_id].sync_fiq_count++; if (type == TSP_HANDLE_FIQ_AND_RETURN) tsp_stats[linear_id].sync_fiq_ret_count++; #if LOG_LEVEL >= LOG_LEVEL_VERBOSE spin_lock(&console_lock); VERBOSE("TSP: cpu 0x%x sync fiq request from 0x%llx\n", mpidr, elr_el3); VERBOSE("TSP: cpu 0x%x: %d sync fiq requests, %d sync fiq returns\n", mpidr, tsp_stats[linear_id].sync_fiq_count, tsp_stats[linear_id].sync_fiq_ret_count); spin_unlock(&console_lock); #endif } /******************************************************************************* * TSP FIQ handler called as a part of both synchronous and asynchronous * handling of FIQ interrupts. It returns 0 upon successfully handling a S-EL1 * FIQ and treats all other FIQs as EL3 interrupts. It assumes that the GIC * architecture version in v2.0 and the secure physical timer interrupt is the * only S-EL1 interrupt that it needs to handle. ******************************************************************************/ int32_t tsp_fiq_handler(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr), id; /* * Get the highest priority pending interrupt id and see if it is the * secure physical generic timer interrupt in which case, handle it. * Otherwise throw this interrupt at the EL3 firmware. */ id = plat_ic_get_pending_interrupt_id(); /* TSP can only handle the secure physical timer interrupt */ if (id != TSP_IRQ_SEC_PHY_TIMER) return TSP_EL3_FIQ; /* * Handle the interrupt. Also sanity check if it has been preempted by * another secure interrupt through an assertion. */ id = plat_ic_acknowledge_interrupt(); assert(id == TSP_IRQ_SEC_PHY_TIMER); tsp_generic_timer_handler(); plat_ic_end_of_interrupt(id); /* Update the statistics and print some messages */ tsp_stats[linear_id].fiq_count++; #if LOG_LEVEL >= LOG_LEVEL_VERBOSE spin_lock(&console_lock); VERBOSE("TSP: cpu 0x%x handled fiq %d\n", mpidr, id); VERBOSE("TSP: cpu 0x%x: %d fiq requests\n", mpidr, tsp_stats[linear_id].fiq_count); spin_unlock(&console_lock); #endif return 0; } int32_t tsp_irq_received(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); tsp_stats[linear_id].irq_count++; #if LOG_LEVEL >= LOG_LEVEL_VERBOSE spin_lock(&console_lock); VERBOSE("TSP: cpu 0x%x received irq\n", mpidr); VERBOSE("TSP: cpu 0x%x: %d irq requests\n", mpidr, tsp_stats[linear_id].irq_count); spin_unlock(&console_lock); #endif return TSP_PREEMPTED; } arm-trusted-firmware-1.0-aw-6/bl32/tsp/tsp_main.c000066400000000000000000000356671322600646200215530ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include "tsp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __COHERENT_RAM_END__; /******************************************************************************* * Lock to control access to the console ******************************************************************************/ spinlock_t console_lock; /******************************************************************************* * Per cpu data structure to populate parameters for an SMC in C code and use * a pointer to this structure in assembler code to populate x0-x7 ******************************************************************************/ static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; /******************************************************************************* * Per cpu data structure to keep track of TSP activity ******************************************************************************/ work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; /******************************************************************************* * The BL32 memory footprint starts with an RO sections and ends * with a section for coherent RAM. Use it to find the memory size ******************************************************************************/ #define BL32_TOTAL_BASE (unsigned long)(&__RO_START__) #define BL32_TOTAL_LIMIT (unsigned long)(&__COHERENT_RAM_END__) static tsp_args_t *set_smc_args(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id; tsp_args_t *pcpu_smc_args; /* * Return to Secure Monitor by raising an SMC. The results of the * service are passed as an arguments to the SMC */ linear_id = platform_get_core_pos(mpidr); pcpu_smc_args = &tsp_smc_args[linear_id]; write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0); write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2); write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3); write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4); write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5); write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6); write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7); return pcpu_smc_args; } /******************************************************************************* * TSP main entry point where it gets the opportunity to initialize its secure * state/applications. Once the state is initialized, it must return to the * SPD with a pointer to the 'tsp_vector_table' jump table. ******************************************************************************/ uint64_t tsp_main(void) { NOTICE("TSP: %s\n", version_string); NOTICE("TSP: %s\n", build_message); INFO("TSP: Total memory base : 0x%x\n", (unsigned long)BL32_TOTAL_BASE); INFO("TSP: Total memory size : 0x%x bytes\n", (unsigned long)(BL32_TOTAL_LIMIT - BL32_TOTAL_BASE)); uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* Initialize the platform */ tsp_platform_setup(); /* Initialize secure/applications state here */ tsp_generic_timer_start(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_on_count++; #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_on_count); spin_unlock(&console_lock); #endif return (uint64_t) &tsp_vector_table; } /******************************************************************************* * This function performs any remaining book keeping in the test secure payload * after this cpu's architectural state has been setup in response to an earlier * psci cpu_on request. ******************************************************************************/ tsp_args_t *tsp_cpu_on_main(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* Initialize secure/applications state here */ tsp_generic_timer_start(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_on_count++; #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); INFO("TSP: cpu 0x%x turned on\n", mpidr); INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu on requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_on_count); spin_unlock(&console_lock); #endif /* Indicate to the SPD that we have completed turned ourselves on */ return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * This function performs any remaining book keeping in the test secure payload * before this cpu is turned off in response to a psci cpu_off request. ******************************************************************************/ tsp_args_t *tsp_cpu_off_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* * This cpu is being turned off, so disable the timer to prevent the * secure timer interrupt from interfering with power down. A pending * interrupt will be lost but we do not care as we are turning off. */ tsp_generic_timer_stop(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_off_count++; #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); INFO("TSP: cpu 0x%x off request\n", mpidr); INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu off requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_off_count); spin_unlock(&console_lock); #endif /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * This function performs any book keeping in the test secure payload before * this cpu's architectural state is saved in response to an earlier psci * cpu_suspend request. ******************************************************************************/ tsp_args_t *tsp_cpu_suspend_main(uint64_t power_state, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* * Save the time context and disable it to prevent the secure timer * interrupt from interfering with wakeup from the suspend state. */ tsp_generic_timer_save(); tsp_generic_timer_stop(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_suspend_count++; #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); INFO("TSP: cpu 0x%x suspend request. power state: 0x%x\n", mpidr, power_state); INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_suspend_count); spin_unlock(&console_lock); #endif /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * This function performs any book keeping in the test secure payload after this * cpu's architectural state has been restored after wakeup from an earlier psci * cpu_suspend request. ******************************************************************************/ tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* Restore the generic timer context */ tsp_generic_timer_restore(); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; tsp_stats[linear_id].cpu_resume_count++; #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); INFO("TSP: cpu 0x%x resumed. suspend level %d\n", mpidr, suspend_level); INFO("TSP: cpu 0x%x: %d smcs, %d erets %d cpu suspend requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count, tsp_stats[linear_id].cpu_suspend_count); spin_unlock(&console_lock); #endif /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * This function performs any remaining bookkeeping in the test secure payload * before the system is switched off (in response to a psci SYSTEM_OFF request) ******************************************************************************/ tsp_args_t *tsp_system_off_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); INFO("TSP: cpu 0x%x SYSTEM_OFF request\n", mpidr); INFO("TSP: cpu 0x%x: %d smcs, %d erets requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count); spin_unlock(&console_lock); #endif /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * This function performs any remaining bookkeeping in the test secure payload * before the system is reset (in response to a psci SYSTEM_RESET request) ******************************************************************************/ tsp_args_t *tsp_system_reset_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; #if LOG_LEVEL >= LOG_LEVEL_INFO spin_lock(&console_lock); INFO("TSP: cpu 0x%x SYSTEM_RESET request\n", mpidr); INFO("TSP: cpu 0x%x: %d smcs, %d erets requests\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count); spin_unlock(&console_lock); #endif /* Indicate to the SPD that we have completed this request */ return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0); } /******************************************************************************* * TSP fast smc handler. The secure monitor jumps to this function by * doing the ERET after populating X0-X7 registers. The arguments are received * in the function arguments in order. Once the service is rendered, this * function returns to Secure Monitor by raising SMC. ******************************************************************************/ tsp_args_t *tsp_smc_handler(uint64_t func, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7) { uint64_t results[2]; uint64_t service_args[2]; uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); /* Update this cpu's statistics */ tsp_stats[linear_id].smc_count++; tsp_stats[linear_id].eret_count++; INFO("TSP: cpu 0x%x received %s smc 0x%x\n", read_mpidr(), ((func >> 31) & 1) == 1 ? "fast" : "standard", func); INFO("TSP: cpu 0x%x: %d smcs, %d erets\n", mpidr, tsp_stats[linear_id].smc_count, tsp_stats[linear_id].eret_count); /* Render secure services and obtain results here */ results[0] = arg1; results[1] = arg2; /* * Request a service back from dispatcher/secure monitor. This call * return and thereafter resume exectuion */ tsp_get_magic(service_args); /* Determine the function to perform based on the function ID */ switch (TSP_BARE_FID(func)) { case TSP_ADD: results[0] += service_args[0]; results[1] += service_args[1]; break; case TSP_SUB: results[0] -= service_args[0]; results[1] -= service_args[1]; break; case TSP_MUL: results[0] *= service_args[0]; results[1] *= service_args[1]; break; case TSP_DIV: results[0] /= service_args[0] ? service_args[0] : 1; results[1] /= service_args[1] ? service_args[1] : 1; break; default: break; } return set_smc_args(func, 0, results[0], results[1], 0, 0, 0, 0); } arm-trusted-firmware-1.0-aw-6/bl32/tsp/tsp_private.h000066400000000000000000000106661322600646200222760ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TSP_PRIVATE_H__ #define __TSP_PRIVATE_H__ /* Definitions to help the assembler access the SMC/ERET args structure */ #define TSP_ARGS_SIZE 0x40 #define TSP_ARG0 0x0 #define TSP_ARG1 0x8 #define TSP_ARG2 0x10 #define TSP_ARG3 0x18 #define TSP_ARG4 0x20 #define TSP_ARG5 0x28 #define TSP_ARG6 0x30 #define TSP_ARG7 0x38 #define TSP_ARGS_END 0x40 #ifndef __ASSEMBLY__ #include #include /* For CACHE_WRITEBACK_GRANULE */ #include #include #include typedef struct work_statistics { uint32_t fiq_count; /* Number of FIQs on this cpu */ uint32_t irq_count; /* Number of IRQs on this cpu */ uint32_t sync_fiq_count; /* Number of sync. fiqs on this cpu */ uint32_t sync_fiq_ret_count; /* Number of fiq returns on this cpu */ uint32_t smc_count; /* Number of returns on this cpu */ uint32_t eret_count; /* Number of entries on this cpu */ uint32_t cpu_on_count; /* Number of cpu on requests */ uint32_t cpu_off_count; /* Number of cpu off requests */ uint32_t cpu_suspend_count; /* Number of cpu suspend requests */ uint32_t cpu_resume_count; /* Number of cpu resume requests */ } __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t; typedef struct tsp_args { uint64_t _regs[TSP_ARGS_END >> 3]; } __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t; /* Macros to access members of the above structure using their offsets */ #define read_sp_arg(args, offset) ((args)->_regs[offset >> 3]) #define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \ = val) /* * Ensure that the assembler's view of the size of the tsp_args is the * same as the compilers */ CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch); void tsp_get_magic(uint64_t args[4]); tsp_args_t *tsp_cpu_resume_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7); tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7); tsp_args_t *tsp_cpu_on_main(void); tsp_args_t *tsp_cpu_off_main(uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5, uint64_t arg6, uint64_t arg7); /* Generic Timer functions */ void tsp_generic_timer_start(void); void tsp_generic_timer_handler(void); void tsp_generic_timer_stop(void); void tsp_generic_timer_save(void); void tsp_generic_timer_restore(void); /* FIQ management functions */ void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3); /* Data structure to keep track of TSP statistics */ extern spinlock_t console_lock; extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; /* Vector table of jumps */ extern tsp_vectors_t tsp_vector_table; #endif /* __ASSEMBLY__ */ #endif /* __TSP_PRIVATE_H__ */ arm-trusted-firmware-1.0-aw-6/bl32/tsp/tsp_timer.c000066400000000000000000000106511322600646200217310ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "tsp_private.h" /******************************************************************************* * Data structure to keep track of per-cpu secure generic timer context across * power management operations. ******************************************************************************/ typedef struct timer_context { uint64_t cval; uint32_t ctl; } timer_context_t; static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT]; /******************************************************************************* * This function initializes the generic timer to fire every 0.5 second ******************************************************************************/ void tsp_generic_timer_start(void) { uint64_t cval; uint32_t ctl = 0; /* The timer will fire every 0.5 second */ cval = read_cntpct_el0() + (read_cntfrq_el0() >> 1); write_cntps_cval_el1(cval); /* Enable the secure physical timer */ set_cntp_ctl_enable(ctl); write_cntps_ctl_el1(ctl); } /******************************************************************************* * This function deasserts the timer interrupt and sets it up again ******************************************************************************/ void tsp_generic_timer_handler(void) { /* Ensure that the timer did assert the interrupt */ assert(get_cntp_ctl_istatus(read_cntps_ctl_el1())); /* * Disable the timer and reprogram it. The barriers ensure that there is * no reordering of instructions around the reprogramming code. */ isb(); write_cntps_ctl_el1(0); tsp_generic_timer_start(); isb(); } /******************************************************************************* * This function deasserts the timer interrupt prior to cpu power down ******************************************************************************/ void tsp_generic_timer_stop(void) { /* Disable the timer */ write_cntps_ctl_el1(0); } /******************************************************************************* * This function saves the timer context prior to cpu suspension ******************************************************************************/ void tsp_generic_timer_save(void) { uint32_t linear_id = platform_get_core_pos(read_mpidr()); pcpu_timer_context[linear_id].cval = read_cntps_cval_el1(); pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1(); flush_dcache_range((uint64_t) &pcpu_timer_context[linear_id], sizeof(pcpu_timer_context[linear_id])); } /******************************************************************************* * This function restores the timer context post cpu resummption ******************************************************************************/ void tsp_generic_timer_restore(void) { uint32_t linear_id = platform_get_core_pos(read_mpidr()); write_cntps_cval_el1(pcpu_timer_context[linear_id].cval); write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl); } arm-trusted-firmware-1.0-aw-6/common/000077500000000000000000000000001322600646200174745ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/common/aarch64/000077500000000000000000000000001322600646200207245ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/common/aarch64/debug.S000066400000000000000000000125011322600646200221350ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include .globl asm_print_str .globl asm_print_hex .globl asm_assert .globl do_panic /* Since the max decimal input number is 65536 */ #define MAX_DEC_DIVISOR 10000 /* The offset to add to get ascii for numerals '0 - 9' */ #define ASCII_OFFSET_NUM 0x30 #if ASM_ASSERTION .section .rodata.assert_str, "aS" assert_msg1: .asciz "ASSERT: File " assert_msg2: .asciz " Line " /* * This macro is intended to be used to print the * line number in decimal. Used by asm_assert macro. * The max number expected is 65536. * In: x4 = the decimal to print. * Clobber: x30, x0, x1, x2, x5, x6 */ .macro asm_print_line_dec mov x6, #10 /* Divide by 10 after every loop iteration */ mov x5, #MAX_DEC_DIVISOR dec_print_loop: udiv x0, x4, x5 /* Get the quotient */ msub x4, x0, x5, x4 /* Find the remainder */ add x0, x0, #ASCII_OFFSET_NUM /* Convert to ascii */ bl plat_crash_console_putc udiv x5, x5, x6 /* Reduce divisor */ cbnz x5, dec_print_loop .endm /* --------------------------------------------------------------------------- * Assertion support in assembly. * The below function helps to support assertions in assembly where we do not * have a C runtime stack. Arguments to the function are : * x0 - File name * x1 - Line no * Clobber list : x30, x0, x1, x2, x3, x4, x5, x6. * --------------------------------------------------------------------------- */ func asm_assert mov x5, x0 mov x6, x1 /* Ensure the console is initialized */ bl plat_crash_console_init /* Check if the console is initialized */ cbz x0, _assert_loop /* The console is initialized */ adr x4, assert_msg1 bl asm_print_str mov x4, x5 bl asm_print_str adr x4, assert_msg2 bl asm_print_str /* Check if line number higher than max permitted */ tst x6, #~0xffff b.ne _assert_loop mov x4, x6 asm_print_line_dec _assert_loop: b _assert_loop #endif /* * This function prints a string from address in x4. * In: x4 = pointer to string. * Clobber: x30, x0, x1, x2, x3 */ func asm_print_str mov x3, x30 1: ldrb w0, [x4], #0x1 cbz x0, 2f bl plat_crash_console_putc b 1b 2: ret x3 /* * This function prints a hexadecimal number in x4. * In: x4 = the hexadecimal to print. * Clobber: x30, x0, x5, x1, x2, x3 */ func asm_print_hex mov x3, x30 mov x5, #64 /* No of bits to convert to ascii */ 1: sub x5, x5, #4 lsrv x0, x4, x5 and x0, x0, #0xf cmp x0, #0xA b.lo 2f /* Add by 0x27 in addition to ASCII_OFFSET_NUM * to get ascii for characters 'a - f'. */ add x0, x0, #0x27 2: add x0, x0, #ASCII_OFFSET_NUM bl plat_crash_console_putc cbnz x5, 1b ret x3 /*********************************************************** * The common implementation of do_panic for all BL stages ***********************************************************/ .section .rodata.panic_str, "aS" panic_msg: .asciz "PANIC at PC : 0x" /* --------------------------------------------------------------------------- * do_panic assumes that it is invoked from a C Runtime Environment ie a * valid stack exists. This call will not return. * Clobber list : if CRASH_REPORTING is not enabled then x30, x0 - x6 * --------------------------------------------------------------------------- */ /* This is for the non el3 BL stages to compile through */ .weak el3_panic func do_panic #if CRASH_REPORTING str x0, [sp, #-0x10]! mrs x0, currentel ubfx x0, x0, #2, #2 cmp x0, #0x3 ldr x0, [sp], #0x10 b.eq el3_panic #endif panic_common: /* * el3_panic will be redefined by the BL31 * crash reporting mechanism (if enabled) */ el3_panic: mov x6, x30 bl plat_crash_console_init /* Check if the console is initialized */ cbz x0, _panic_loop /* The console is initialized */ adr x4, panic_msg bl asm_print_str mov x4, x6 /* The panic location is lr -4 */ sub x4, x4, #4 bl asm_print_hex _panic_loop: b _panic_loop arm-trusted-firmware-1.0-aw-6/common/aarch64/early_exceptions.S000066400000000000000000000107171322600646200244330ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include .globl early_exceptions .section .vectors, "ax"; .align 11 /* ----------------------------------------------------- * Very simple stackless exception handlers used by BL2 * and BL3-1 bootloader stages. BL3-1 uses them before * stacks are setup. BL2 uses them throughout. * ----------------------------------------------------- */ .align 7 early_exceptions: /* ----------------------------------------------------- * Current EL with SP0 : 0x0 - 0x180 * ----------------------------------------------------- */ SynchronousExceptionSP0: mov x0, #SYNC_EXCEPTION_SP_EL0 bl plat_report_exception b SynchronousExceptionSP0 check_vector_size SynchronousExceptionSP0 .align 7 IrqSP0: mov x0, #IRQ_SP_EL0 bl plat_report_exception b IrqSP0 check_vector_size IrqSP0 .align 7 FiqSP0: mov x0, #FIQ_SP_EL0 bl plat_report_exception b FiqSP0 check_vector_size FiqSP0 .align 7 SErrorSP0: mov x0, #SERROR_SP_EL0 bl plat_report_exception b SErrorSP0 check_vector_size SErrorSP0 /* ----------------------------------------------------- * Current EL with SPx: 0x200 - 0x380 * ----------------------------------------------------- */ .align 7 SynchronousExceptionSPx: mov x0, #SYNC_EXCEPTION_SP_ELX bl plat_report_exception b SynchronousExceptionSPx check_vector_size SynchronousExceptionSPx .align 7 IrqSPx: mov x0, #IRQ_SP_ELX bl plat_report_exception b IrqSPx check_vector_size IrqSPx .align 7 FiqSPx: mov x0, #FIQ_SP_ELX bl plat_report_exception b FiqSPx check_vector_size FiqSPx .align 7 SErrorSPx: mov x0, #SERROR_SP_ELX bl plat_report_exception b SErrorSPx check_vector_size SErrorSPx /* ----------------------------------------------------- * Lower EL using AArch64 : 0x400 - 0x580 * ----------------------------------------------------- */ .align 7 SynchronousExceptionA64: mov x0, #SYNC_EXCEPTION_AARCH64 bl plat_report_exception b SynchronousExceptionA64 check_vector_size SynchronousExceptionA64 .align 7 IrqA64: mov x0, #IRQ_AARCH64 bl plat_report_exception b IrqA64 check_vector_size IrqA64 .align 7 FiqA64: mov x0, #FIQ_AARCH64 bl plat_report_exception b FiqA64 check_vector_size FiqA64 .align 7 SErrorA64: mov x0, #SERROR_AARCH64 bl plat_report_exception b SErrorA64 check_vector_size SErrorA64 /* ----------------------------------------------------- * Lower EL using AArch32 : 0x0 - 0x180 * ----------------------------------------------------- */ .align 7 SynchronousExceptionA32: mov x0, #SYNC_EXCEPTION_AARCH32 bl plat_report_exception b SynchronousExceptionA32 check_vector_size SynchronousExceptionA32 .align 7 IrqA32: mov x0, #IRQ_AARCH32 bl plat_report_exception b IrqA32 check_vector_size IrqA32 .align 7 FiqA32: mov x0, #FIQ_AARCH32 bl plat_report_exception b FiqA32 check_vector_size FiqA32 .align 7 SErrorA32: mov x0, #SERROR_AARCH32 bl plat_report_exception b SErrorA32 check_vector_size SErrorA32 arm-trusted-firmware-1.0-aw-6/common/bl_common.c000066400000000000000000000241221322600646200216060ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include unsigned long page_align(unsigned long value, unsigned dir) { unsigned long page_size = 1 << FOUR_KB_SHIFT; /* Round up the limit to the next page boundary */ if (value & (page_size - 1)) { value &= ~(page_size - 1); if (dir == UP) value += page_size; } return value; } static inline unsigned int is_page_aligned (unsigned long addr) { const unsigned long page_size = 1 << FOUR_KB_SHIFT; return (addr & (page_size - 1)) == 0; } void change_security_state(unsigned int target_security_state) { unsigned long scr = read_scr(); assert(sec_state_is_valid(target_security_state)); if (target_security_state == SECURE) scr &= ~SCR_NS_BIT; else scr |= SCR_NS_BIT; write_scr(scr); } /****************************************************************************** * Determine whether the memory region delimited by 'addr' and 'size' is free, * given the extents of free memory. * Return 1 if it is free, 0 otherwise. *****************************************************************************/ static int is_mem_free(uint64_t free_base, size_t free_size, uint64_t addr, size_t size) { return (addr >= free_base) && (addr + size <= free_base + free_size); } /****************************************************************************** * Inside a given memory region, determine whether a sub-region of memory is * closer from the top or the bottom of the encompassing region. Return the * size of the smallest chunk of free memory surrounding the sub-region in * 'small_chunk_size'. *****************************************************************************/ static unsigned int choose_mem_pos(uint64_t mem_start, uint64_t mem_end, uint64_t submem_start, uint64_t submem_end, size_t *small_chunk_size) { size_t top_chunk_size, bottom_chunk_size; assert(mem_start <= submem_start); assert(submem_start <= submem_end); assert(submem_end <= mem_end); assert(small_chunk_size != NULL); top_chunk_size = mem_end - submem_end; bottom_chunk_size = submem_start - mem_start; if (top_chunk_size < bottom_chunk_size) { *small_chunk_size = top_chunk_size; return TOP; } else { *small_chunk_size = bottom_chunk_size; return BOTTOM; } } /****************************************************************************** * Reserve the memory region delimited by 'addr' and 'size'. The extents of free * memory are passed in 'free_base' and 'free_size' and they will be updated to * reflect the memory usage. * The caller must ensure the memory to reserve is free. *****************************************************************************/ void reserve_mem(uint64_t *free_base, size_t *free_size, uint64_t addr, size_t size) { size_t discard_size; size_t reserved_size; unsigned int pos; assert(free_base != NULL); assert(free_size != NULL); assert(is_mem_free(*free_base, *free_size, addr, size)); pos = choose_mem_pos(*free_base, *free_base + *free_size, addr, addr + size, &discard_size); reserved_size = size + discard_size; *free_size -= reserved_size; if (pos == BOTTOM) *free_base = addr + size; VERBOSE("Reserved %u bytes (discarded %u bytes %s)\n", reserved_size, discard_size, pos == TOP ? "above" : "below"); } static void dump_load_info(unsigned long image_load_addr, unsigned long image_size, const meminfo_t *mem_layout) { INFO("Trying to load image at address 0x%lx, size = 0x%lx\n", image_load_addr, image_size); INFO("Current memory layout:\n"); INFO(" total region = [0x%lx, 0x%lx]\n", mem_layout->total_base, mem_layout->total_base + mem_layout->total_size); INFO(" free region = [0x%lx, 0x%lx]\n", mem_layout->free_base, mem_layout->free_base + mem_layout->free_size); } /* Generic function to return the size of an image */ unsigned long image_size(const char *image_name) { uintptr_t dev_handle; uintptr_t image_handle; uintptr_t image_spec; size_t image_size = 0; int io_result = IO_FAIL; assert(image_name != NULL); /* Obtain a reference to the image by querying the platform layer */ io_result = plat_get_image_source(image_name, &dev_handle, &image_spec); if (io_result != IO_SUCCESS) { WARN("Failed to obtain reference to image '%s' (%i)\n", image_name, io_result); return 0; } /* Attempt to access the image */ io_result = io_open(dev_handle, image_spec, &image_handle); if (io_result != IO_SUCCESS) { WARN("Failed to access image '%s' (%i)\n", image_name, io_result); return 0; } /* Find the size of the image */ io_result = io_size(image_handle, &image_size); if ((io_result != IO_SUCCESS) || (image_size == 0)) { WARN("Failed to determine the size of the image '%s' file (%i)\n", image_name, io_result); } io_result = io_close(image_handle); /* Ignore improbable/unrecoverable error in 'close' */ /* TODO: Consider maintaining open device connection from this * bootloader stage */ io_result = io_dev_close(dev_handle); /* Ignore improbable/unrecoverable error in 'dev_close' */ return image_size; } /******************************************************************************* * Generic function to load an image at a specific address given a name and * extents of free memory. It updates the memory layout if the load is * successful, as well as the image information and the entry point information. * The caller might pass a NULL pointer for the entry point if it is not * interested in this information, e.g. because the image just needs to be * loaded in memory but won't ever be executed. * Returns 0 on success, a negative error code otherwise. ******************************************************************************/ int load_image(meminfo_t *mem_layout, const char *image_name, uint64_t image_base, image_info_t *image_data, entry_point_info_t *entry_point_info) { uintptr_t dev_handle; uintptr_t image_handle; uintptr_t image_spec; size_t image_size; size_t bytes_read; int io_result = IO_FAIL; assert(mem_layout != NULL); assert(image_name != NULL); assert(image_data != NULL); assert(image_data->h.version >= VERSION_1); /* Obtain a reference to the image by querying the platform layer */ io_result = plat_get_image_source(image_name, &dev_handle, &image_spec); if (io_result != IO_SUCCESS) { WARN("Failed to obtain reference to image '%s' (%i)\n", image_name, io_result); return io_result; } /* Attempt to access the image */ io_result = io_open(dev_handle, image_spec, &image_handle); if (io_result != IO_SUCCESS) { WARN("Failed to access image '%s' (%i)\n", image_name, io_result); return io_result; } INFO("Loading file '%s' at address 0x%lx\n", image_name, image_base); /* Find the size of the image */ io_result = io_size(image_handle, &image_size); if ((io_result != IO_SUCCESS) || (image_size == 0)) { WARN("Failed to determine the size of the image '%s' file (%i)\n", image_name, io_result); goto exit; } /* Check that the memory where the image will be loaded is free */ if (!is_mem_free(mem_layout->free_base, mem_layout->free_size, image_base, image_size)) { WARN("Failed to reserve memory: 0x%lx - 0x%lx\n", image_base, image_base + image_size); dump_load_info(image_base, image_size, mem_layout); io_result = -ENOMEM; goto exit; } /* We have enough space so load the image now */ /* TODO: Consider whether to try to recover/retry a partially successful read */ io_result = io_read(image_handle, image_base, image_size, &bytes_read); if ((io_result != IO_SUCCESS) || (bytes_read < image_size)) { WARN("Failed to load '%s' file (%i)\n", image_name, io_result); goto exit; } /* * Update the memory usage info. * This is done after the actual loading so that it is not updated when * the load is unsuccessful. */ reserve_mem(&mem_layout->free_base, &mem_layout->free_size, image_base, image_size); image_data->image_base = image_base; image_data->image_size = image_size; if (entry_point_info != NULL) entry_point_info->pc = image_base; /* * File has been successfully loaded. * Flush the image in TZRAM so that the next EL can see it. */ flush_dcache_range(image_base, image_size); INFO("File '%s' loaded: 0x%lx - 0x%lx\n", image_name, image_base, image_base + image_size); exit: io_close(image_handle); /* Ignore improbable/unrecoverable error in 'close' */ /* TODO: Consider maintaining open device connection from this bootloader stage */ io_dev_close(dev_handle); /* Ignore improbable/unrecoverable error in 'dev_close' */ return io_result; } arm-trusted-firmware-1.0-aw-6/common/tf_printf.c000066400000000000000000000101651322600646200216360ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include /*********************************************************** * The tf_printf implementation for all BL stages ***********************************************************/ static void unsigned_num_print(unsigned long int unum, unsigned int radix) { /* Just need enough space to store 64 bit decimal integer */ unsigned char num_buf[20]; int i = 0 , rem; do { rem = unum % radix; if (rem < 0xa) num_buf[i++] = '0' + rem; else num_buf[i++] = 'a' + (rem - 0xa); } while (unum /= radix); while (--i >= 0) putchar(num_buf[i]); } static void string_print(const char *str) { while (*str) putchar(*str++); } /******************************************************************* * Reduced format print for Trusted firmware. * The following formats are supported by this print * %x - 32 bit hexadecimal format * %llx and %lx -64 bit hexadecimal format * %s - string format * %d or %i - signed 32 bit decimal format * %u - unsigned 32 bit decimal format * %ld and %lld - signed 64 bit decimal format * %lu and %llu - unsigned 64 bit decimal format * Exits on all other formats. *******************************************************************/ void tf_printf(const char *fmt, ...) { va_list args; int bit64; int64_t num; uint64_t unum; char *str; va_start(args, fmt); while (*fmt) { bit64 = 0; if (*fmt == '%') { fmt++; /* Check the format specifier */ loop: switch (*fmt) { case 'i': /* Fall through to next one */ case 'd': if (bit64) num = va_arg(args, int64_t); else num = va_arg(args, int32_t); if (num < 0) { putchar('-'); unum = (unsigned long int)-num; } else unum = (unsigned long int)num; unsigned_num_print(unum, 10); break; case 's': str = va_arg(args, char *); string_print(str); break; case 'x': if (bit64) unum = va_arg(args, uint64_t); else unum = va_arg(args, uint32_t); unsigned_num_print(unum, 16); break; case 'p': unum =(uint64_t)va_arg(args, void *); unsigned_num_print(unum, 16); break; case 'z': fmt++; bit64 = sizeof(long) == 0x8 ? 1:0; goto loop; case 'l': bit64 = 1; fmt++; goto loop; case 'u': if (bit64) unum = va_arg(args, uint64_t); else unum = va_arg(args, uint32_t); unsigned_num_print(unum, 10); break; default: /* Exit on any other format specifier */ goto exit; } fmt++; continue; } //for windos newline"\r\n" else if (*fmt == '\n') { putchar('\r'); } putchar(*fmt++); } exit: va_end(args); } arm-trusted-firmware-1.0-aw-6/contributing.md000066400000000000000000000143031322600646200212360ustar00rootroot00000000000000Contributing to ARM Trusted Firmware ==================================== Before you start contributing to this project you must sign the ARM Contributor License Agreement (CLA). Individuals who want to contribute their own work must sign and return an Individual CLA. Companies that want to contribute must sign and return a Corporate CLA if their employees' intellectual property has been assigned to the employer. Copies of the CLAs are available from the [contributing page] of the ARM website. For this project, ARM also requires the GitHub account name(s) associated with each individual contributor or the designated employees of corporate contributors. Only contributions originating from these accounts will be considered covered by the CLA. To avoid delay, you should provide the Github account name(s) at the same time as the signed CLA. ARM reserves the right to not accept a contribution. This may be for technical, commercial or legal reasons. Getting Started --------------- * Make sure you have a [GitHub account]. * Create an [issue] for your work if one does not already exist. This gives everyone visibility of whether others are working on something similar. ARM licensees may contact ARM directly via their partner managers instead if they prefer. * Note that the [issue] tracker for this project is in a separate [issue tracking repository]. Please follow the guidelines in that repository. * If you intend to include Third Party IP in your contribution, please raise a separate [issue] for this and ensure that the changes that include Third Party IP are made on a separate topic branch. * [Fork][] [arm-trusted-firmware][] on GitHub. * Clone the fork to your own machine. * Create a local topic branch based on the [arm-trusted-firmware][] `master` branch. Making Changes -------------- * Make commits of logical units. See these general [Git guidelines] for contributing to a project. * Follow the [Linux coding style]; this style is enforced for the ARM Trusted Firmware project (style errors only, not warnings). * Use the checkpatch.pl script provided with the Linux source tree. A Makefile target is provided for convenience (see section 2 in the [User Guide]). * Keep the commits on topic. If you need to fix another bug or make another enhancement, please create a separate [issue] and address it on a separate topic branch. * Avoid long commit series. If you do have a long series, consider whether some commits should be squashed together or addressed in a separate topic. * Make sure your commit messages are in the proper format. If a commit fixes a GitHub [issue], include a reference (e.g. "fixes arm-software/tf-issues#45"); this ensures the [issue] is [automatically closed] when merged into the [arm-trusted-firmware] `master` branch. * Where appropriate, please update the documentation. * Consider whether the [User Guide], [Porting Guide], [Firmware Design] or other in-source documentation needs updating. * If this is your first contribution, you may add your name or your company name to the [Acknowledgements] file. * For topics with multiple commits, you should make all documentation changes (and nothing else) in the last commit of the series. Otherwise, include the documentation changes within the single commit. * Please test your changes. As a minimum, ensure UEFI boots to the shell on the Foundation FVP. See the "[Running the software]" section of the [User Guide] for more information. Submitting Changes ------------------ * Ensure we have your signed CLA. * Push your local changes to your fork of the repository. * Submit a [pull request] to the [arm-trusted-firmware] `integration` branch. * The changes in the [pull request] will then undergo further review and testing. Any review comments will be made as comments on the [pull request]. This may require you to do some rework. * When the changes are accepted, ARM will integrate them. * Typically, ARM will merge the [pull request] into the `integration` branch within the GitHub UI, creating a merge commit. * Please avoid creating merge commits in the [pull request] itself. * If the [pull request] is not based on a recent commit, ARM may rebase it onto the `master` branch first, or ask you to do this. * If the [pull request] cannot be automatically merged, ARM will ask you to rebase it onto the `master` branch. * After final integration testing, ARM will push your merge commit to the `master` branch. If a problem is found at this stage, the merge commit will be removed from the `integration` branch and ARM will ask you to create a new pull request to resolve the problem. * Please do not delete your topic branch until it is safely merged into the `master` branch. - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._ [User Guide]: ./docs/user-guide.md [Running the software]: ./docs/user-guide.md#6--running-the-software [Porting Guide]: ./docs/porting-guide.md [Firmware Design]: ./docs/firmware-design.md [Acknowledgements]: ./acknowledgements.md "Contributor acknowledgements" [contributing page]: http://www.arm.com/community/open-source-contributing.php [GitHub account]: https://github.com/signup/free [Fork]: https://help.github.com/articles/fork-a-repo [issue tracking repository]: https://github.com/ARM-software/tf-issues [issue]: https://github.com/ARM-software/tf-issues/issues [pull request]: https://help.github.com/articles/using-pull-requests [automatically closed]: https://help.github.com/articles/closing-issues-via-commit-messages [Git guidelines]: http://git-scm.com/book/ch5-2.html [Linux coding style]: https://www.kernel.org/doc/Documentation/CodingStyle [arm-trusted-firmware]: https://github.com/ARM-software/arm-trusted-firmware arm-trusted-firmware-1.0-aw-6/docs/000077500000000000000000000000001322600646200171345ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/docs/change-log.md000066400000000000000000000551251322600646200214720ustar00rootroot00000000000000ARM Trusted Firmware - version 1.0 ================================== New features ------------ * It is now possible to map higher physical addresses using non-flat virtual to physical address mappings in the MMU setup. * Wider use is now made of the per-CPU data cache in BL3-1 to store: * Pointers to the non-secure and secure security state contexts. * A pointer to the CPU-specific operations. * A pointer to PSCI specific information (for example the current power state). * A crash reporting buffer. * The following RAM usage improvements result in a BL3-1 RAM usage reduction from 96KB to 56KB (for FVP with TSPD), and a total RAM usage reduction across all images from 208KB to 88KB, compared to the previous release. * Removed the separate `early_exception` vectors from BL3-1 (2KB code size saving). * Removed NSRAM from the FVP memory map, allowing the removal of one (4KB) translation table. * Eliminated the internal `psci_suspend_context` array, saving 2KB. * Correctly dimensioned the PSCI `aff_map_node` array, saving 1.5KB in the FVP port. * Removed calling CPU mpidr from the bakery lock API, saving 160 bytes. * Removed current CPU mpidr from PSCI common code, saving 160 bytes. * Inlined the mmio accessor functions, saving 360 bytes. * Fully reclaimed all BL1 RW memory and BL2 memory on the FVP port by overlaying the BL3-1/BL3-2 NOBITS sections on top of these at runtime. * Made storing the FP register context optional, saving 0.5KB per context (8KB on the FVP port, with TSPD enabled and running on 8 CPUs). * Implemented a leaner `tf_printf()` function, allowing the stack to be greatly reduced. * Removed coherent stacks from the codebase. Stacks allocated in normal memory are now used before and after the MMU is enabled. This saves 768 bytes per CPU in BL3-1. * Reworked the crash reporting in BL3-1 to use less stack. * Optimized the EL3 register state stored in the `cpu_context` structure so that registers that do not change during normal execution are re-initialized each time during cold/warm boot, rather than restored from memory. This saves about 1.2KB. * As a result of some of the above, reduced the runtime stack size in all BL images. For BL3-1, this saves 1KB per CPU. * PSCI SMC handler improvements to correctly handle calls from secure states and from AArch32. * CPU contexts are now initialized from the `entry_point_info`. BL3-1 fully determines the exception level to use for the non-trusted firmware (BL3-3) based on the SPSR value provided by the BL2 platform code (or otherwise provided to BL3-1). This allows platform code to directly run non-trusted firmware payloads at either EL2 or EL1 without requiring an EL2 stub or OS loader. * Code refactoring improvements: * Refactored `fvp_config` into a common platform header. * Refactored the fvp gic code to be a generic driver that no longer has an explicit dependency on platform code. * Refactored the CCI-400 driver to not have dependency on platform code. * Simplified the IO driver so it's no longer necessary to call `io_init()` and moved all the IO storage framework code to one place. * Simplified the interface the the TZC-400 driver. * Clarified the platform porting interface to the TSP. * Reworked the TSPD setup code to support the alternate BL3-2 intialization flow where BL3-1 generic code hands control to BL3-2, rather than expecting the TSPD to hand control directly to BL3-2. * Considerable rework to PSCI generic code to support CPU specific operations. * Improved console log output, by: * Adding the concept of debug log levels. * Rationalizing the existing debug messages and adding new ones. * Printing out the version of each BL stage at runtime. * Adding support for printing console output from assembler code, including when a crash occurs before the C runtime is initialized. * Moved up to the latest versions of the FVPs, toolchain, EDK2, kernel, Linaro file system and DS-5. * On the FVP port, made the use of the Trusted DRAM region optional at build time (off by default). Normal platforms will not have such a "ready-to-use" DRAM area so it is not a good example to use it. * Added support for PSCI `SYSTEM_OFF` and `SYSTEM_RESET` APIs. * Added support for CPU specific reset sequences, power down sequences and register dumping during crash reporting. The CPU specific reset sequences include support for errata workarounds. * Merged the Juno port into the master branch. Added support for CPU hotplug and CPU idle. Updated the user guide to describe how to build and run on the Juno platform. Issues resolved since last release ---------------------------------- * Removed the concept of top/bottom image loading. The image loader now automatically detects the position of the image inside the current memory layout and updates the layout to minimize fragementation. This resolves the image loader limitations of previously releases. There are currently no plans to support dynamic image loading. * CPU idle now works on the publicized version of the Foundation FVP. * All known issues relating to the compiler version used have now been resolved. This TF version uses Linaro toolchain 14.07 (based on GCC 4.9). Known issues ------------ * GICv3 support is experimental. The Linux kernel patches to support this are not widely available. There are known issues with GICv3 initialization in the ARM Trusted Firmware. * While this version greatly reduces the on-chip RAM requirements, there are further RAM usage enhancements that could be made. * The firmware design documentation for the Test Secure-EL1 Payload (TSP) and its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. * The Juno-specific firmware design documentation is incomplete. * Some recent enhancements to the FVP port have not yet been translated into the Juno port. These will be tracked via the tf-issues project. * The Linux kernel version referred to in the user guide has DVFS and HMP support disabled due to some known instabilities at the time of this release. A future kernel version will re-enable these features. * DS-5 v5.19 does not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in CADI server mode. This is because the `` reported by the FVP in this version has changed. For example, for the Cortex-A57x4-A53x4 Base FVP, the `` reported by the FVP is `FVP_Base_Cortex_A57x4_A53x4`, while DS-5 expects it to be `FVP_Base_A57x4_A53x4`. The temporary fix to this problem is to change the name of the FVP in `sw/debugger/configdb/Boards/ARM FVP/Base_A57x4_A53x4/cadi_config.xml`. Change the following line: System Generator:FVP_Base_A57x4_A53x4 to System Generator:FVP_Base_Cortex-A57x4_A53x4 A similar change can be made to the other Cortex-A57-A53 Base FVP variants. ARM Trusted Firmware - version 0.4 ================================== New features ------------ * Makefile improvements: * Improved dependency checking when building. * Removed `dump` target (build now always produces dump files). * Enabled platform ports to optionally make use of parts of the Trusted Firmware (e.g. BL3-1 only), rather than being forced to use all parts. Also made the `fip` target optional. * Specified the full path to source files and removed use of the `vpath` keyword. * Provided translation table library code for potential re-use by platforms other than the FVPs. * Moved architectural timer setup to platform-specific code. * Added standby state support to PSCI cpu_suspend implementation. * SRAM usage improvements: * Started using the `-ffunction-sections`, `-fdata-sections` and `--gc-sections` compiler/linker options to remove unused code and data from the images. Previously, all common functions were being built into all binary images, whether or not they were actually used. * Placed all assembler functions in their own section to allow more unused functions to be removed from images. * Updated BL1 and BL2 to use a single coherent stack each, rather than one per CPU. * Changed variables that were unnecessarily declared and initialized as non-const (i.e. in the .data section) so they are either uninitialized (zero init) or const. * Moved the Test Secure-EL1 Payload (BL3-2) to execute in Trusted SRAM by default. The option for it to run in Trusted DRAM remains. * Implemented a TrustZone Address Space Controller (TZC-400) driver. A default configuration is provided for the Base FVPs. This means the model parameter `-C bp.secure_memory=1` is now supported. * Started saving the PSCI cpu_suspend 'power_state' parameter prior to suspending a CPU. This allows platforms that implement multiple power-down states at the same affinity level to identify a specific state. * Refactored the entire codebase to reduce the amount of nesting in header files and to make the use of system/user includes more consistent. Also split platform.h to separate out the platform porting declarations from the required platform porting definitions and the definitions/declarations specific to the platform port. * Optimized the data cache clean/invalidate operations. * Improved the BL3-1 unhandled exception handling and reporting. Unhandled exceptions now result in a dump of registers to the console. * Major rework to the handover interface between BL stages, in particular the interface to BL3-1. The interface now conforms to a specification and is more future proof. * Added support for optionally making the BL3-1 entrypoint a reset handler (instead of BL1). This allows platforms with an alternative image loading architecture to re-use BL3-1 with fewer modifications to generic code. * Reserved some DDR DRAM for secure use on FVP platforms to avoid future compatibility problems with non-secure software. * Added support for secure interrupts targeting the Secure-EL1 Payload (SP) (using GICv2 routing only). Demonstrated this working by adding an interrupt target and supporting test code to the TSP. Also demonstrated non-secure interrupt handling during TSP processing. Issues resolved since last release ---------------------------------- * Now support use of the model parameter `-C bp.secure_memory=1` in the Base FVPs (see **New features**). * Support for secure world interrupt handling now available (see **New features**). * Made enough SRAM savings (see **New features**) to enable the Test Secure-EL1 Payload (BL3-2) to execute in Trusted SRAM by default. * The tested filesystem used for this release (Linaro AArch64 OpenEmbedded 14.04) now correctly reports progress in the console. * Improved the Makefile structure to make it easier to separate out parts of the Trusted Firmware for re-use in platform ports. Also, improved target dependency checking. Known issues ------------ * GICv3 support is experimental. The Linux kernel patches to support this are not widely available. There are known issues with GICv3 initialization in the ARM Trusted Firmware. * Dynamic image loading is not available yet. The current image loader implementation (used to load BL2 and all subsequent images) has some limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead to loading errors, even if the images should theoretically fit in memory. * The ARM Trusted Firmware still uses too much on-chip Trusted SRAM. A number of RAM usage enhancements have been identified to rectify this situation. * CPU idle does not work on the advertised version of the Foundation FVP. Some FVP fixes are required that are not available externally at the time of writing. This can be worked around by disabling CPU idle in the Linux kernel. * Various bugs in ARM Trusted Firmware, UEFI and the Linux kernel have been observed when using Linaro toolchain versions later than 13.11. Although most of these have been fixed, some remain at the time of writing. These mainly seem to relate to a subtle change in the way the compiler converts between 64-bit and 32-bit values (e.g. during casting operations), which reveals previously hidden bugs in client code. * The firmware design documentation for the Test Secure-EL1 Payload (TSP) and its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. ARM Trusted Firmware - version 0.3 ================================== New features ------------ * Support for Foundation FVP Version 2.0 added. The documented UEFI configuration disables some devices that are unavailable in the Foundation FVP, including MMC and CLCD. The resultant UEFI binary can be used on the AEMv8 and Cortex-A57-A53 Base FVPs, as well as the Foundation FVP. NOTE: The software will not work on Version 1.0 of the Foundation FVP. * Enabled third party contributions. Added a new contributing.md containing instructions for how to contribute and updated copyright text in all files to acknowledge contributors. * The PSCI CPU_SUSPEND API has been stabilised to the extent where it can be used for entry into power down states with the following restrictions: - Entry into standby states is not supported. - The API is only supported on the AEMv8 and Cortex-A57-A53 Base FVPs. * The PSCI AFFINITY_INFO api has undergone limited testing on the Base FVPs to allow experimental use. * Required C library and runtime header files are now included locally in ARM Trusted Firmware instead of depending on the toolchain standard include paths. The local implementation has been cleaned up and reduced in scope. * Added I/O abstraction framework, primarily to allow generic code to load images in a platform-independent way. The existing image loading code has been reworked to use the new framework. Semi-hosting and NOR flash I/O drivers are provided. * Introduced Firmware Image Package (FIP) handling code and tools. A FIP combines multiple firmware images with a Table of Contents (ToC) into a single binary image. The new FIP driver is another type of I/O driver. The Makefile builds a FIP by default and the FVP platform code expect to load a FIP from NOR flash, although some support for image loading using semi- hosting is retained. NOTE: Building a FIP by default is a non-backwards-compatible change. NOTE: Generic BL2 code now loads a BL3-3 (non-trusted firmware) image into DRAM instead of expecting this to be pre-loaded at known location. This is also a non-backwards-compatible change. NOTE: Some non-trusted firmware (e.g. UEFI) will need to be rebuilt so that it knows the new location to execute from and no longer needs to copy particular code modules to DRAM itself. * Reworked BL2 to BL3-1 handover interface. A new composite structure (bl31_args) holds the superset of information that needs to be passed from BL2 to BL3-1, including information on how handover execution control to BL3-2 (if present) and BL3-3 (non-trusted firmware). * Added library support for CPU context management, allowing the saving and restoring of - Shared system registers between Secure-EL1 and EL1. - VFP registers. - Essential EL3 system registers. * Added a framework for implementing EL3 runtime services. Reworked the PSCI implementation to be one such runtime service. * Reworked the exception handling logic, making use of both SP_EL0 and SP_EL3 stack pointers for determining the type of exception, managing general purpose and system register context on exception entry/exit, and handling SMCs. SMCs are directed to the correct EL3 runtime service. * Added support for a Test Secure-EL1 Payload (TSP) and a corresponding Dispatcher (TSPD), which is loaded as an EL3 runtime service. The TSPD implements Secure Monitor functionality such as world switching and EL1 context management, and is responsible for communication with the TSP. NOTE: The TSPD does not yet contain support for secure world interrupts. NOTE: The TSP/TSPD is not built by default. Issues resolved since last release ---------------------------------- * Support has been added for switching context between secure and normal worlds in EL3. * PSCI API calls `AFFINITY_INFO` & `PSCI_VERSION` have now been tested (to a limited extent). * The ARM Trusted Firmware build artifacts are now placed in the `./build` directory and sub-directories instead of being placed in the root of the project. * The ARM Trusted Firmware is now free from build warnings. Build warnings are now treated as errors. * The ARM Trusted Firmware now provides C library support locally within the project to maintain compatibility between toolchains/systems. * The PSCI locking code has been reworked so it no longer takes locks in an incorrect sequence. * The RAM-disk method of loading a Linux file-system has been confirmed to work with the ARM Trusted Firmware and Linux kernel version (based on version 3.13) used in this release, for both Foundation and Base FVPs. Known issues ------------ The following is a list of issues which are expected to be fixed in the future releases of the ARM Trusted Firmware. * The TrustZone Address Space Controller (TZC-400) is not being programmed yet. Use of model parameter `-C bp.secure_memory=1` is not supported. * No support yet for secure world interrupt handling. * GICv3 support is experimental. The Linux kernel patches to support this are not widely available. There are known issues with GICv3 initialization in the ARM Trusted Firmware. * Dynamic image loading is not available yet. The current image loader implementation (used to load BL2 and all subsequent images) has some limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead to loading errors, even if the images should theoretically fit in memory. * The ARM Trusted Firmware uses too much on-chip Trusted SRAM. Currently the Test Secure-EL1 Payload (BL3-2) executes in Trusted DRAM since there is not enough SRAM. A number of RAM usage enhancements have been identified to rectify this situation. * CPU idle does not work on the advertised version of the Foundation FVP. Some FVP fixes are required that are not available externally at the time of writing. * Various bugs in ARM Trusted Firmware, UEFI and the Linux kernel have been observed when using Linaro toolchain versions later than 13.11. Although most of these have been fixed, some remain at the time of writing. These mainly seem to relate to a subtle change in the way the compiler converts between 64-bit and 32-bit values (e.g. during casting operations), which reveals previously hidden bugs in client code. * The tested filesystem used for this release (Linaro AArch64 OpenEmbedded 14.01) does not report progress correctly in the console. It only seems to produce error output, not standard output. It otherwise appears to function correctly. Other filesystem versions on the same software stack do not exhibit the problem. * The Makefile structure doesn't make it easy to separate out parts of the Trusted Firmware for re-use in platform ports, for example if only BL3-1 is required in a platform port. Also, dependency checking in the Makefile is flawed. * The firmware design documentation for the Test Secure-EL1 Payload (TSP) and its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. ARM Trusted Firmware - version 0.2 ================================== New features ------------ * First source release. * Code for the PSCI suspend feature is supplied, although this is not enabled by default since there are known issues (see below). Issues resolved since last release ---------------------------------- * The "psci" nodes in the FDTs provided in this release now fully comply with the recommendations made in the PSCI specification. Known issues ------------ The following is a list of issues which are expected to be fixed in the future releases of the ARM Trusted Firmware. * The TrustZone Address Space Controller (TZC-400) is not being programmed yet. Use of model parameter `-C bp.secure_memory=1` is not supported. * No support yet for secure world interrupt handling or for switching context between secure and normal worlds in EL3. * GICv3 support is experimental. The Linux kernel patches to support this are not widely available. There are known issues with GICv3 initialization in the ARM Trusted Firmware. * Dynamic image loading is not available yet. The current image loader implementation (used to load BL2 and all subsequent images) has some limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead to loading errors, even if the images should theoretically fit in memory. * Although support for PSCI `CPU_SUSPEND` is present, it is not yet stable and ready for use. * PSCI API calls `AFFINITY_INFO` & `PSCI_VERSION` are implemented but have not been tested. * The ARM Trusted Firmware make files result in all build artifacts being placed in the root of the project. These should be placed in appropriate sub-directories. * The compilation of ARM Trusted Firmware is not free from compilation warnings. Some of these warnings have not been investigated yet so they could mask real bugs. * The ARM Trusted Firmware currently uses toolchain/system include files like stdio.h. It should provide versions of these within the project to maintain compatibility between toolchains/systems. * The PSCI code takes some locks in an incorrect sequence. This may cause problems with suspend and hotplug in certain conditions. * The Linux kernel used in this release is based on version 3.12-rc4. Using this kernel with the ARM Trusted Firmware fails to start the file-system as a RAM-disk. It fails to execute user-space `init` from the RAM-disk. As an alternative, the VirtioBlock mechanism can be used to provide a file-system to the kernel. - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._ arm-trusted-firmware-1.0-aw-6/docs/cpu-errata-workarounds.md000066400000000000000000000033271322600646200241020ustar00rootroot00000000000000ARM CPU Errata Workarounds ========================== ARM Trusted Firmware exports a series of build flags which control the errata workarounds that are applied to each CPU by the reset handler. The errata details can be found in the CPU specifc errata documents published by ARM. The errata workarounds are implemented for a particular revision or a set of processor revisions. This check is done in the debug build. Each errata workaround is identified by its `ID` as specified in the processor's errata notice document. The format of the define used to enable/disable the errata is `ERRATA__` where the `Processor name` is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU. All workarounds are disabled by default. The platform is reponsible for enabling these workarounds according to its requirement by defining the errata workaround build flags in the platform specific makefile. In the current implementation, a platform which has more than 1 variant with different revisions of a processor has no runtime mechanism available for it to specify which errata workarounds should be enabled or not. The value of the build flags are 0 by default, that is, disabled. Any other value will enable it. For Cortex A57, following errata build flags are defined : * `ERRATA_A57_806969`: This applies errata 806969 workaround to cortex a57 CPU. This needs to be enabled only for revision r0p0 of the CPU. * `ERRATA_A57_813420`: This applies errata 813420 workaround to cortex a57 CPU. This needs to be enabled only for revision r0p0 of the CPU. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2014, ARM Limited and Contributors. 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Introduction 2. Cold boot 3. EL3 runtime services framework 4. Power State Coordination Interface 5. Secure-EL1 Payloads and Dispatchers 6. Crash Reporting in BL3-1 7. CPU specific operations framework 8. Memory layout of BL images 9. Firmware Image Package (FIP) 10. Code Structure 11. References 1. Introduction ---------------- The ARM Trusted Firmware implements a subset of the Trusted Board Boot Requirements (TBBR) Platform Design Document (PDD) [1] for ARM reference platforms. The TBB sequence starts when the platform is powered on and runs up to the stage where it hands-off control to firmware running in the normal world in DRAM. This is the cold boot path. The ARM Trusted Firmware also implements the Power State Coordination Interface ([PSCI]) PDD [2] as a runtime service. PSCI is the interface from normal world software to firmware implementing power management use-cases (for example, secondary CPU boot, hotplug and idle). Normal world software can access ARM Trusted Firmware runtime services via the ARM SMC (Secure Monitor Call) instruction. The SMC instruction must be used as mandated by the [SMC Calling Convention PDD][SMCCC] [3]. The ARM Trusted Firmware implements a framework for configuring and managing interrupts generated in either security state. The details of the interrupt management framework and its design can be found in [ARM Trusted Firmware Interrupt Management Design guide][INTRG] [4]. 2. Cold boot ------------- The cold boot path starts when the platform is physically turned on. One of the CPUs released from reset is chosen as the primary CPU, and the remaining CPUs are considered secondary CPUs. The primary CPU is chosen through platform-specific means. The cold boot path is mainly executed by the primary CPU, other than essential CPU initialization executed by all CPUs. The secondary CPUs are kept in a safe platform-specific state until the primary CPU has performed enough initialization to boot them. The cold boot path in this implementation of the ARM Trusted Firmware is divided into five steps (in order of execution): * Boot Loader stage 1 (BL1) _AP Trusted ROM_ * Boot Loader stage 2 (BL2) _Trusted Boot Firmware_ * Boot Loader stage 3-1 (BL3-1) _EL3 Runtime Firmware_ * Boot Loader stage 3-2 (BL3-2) _Secure-EL1 Payload_ (optional) * Boot Loader stage 3-3 (BL3-3) _Non-trusted Firmware_ ARM development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a combination of the following types of memory regions. Each bootloader stage uses one or more of these memory regions. * Regions accessible from both non-secure and secure states. For example, non-trusted SRAM, ROM and DRAM. * Regions accessible from only the secure state. For example, trusted SRAM and ROM. The FVPs also implement the trusted DRAM which is statically configured. Additionally, the Base FVPs and Juno development platform configure the TrustZone Controller (TZC) to create a region in the DRAM which is accessible only from the secure state. The sections below provide the following details: * initialization and execution of the first three stages during cold boot * specification of the BL3-1 entrypoint requirements for use by alternative Trusted Boot Firmware in place of the provided BL1 and BL2 * changes in BL3-1 behavior when using the `RESET_TO_BL31` option which allows BL3-1 to run without BL1 and BL2 ### BL1 This stage begins execution from the platform's reset vector at EL3. The reset address is platform dependent but it is usually located in a Trusted ROM area. The BL1 data section is copied to trusted SRAM at runtime. On the ARM FVP port, BL1 code starts execution from the reset vector at address `0x00000000` (trusted ROM). The BL1 data section is copied to the start of trusted SRAM at address `0x04000000`. On the Juno ARM development platform port, BL1 code starts execution at `0x0BEC0000` (FLASH). The BL1 data section is copied to trusted SRAM at address `0x04001000. The functionality implemented by this stage is as follows. #### Determination of boot path Whenever a CPU is released from reset, BL1 needs to distinguish between a warm boot and a cold boot. This is done using platform-specific mechanisms (see the `platform_get_entrypoint()` function in the [Porting Guide]). In the case of a warm boot, a CPU is expected to continue execution from a seperate entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe platform-specific state (see the `plat_secondary_cold_boot_setup()` function in the [Porting Guide]) while the primary CPU executes the remaining cold boot path as described in the following sections. #### Architectural initialization BL1 performs minimal architectural initialization as follows. * Exception vectors BL1 sets up simple exception vectors for both synchronous and asynchronous exceptions. The default behavior upon receiving an exception is to populate a status code in the general purpose register `X0` and call the `plat_report_exception()` function (see the [Porting Guide]). The status code is one of: 0x0 : Synchronous exception from Current EL with SP_EL0 0x1 : IRQ exception from Current EL with SP_EL0 0x2 : FIQ exception from Current EL with SP_EL0 0x3 : System Error exception from Current EL with SP_EL0 0x4 : Synchronous exception from Current EL with SP_ELx 0x5 : IRQ exception from Current EL with SP_ELx 0x6 : FIQ exception from Current EL with SP_ELx 0x7 : System Error exception from Current EL with SP_ELx 0x8 : Synchronous exception from Lower EL using aarch64 0x9 : IRQ exception from Lower EL using aarch64 0xa : FIQ exception from Lower EL using aarch64 0xb : System Error exception from Lower EL using aarch64 0xc : Synchronous exception from Lower EL using aarch32 0xd : IRQ exception from Lower EL using aarch32 0xe : FIQ exception from Lower EL using aarch32 0xf : System Error exception from Lower EL using aarch32 The `plat_report_exception()` implementation on the ARM FVP port programs the Versatile Express System LED register in the following format to indicate the occurence of an unexpected exception: SYS_LED[0] - Security state (Secure=0/Non-Secure=1) SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value of the status code A write to the LED register reflects in the System LEDs (S6LED0..7) in the CLCD window of the FVP. BL1 does not expect to receive any exceptions other than the SMC exception. For the latter, BL1 installs a simple stub. The stub expects to receive only a single type of SMC (determined by its function ID in the general purpose register `X0`). This SMC is raised by BL2 to make BL1 pass control to BL3-1 (loaded by BL2) at EL3. Any other SMC leads to an assertion failure. * CPU initialization BL1 calls the `reset_handler()` function which in turn calls the CPU specific reset handler function (see the section: "CPU specific operations framework"). * MMU setup BL1 sets up EL3 memory translation by creating page tables to cover the first 4GB of physical address space. This covers all the memories and peripherals needed by BL1. * Control register setup - `SCTLR_EL3`. Instruction cache is enabled by setting the `SCTLR_EL3.I` bit. Alignment and stack alignment checking is enabled by setting the `SCTLR_EL3.A` and `SCTLR_EL3.SA` bits. Exception endianness is set to little-endian by clearing the `SCTLR_EL3.EE` bit. - `SCR_EL3`. The register width of the next lower exception level is set to AArch64 by setting the `SCR.RW` bit. - `CPTR_EL3`. Accesses to the `CPACR_EL1` register from EL1 or EL2, or the `CPTR_EL2` register from EL2 are configured to not trap to EL3 by clearing the `CPTR_EL3.TCPAC` bit. Access to the trace functionality is configured not to trap to EL3 by clearing the `CPTR_EL3.TTA` bit. Instructions that access the registers associated with Floating Point and Advanced SIMD execution are configured to not trap to EL3 by clearing the `CPTR_EL3.TFP` bit. #### Platform initialization BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests from the CCI-400 slave interface corresponding to the cluster that includes the primary CPU. BL1 also initializes UART0 (PL011 console), which enables access to the `printf` family of functions in BL1. #### BL2 image load and execution BL1 execution continues as follows: 1. BL1 determines the amount of free trusted SRAM memory available by calculating the extent of its own data section, which also resides in trusted SRAM. BL1 loads a BL2 raw binary image from platform storage, at a platform-specific base address. If the BL2 image file is not present or if there is not enough free trusted SRAM the following error message is printed: "Failed to load boot loader stage 2 (BL2) firmware." If the load is successful, BL1 updates the limits of the remaining free trusted SRAM. It also populates information about the amount of trusted SRAM used by the BL2 image. The exact load location of the image is provided as a base address in the platform header. Further description of the memory layout can be found later in this document. 2. BL1 prints the following string from the primary CPU to indicate successful execution of the BL1 stage: "Booting trusted firmware boot loader stage 1" 3. BL1 passes control to the BL2 image at Secure EL1, starting from its load address. 4. BL1 also passes information about the amount of trusted SRAM used and available for use. This information is populated at a platform-specific memory address. ### BL2 BL1 loads and passes control to BL2 at Secure-EL1. BL2 is linked against and loaded at a platform-specific base address (more information can be found later in this document). The functionality implemented by BL2 is as follows. #### Architectural initialization BL2 performs minimal architectural initialization required for subsequent stages of the ARM Trusted Firmware and normal world software. It sets up Secure EL1 memory translation by creating page tables to address the first 4GB of the physical address space in a similar way to BL1. EL1 and EL0 are given access to Floating Point & Advanced SIMD registers by clearing the `CPACR.FPEN` bits. #### Platform initialization BL2 copies the information regarding the trusted SRAM populated by BL1 using a platform-specific mechanism. It calculates the limits of DRAM (main memory) to determine whether there is enough space to load the BL3-3 image. A platform defined base address is used to specify the load address for the BL3-1 image. It also defines the extents of memory available for use by the BL3-2 image. BL2 also initializes UART0 (PL011 console), which enables access to the `printf` family of functions in BL2. Platform security is initialized to allow access to controlled components. The storage abstraction layer is initialized which is used to load further bootloader images. #### BL3-0 (System Control Processor Firmware) image load Some systems have a separate System Control Processor (SCP) for power, clock, reset and system control. BL2 loads the optional BL3-0 image from platform storage into a platform-specific region of secure memory. The subsequent handling of BL3-0 is platform specific. For example, on the Juno ARM development platform port the image is transferred into SCP memory using the SCPI protocol after being loaded in the trusted SRAM memory at address `0x04009000`. The SCP executes BL3-0 and signals to the Application Processor (AP) for BL2 execution to continue. #### BL3-1 (EL3 Runtime Firmware) image load BL2 loads the BL3-1 image from platform storage into a platform-specific address in trusted SRAM. If there is not enough memory to load the image or image is missing it leads to an assertion failure. If the BL3-1 image loads successfully, BL2 updates the amount of trusted SRAM used and available for use by BL3-1. This information is populated at a platform-specific memory address. #### BL3-2 (Secure-EL1 Payload) image load BL2 loads the optional BL3-2 image from platform storage into a platform- specific region of secure memory. The image executes in the secure world. BL2 relies on BL3-1 to pass control to the BL3-2 image, if present. Hence, BL2 populates a platform-specific area of memory with the entrypoint/load-address of the BL3-2 image. The value of the Saved Processor Status Register (`SPSR`) for entry into BL3-2 is not determined by BL2, it is initialized by the Secure-EL1 Payload Dispatcher (see later) within BL3-1, which is responsible for managing interaction with BL3-2. This information is passed to BL3-1. #### BL3-3 (Non-trusted Firmware) image load BL2 loads the BL3-3 image (e.g. UEFI or other test or boot software) from platform storage into non-secure memory as defined by the platform. BL2 relies on BL3-1 to pass control to BL3-3 once secure state initialization is complete. Hence, BL2 populates a platform-specific area of memory with the entrypoint and Saved Program Status Register (`SPSR`) of the normal world software image. The entrypoint is the load address of the BL3-3 image. The `SPSR` is determined as specified in Section 5.13 of the [PSCI PDD] [PSCI]. This information is passed to BL3-1. #### BL3-1 (EL3 Runtime Firmware) execution BL2 execution continues as follows: 1. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the BL3-1 entrypoint. The exception is handled by the SMC exception handler installed by BL1. 2. BL1 turns off the MMU and flushes the caches. It clears the `SCTLR_EL3.M/I/C` bits, flushes the data cache to the point of coherency and invalidates the TLBs. 3. BL1 passes control to BL3-1 at the specified entrypoint at EL3. ### BL3-1 The image for this stage is loaded by BL2 and BL1 passes control to BL3-1 at EL3. BL3-1 executes solely in trusted SRAM. BL3-1 is linked against and loaded at a platform-specific base address (more information can be found later in this document). The functionality implemented by BL3-1 is as follows. #### Architectural initialization Currently, BL3-1 performs a similar architectural initialization to BL1 as far as system register settings are concerned. Since BL1 code resides in ROM, architectural initialization in BL3-1 allows override of any previous initialization done by BL1. BL3-1 creates page tables to address the first 4GB of physical address space and initializes the MMU accordingly. It initializes a buffer of frequently used pointers, called per-CPU pointer cache, in memory for faster access. Currently the per-CPU pointer cache contains only the pointer to crash stack. It then replaces the exception vectors populated by BL1 with its own. BL3-1 exception vectors implement more elaborate support for handling SMCs since this is the only mechanism to access the runtime services implemented by BL3-1 (PSCI for example). BL3-1 checks each SMC for validity as specified by the [SMC calling convention PDD][SMCCC] before passing control to the required SMC handler routine. BL3-1 programs the `CNTFRQ_EL0` register with the clock frequency of the system counter, which is provided by the platform. #### Platform initialization BL3-1 performs detailed platform initialization, which enables normal world software to function correctly. It also retrieves entrypoint information for the BL3-3 image loaded by BL2 from the platform defined memory address populated by BL2. BL3-1 also initializes UART0 (PL011 console), which enables access to the `printf` family of functions in BL3-1. It enables the system level implementation of the generic timer through the memory mapped interface. * GICv2 initialization: - Enable group0 interrupts in the GIC CPU interface. - Configure group0 interrupts to be asserted as FIQs. - Disable the legacy interrupt bypass mechanism. - Configure the priority mask register to allow interrupts of all priorities to be signaled to the CPU interface. - Mark SGIs 8-15, the secure physical timer interrupt (#29) and the trusted watchdog interrupt (#56) as group0 (secure). - Target the trusted watchdog interrupt to CPU0. - Enable these group0 interrupts in the GIC distributor. - Configure all other interrupts as group1 (non-secure). - Enable signaling of group0 interrupts in the GIC distributor. * GICv3 initialization: If a GICv3 implementation is available in the platform, BL3-1 initializes the GICv3 in GICv2 emulation mode with settings as described for GICv2 above. * Power management initialization: BL3-1 implements a state machine to track CPU and cluster state. The state can be one of `OFF`, `ON_PENDING`, `SUSPEND` or `ON`. All secondary CPUs are initially in the `OFF` state. The cluster that the primary CPU belongs to is `ON`; any other cluster is `OFF`. BL3-1 initializes the data structures that implement the state machine, including the locks that protect them. BL3-1 accesses the state of a CPU or cluster immediately after reset and before the MMU is enabled in the warm boot path. It is not currently possible to use 'exclusive' based spinlocks, therefore BL3-1 uses locks based on Lamport's Bakery algorithm instead. BL3-1 allocates these locks in device memory. They are accessible irrespective of MMU state. * Runtime services initialization: The runtime service framework and its initialization is described in the "EL3 runtime services framework" section below. Details about the PSCI service are provided in the "Power State Coordination Interface" section below. * BL3-2 (Secure-EL1 Payload) image initialization If a BL3-2 image is present then there must be a matching Secure-EL1 Payload Dispatcher (SPD) service (see later for details). During initialization that service must register a function to carry out initialization of BL3-2 once the runtime services are fully initialized. BL3-1 invokes such a registered function to initialize BL3-2 before running BL3-3. Details on BL3-2 initialization and the SPD's role are described in the "Secure-EL1 Payloads and Dispatchers" section below. * BL3-3 (Non-trusted Firmware) execution BL3-1 initializes the EL2 or EL1 processor context for normal-world cold boot, ensuring that no secure state information finds its way into the non-secure execution state. BL3-1 uses the entrypoint information provided by BL2 to jump to the Non-trusted firmware image (BL3-3) at the highest available Exception Level (EL2 if available, otherwise EL1). ### Using alternative Trusted Boot Firmware in place of BL1 and BL2 Some platforms have existing implementations of Trusted Boot Firmware that would like to use ARM Trusted Firmware BL3-1 for the EL3 Runtime Firmware. To enable this firmware architecture it is important to provide a fully documented and stable interface between the Trusted Boot Firmware and BL3-1. Future changes to the BL3-1 interface will be done in a backwards compatible way, and this enables these firmware components to be independently enhanced/ updated to develop and exploit new functionality. #### Required CPU state when calling `bl31_entrypoint()` during cold boot This function must only be called by the primary CPU, if this is called by any other CPU the firmware will abort. On entry to this function the calling primary CPU must be executing in AArch64 EL3, little-endian data access, and all interrupt sources masked: PSTATE.EL = 3 PSTATE.RW = 1 PSTATE.DAIF = 0xf CTLR_EL3.EE = 0 X0 and X1 can be used to pass information from the Trusted Boot Firmware to the platform code in BL3-1: X0 : Reserved for common Trusted Firmware information X1 : Platform specific information BL3-1 zero-init sections (e.g. `.bss`) should not contain valid data on entry, these will be zero filled prior to invoking platform setup code. ##### Use of the X0 and X1 parameters The parameters are platform specific and passed from `bl31_entrypoint()` to `bl31_early_platform_setup()`. The value of these parameters is never directly used by the common BL3-1 code. The convention is that `X0` conveys information regarding the BL3-1, BL3-2 and BL3-3 images from the Trusted Boot firmware and `X1` can be used for other platform specific purpose. This convention allows platforms which use ARM Trusted Firmware's BL1 and BL2 images to transfer additional platform specific information from Secure Boot without conflicting with future evolution of the Trusted Firmware using `X0` to pass a `bl31_params` structure. BL3-1 common and SPD initialization code depends on image and entrypoint information about BL3-3 and BL3-2, which is provided via BL3-1 platform APIs. This information is required until the start of execution of BL3-3. This information can be provided in a platform defined manner, e.g. compiled into the platform code in BL3-1, or provided in a platform defined memory location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the Cold boot Initialization parameters. This data may need to be cleaned out of the CPU caches if it is provided by an earlier boot stage and then accessed by BL3-1 platform code before the caches are enabled. ARM Trusted Firmware's BL2 implementation passes a `bl31_params` structure in `X0` and the FVP port interprets this in the BL3-1 platform code. ##### MMU, Data caches & Coherency BL3-1 does not depend on the enabled state of the MMU, data caches or interconnect coherency on entry to `bl31_entrypoint()`. If these are disabled on entry, these should be enabled during `bl31_plat_arch_setup()`. ##### Data structures used in the BL3-1 cold boot interface These structures are designed to support compatibility and independent evolution of the structures and the firmware images. For example, a version of BL3-1 that can interpret the BL3-x image information from different versions of BL2, a platform that uses an extended entry_point_info structure to convey additional register information to BL3-1, or a ELF image loader that can convey more details about the firmware images. To support these scenarios the structures are versioned and sized, which enables BL3-1 to detect which information is present and respond appropriately. The `param_header` is defined to capture this information: typedef struct param_header { uint8_t type; /* type of the structure */ uint8_t version; /* version of this structure */ uint16_t size; /* size of this structure in bytes */ uint32_t attr; /* attributes: unused bits SBZ */ } param_header_t; The structures using this format are `entry_point_info`, `image_info` and `bl31_params`. The code that allocates and populates these structures must set the header fields appropriately, and the `SET_PARA_HEAD()` a macro is defined to simplify this action. #### Required CPU state for BL3-1 Warm boot initialization When requesting a CPU power-on, or suspending a running CPU, ARM Trusted Firmware provides the platform power management code with a Warm boot initialization entry-point, to be invoked by the CPU immediately after the reset handler. On entry to the Warm boot initialization function the calling CPU must be in AArch64 EL3, little-endian data access and all interrupt sources masked: PSTATE.EL = 3 PSTATE.RW = 1 PSTATE.DAIF = 0xf SCTLR_EL3.EE = 0 The PSCI implementation will initialize the processor state and ensure that the platform power management code is then invoked as required to initialize all necessary system, cluster and CPU resources. ### Using BL3-1 as the CPU reset vector On some platforms the runtime firmware (BL3-x images) for the application processors are loaded by trusted firmware running on a secure system processor on the SoC, rather than by BL1 and BL2 running on the primary application processor. For this type of SoC it is desirable for the application processor to always reset to BL3-1 which eliminates the need for BL1 and BL2. ARM Trusted Firmware provides a build-time option `RESET_TO_BL31` that includes some additional logic in the BL3-1 entrypoint to support this use case. In this configuration, the platform's Trusted Boot Firmware must ensure that BL3-1 is loaded to its runtime address, which must match the CPU's RVBAR reset vector address, before the application processor is powered on. Additionally, platform software is responsible for loading the other BL3-x images required and providing entry point information for them to BL3-1. Loading these images might be done by the Trusted Boot Firmware or by platform code in BL3-1. The ARM FVP port supports the `RESET_TO_BL31` configuration, in which case the `bl31.bin` image must be loaded to its run address in Trusted SRAM and all CPU reset vectors be changed from the default `0x0` to this run address. See the [User Guide] for details of running the FVP models in this way. This configuration requires some additions and changes in the BL3-1 functionality: #### Determination of boot path In this configuration, BL3-1 uses the same reset framework and code as the one described for BL1 above. On a warm boot a CPU is directed to the PSCI implementation via a platform defined mechanism. On a cold boot, the platform must place any secondary CPUs into a safe state while the primary CPU executes a modified BL3-1 initialization, as described below. #### Architectural initialization As the first image to execute in this configuration BL3-1 must ensure that interconnect coherency is enabled (if required) before enabling the MMU. #### Platform initialization In this configuration, when the CPU resets to BL3-1 there are no parameters that can be passed in registers by previous boot stages. Instead, the platform code in BL3-1 needs to know, or be able to determine, the location of the BL3-2 (if required) and BL3-3 images and provide this information in response to the `bl31_plat_get_next_image_ep_info()` function. As the first image to execute in this configuration BL3-1 must also ensure that any security initialisation, for example programming a TrustZone address space controller, is carried out during early platform initialisation. 3. EL3 runtime services framework ---------------------------------- Software executing in the non-secure state and in the secure state at exception levels lower than EL3 will request runtime services using the Secure Monitor Call (SMC) instruction. These requests will follow the convention described in the SMC Calling Convention PDD ([SMCCC]). The [SMCCC] assigns function identifiers to each SMC request and describes how arguments are passed and returned. The EL3 runtime services framework enables the development of services by different providers that can be easily integrated into final product firmware. The following sections describe the framework which facilitates the registration, initialization and use of runtime services in EL3 Runtime Firmware (BL3-1). The design of the runtime services depends heavily on the concepts and definitions described in the [SMCCC], in particular SMC Function IDs, Owning Entity Numbers (OEN), Fast and Standard calls, and the SMC32 and SMC64 calling conventions. Please refer to that document for more detailed explanation of these terms. The following runtime services are expected to be implemented first. They have not all been instantiated in the current implementation. 1. Standard service calls This service is for management of the entire system. The Power State Coordination Interface ([PSCI]) is the first set of standard service calls defined by ARM (see PSCI section later). NOTE: Currently this service is called PSCI since there are no other defined standard service calls. 2. Secure-EL1 Payload Dispatcher service If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then it also requires a _Secure Monitor_ at EL3 to switch the EL1 processor context between the normal world (EL1/EL2) and trusted world (Secure-EL1). The Secure Monitor will make these world switches in response to SMCs. The [SMCCC] provides for such SMCs with the Trusted OS Call and Trusted Application Call OEN ranges. The interface between the EL3 Runtime Firmware and the Secure-EL1 Payload is not defined by the [SMCCC] or any other standard. As a result, each Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime service - within ARM Trusted Firmware this service is referred to as the Secure-EL1 Payload Dispatcher (SPD). ARM Trusted Firmware provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher (TSPD). Details of SPD design and TSP/TSPD operation are described in the "Secure-EL1 Payloads and Dispatchers" section below. 3. CPU implementation service This service will provide an interface to CPU implementation specific services for a given platform e.g. access to processor errata workarounds. This service is currently unimplemented. Additional services for ARM Architecture, SiP and OEM calls can be implemented. Each implemented service handles a range of SMC function identifiers as described in the [SMCCC]. ### Registration A runtime service is registered using the `DECLARE_RT_SVC()` macro, specifying the name of the service, the range of OENs covered, the type of service and initialization and call handler functions. This macro instantiates a `const struct rt_svc_desc` for the service with these details (see `runtime_svc.h`). This structure is allocated in a special ELF section `rt_svc_descs`, enabling the framework to find all service descriptors included into BL3-1. The specific service for a SMC Function is selected based on the OEN and call type of the Function ID, and the framework uses that information in the service descriptor to identify the handler for the SMC Call. The service descriptors do not include information to identify the precise set of SMC function identifiers supported by this service implementation, the security state from which such calls are valid nor the capability to support 64-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately to these aspects of a SMC call is the responsibility of the service implementation, the framework is focused on integration of services from different providers and minimizing the time taken by the framework before the service handler is invoked. Details of the parameters, requirements and behavior of the initialization and call handling functions are provided in the following sections. ### Initialization `runtime_svc_init()` in `runtime_svc.c` initializes the runtime services framework running on the primary CPU during cold boot as part of the BL3-1 initialization. This happens prior to initializing a Trusted OS and running Normal world boot firmware that might in turn use these services. Initialization involves validating each of the declared runtime service descriptors, calling the service initialization function and populating the index used for runtime lookup of the service. The BL3-1 linker script collects all of the declared service descriptors into a single array and defines symbols that allow the framework to locate and traverse the array, and determine its size. The framework does basic validation of each descriptor to halt firmware initialization if service declaration errors are detected. The framework does not check descriptors for the following error conditions, and may behave in an unpredictable manner under such scenarios: 1. Overlapping OEN ranges 2. Multiple descriptors for the same range of OENs and `call_type` 3. Incorrect range of owning entity numbers for a given `call_type` Once validated, the service `init()` callback is invoked. This function carries out any essential EL3 initialization before servicing requests. The `init()` function is only invoked on the primary CPU during cold boot. If the service uses per-CPU data this must either be initialized for all CPUs during this call, or be done lazily when a CPU first issues an SMC call to that service. If `init()` returns anything other than `0`, this is treated as an initialization error and the service is ignored: this does not cause the firmware to halt. The OEN and call type fields present in the SMC Function ID cover a total of 128 distinct services, but in practice a single descriptor can cover a range of OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a service handler, the framework uses an array of 128 indices that map every distinct OEN/call-type combination either to one of the declared services or to indicate the service is not handled. This `rt_svc_descs_indices[]` array is populated for all of the OENs covered by a service after the service `init()` function has reported success. So a service that fails to initialize will never have it's `handle()` function invoked. The following figure shows how the `rt_svc_descs_indices[]` index maps the SMC Function ID call type and OEN onto a specific service handler in the `rt_svc_descs[]` array. ![Image 1](diagrams/rt-svc-descs-layout.png?raw=true) ### Handling an SMC When the EL3 runtime services framework receives a Secure Monitor Call, the SMC Function ID is passed in W0 from the lower exception level (as per the [SMCCC]). If the calling register width is AArch32, it is invalid to invoke an SMC Function which indicates the SMC64 calling convention: such calls are ignored and return the Unknown SMC Function Identifier result code `0xFFFFFFFF` in R0/X0. Bit[31] (fast/standard call) and bits[29:24] (owning entity number) of the SMC Function ID are combined to index into the `rt_svc_descs_indices[]` array. The resulting value might indicate a service that has no handler, in this case the framework will also report an Unknown SMC Function ID. Otherwise, the value is used as a further index into the `rt_svc_descs[]` array to locate the required service and handler. The service's `handle()` callback is provided with five of the SMC parameters directly, the others are saved into memory for retrieval (if needed) by the handler. The handler is also provided with an opaque `handle` for use with the supporting library for parameter retrieval, setting return values and context manipulation; and with `flags` indicating the security state of the caller. The framework finally sets up the execution stack for the handler, and invokes the services `handle()` function. On return from the handler the result registers are populated in X0-X3 before restoring the stack and CPU state and returning from the original SMC. 4. Power State Coordination Interface -------------------------------------- TODO: Provide design walkthrough of PSCI implementation. The complete PSCI API is not yet implemented. The following functions are currently implemented: - `PSCI_VERSION` - `CPU_OFF` - `CPU_ON` - `CPU_SUSPEND` - `AFFINITY_INFO` - `SYSTEM_OFF` - `SYSTEM_RESET` The `CPU_ON`, `CPU_OFF` and `CPU_SUSPEND` functions implement the warm boot path in ARM Trusted Firmware. `CPU_ON` and `CPU_OFF` have undergone testing on all the supported FVPs. `CPU_SUSPEND` & `AFFINITY_INFO` have undergone testing only on the AEM v8 Base FVP. Support for `AFFINITY_INFO` is still experimental. Support for `CPU_SUSPEND` is stable for entry into power down states. Standby states are currently not supported. `PSCI_VERSION` is present but completely untested in this version of the software. The following unsupported functions return with a error code as documented in the [Power State Coordination Interface PDD] [PSCI]. - `MIGRATE` : -1 (NOT_SUPPORTED) - `MIGRATE_INFO_TYPE` : 2 (Trusted OS is either not present or does not require migration) - `MIGRATE_INFO_UP_CPU` : 0 (Return value is UNDEFINED) 5. Secure-EL1 Payloads and Dispatchers --------------------------------------- On a production system that includes a Trusted OS running in Secure-EL1/EL0, the Trusted OS is coupled with a companion runtime service in the BL3-1 firmware. This service is responsible for the initialisation of the Trusted OS and all communications with it. The Trusted OS is the BL3-2 stage of the boot flow in ARM Trusted Firmware. The firmware will attempt to locate, load and execute a BL3-2 image. ARM Trusted Firmware uses a more general term for the BL3-2 software that runs at Secure-EL1 - the _Secure-EL1 Payload_ - as it is not always a Trusted OS. The ARM Trusted Firmware provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a production system using the Runtime Services Framework. On such a system, the Test BL3-2 image and service are replaced by the Trusted OS and its dispatcher service. The TSP runs in Secure-EL1. It is designed to demonstrate synchronous communication with the normal-world software running in EL1/EL2. Communication is initiated by the normal-world software * either directly through a Fast SMC (as defined in the [SMCCC]) * or indirectly through a [PSCI] SMC. The [PSCI] implementation in turn informs the TSPD about the requested power management operation. This allows the TSP to prepare for or respond to the power state change The TSPD service is responsible for. * Initializing the TSP * Routing requests and responses between the secure and the non-secure states during the two types of communications just described ### Initializing a BL3-2 Image The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing the BL3-2 image. It needs access to the information passed by BL2 to BL3-1 to do so. This is provided by: entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); which returns a reference to the `entry_point_info` structure corresponding to the image which will be run in the specified security state. The SPD uses this API to get entry point information for the SECURE image, BL3-2. In the absence of a BL3-2 image, BL3-1 passes control to the normal world bootloader image (BL3-3). When the BL3-2 image is present, it is typical that the SPD wants control to be passed to BL3-2 first and then later to BL3-3. To do this the SPD has to register a BL3-2 initialization function during initialization of the SPD service. The BL3-2 initialization function has this prototype: int32_t init(); and is registered using the `bl31_register_bl32_init()` function. Trusted Firmware supports two approaches for the SPD to pass control to BL3-2 before returning through EL3 and running the non-trusted firmware (BL3-3): 1. In the BL3-2 setup function, use `bl31_set_next_image_type()` to request that the exit from `bl31_main()` is to the BL3-2 entrypoint in Secure-EL1. BL3-1 will exit to BL3-2 using the asynchronous method by calling bl31_prepare_next_image_entry() and el3_exit(). When the BL3-2 has completed initialization at Secure-EL1, it returns to BL3-1 by issuing an SMC, using a Function ID allocated to the SPD. On receipt of this SMC, the SPD service handler should switch the CPU context from trusted to normal world and use the `bl31_set_next_image_type()` and `bl31_prepare_next_image_entry()` functions to set up the initial return to the normal world firmware BL3-3. On return from the handler the framework will exit to EL2 and run BL3-3. 2. The BL3-2 setup function registers a initialization function using `bl31_register_bl32_init()` which provides a SPD-defined mechanism to invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL3-2 entrypoint. NOTE: The Test SPD service included with the Trusted Firmware provides one implementation of such a mechanism. On completion BL3-2 returns control to BL3-1 via a SMC, and on receipt the SPD service handler invokes the synchronous call return mechanism to return to the BL3-2 initialization function. On return from this function, `bl31_main()` will set up the return to the normal world firmware BL3-3 and continue the boot process in the normal world. 6. Crash Reporting in BL3-1 ---------------------------- The BL3-1 implements a scheme for reporting the processor state when an unhandled exception is encountered. The reporting mechanism attempts to preserve all the register contents and report it via the default serial output. The general purpose registers, EL3, Secure EL1 and some EL2 state registers are reported. A dedicated per-CPU crash stack is maintained by BL3-1 and this is retrieved via the per-CPU pointer cache. The implementation attempts to minimise the memory required for this feature. The file `crash_reporting.S` contains the implementation for crash reporting. The sample crash output is shown below. x0 :0x000000004F00007C x1 :0x0000000007FFFFFF x2 :0x0000000004014D50 x3 :0x0000000000000000 x4 :0x0000000088007998 x5 :0x00000000001343AC x6 :0x0000000000000016 x7 :0x00000000000B8A38 x8 :0x00000000001343AC x9 :0x00000000000101A8 x10 :0x0000000000000002 x11 :0x000000000000011C x12 :0x00000000FEFDC644 x13 :0x00000000FED93FFC x14 :0x0000000000247950 x15 :0x00000000000007A2 x16 :0x00000000000007A4 x17 :0x0000000000247950 x18 :0x0000000000000000 x19 :0x00000000FFFFFFFF x20 :0x0000000004014D50 x21 :0x000000000400A38C x22 :0x0000000000247950 x23 :0x0000000000000010 x24 :0x0000000000000024 x25 :0x00000000FEFDC868 x26 :0x00000000FEFDC86A x27 :0x00000000019EDEDC x28 :0x000000000A7CFDAA x29 :0x0000000004010780 x30 :0x000000000400F004 scr_el3 :0x0000000000000D3D sctlr_el3 :0x0000000000C8181F cptr_el3 :0x0000000000000000 tcr_el3 :0x0000000080803520 daif :0x00000000000003C0 mair_el3 :0x00000000000004FF spsr_el3 :0x00000000800003CC elr_el3 :0x000000000400C0CC ttbr0_el3 :0x00000000040172A0 esr_el3 :0x0000000096000210 sp_el3 :0x0000000004014D50 far_el3 :0x000000004F00007C spsr_el1 :0x0000000000000000 elr_el1 :0x0000000000000000 spsr_abt :0x0000000000000000 spsr_und :0x0000000000000000 spsr_irq :0x0000000000000000 spsr_fiq :0x0000000000000000 sctlr_el1 :0x0000000030C81807 actlr_el1 :0x0000000000000000 cpacr_el1 :0x0000000000300000 csselr_el1 :0x0000000000000002 sp_el1 :0x0000000004028800 esr_el1 :0x0000000000000000 ttbr0_el1 :0x000000000402C200 ttbr1_el1 :0x0000000000000000 mair_el1 :0x00000000000004FF amair_el1 :0x0000000000000000 tcr_el1 :0x0000000000003520 tpidr_el1 :0x0000000000000000 tpidr_el0 :0x0000000000000000 tpidrro_el0 :0x0000000000000000 dacr32_el2 :0x0000000000000000 ifsr32_el2 :0x0000000000000000 par_el1 :0x0000000000000000 far_el1 :0x0000000000000000 afsr0_el1 :0x0000000000000000 afsr1_el1 :0x0000000000000000 contextidr_el1 :0x0000000000000000 vbar_el1 :0x0000000004027000 cntp_ctl_el0 :0x0000000000000000 cntp_cval_el0 :0x0000000000000000 cntv_ctl_el0 :0x0000000000000000 cntv_cval_el0 :0x0000000000000000 cntkctl_el1 :0x0000000000000000 fpexc32_el2 :0x0000000004000700 sp_el0 :0x0000000004010780 7. CPU specific operations framework ----------------------------- Certain aspects of the ARMv8 architecture are implementation defined, that is, certain behaviours are not architecturally defined, but must be defined and documented by individual processor implementations. The ARM Trusted Firmware implements a framework which categorises the common implementation defined behaviours and allows a processor to export its implementation of that behaviour. The categories are: 1. Processor specific reset sequence. 2. Processor specific power down sequences. 3. Processor specific register dumping as a part of crash reporting. Each of the above categories fulfils a different requirement. 1. allows any processor specific initialization before the caches and MMU are turned on, like implementation of errata workarounds, entry into the intra-cluster coherency domain etc. 2. allows each processor to implement the power down sequence mandated in its Technical Reference Manual (TRM). 3. allows a processor to provide additional information to the developer in the event of a crash, for example Cortex-A53 has registers which can expose the data cache contents. Please note that only 2. is mandated by the TRM. The CPU specific operations framework scales to accommodate a large number of different CPUs during power down and reset handling. The platform can specify the CPU errata workarounds to be applied for each CPU type during reset handling by defining CPU errata compile time macros. Details on these macros can be found in the [cpu-errata-workarounds.md][ERRW] file. The CPU specific operations framework depends on the `cpu_ops` structure which needs to be exported for each type of CPU in the platform. It is defined in `include/lib/cpus/aarch64/cpu_macros.S` and has the following fields : `midr`, `reset_func()`, `core_pwr_dwn()`, `cluster_pwr_dwn()` and `cpu_reg_dump()`. The CPU specific files in `lib/cpus` export a `cpu_ops` data structure with suitable handlers for that CPU. For example, `lib/cpus/cortex_a53.S` exports the `cpu_ops` for Cortex-A53 CPU. According to the platform configuration, these CPU specific files must must be included in the build by the platform makefile. The generic CPU specific operations framework code exists in `lib/cpus/aarch64/cpu_helpers.S`. ### CPU specific Reset Handling After a reset, the state of the CPU when it calls generic reset handler is: MMU turned off, both instruction and data caches turned off and not part of any coherency domain. The BL entrypoint code first invokes the `plat_reset_handler()` to allow the platform to perform any system initialization required and any system errata wrokarounds that needs to be applied. The `get_cpu_ops_ptr()` reads the current CPU midr, finds the matching `cpu_ops` entry in the `cpu_ops` array and returns it. Note that only the part number and implementator fields in midr are used to find the matching `cpu_ops` entry. The `reset_func()` in the returned `cpu_ops` is then invoked which executes the required reset handling for that CPU and also any errata workarounds enabled by the platform. ### CPU specific power down sequence During the BL3-1 initialization sequence, the pointer to the matching `cpu_ops` entry is stored in per-CPU data by `init_cpu_ops()` so that it can be quickly retrieved during power down sequences. The PSCI service, upon receiving a power down request, determines the highest affinity level at which to execute power down sequence for a particular CPU and invokes the corresponding 'prepare' power down handler in the CPU specific operations framework. For example, when a CPU executes a power down for affinity level 0, the `prepare_core_pwr_dwn()` retrieves the `cpu_ops` pointer from the per-CPU data and the corresponding `core_pwr_dwn()` is invoked. Similarly when a CPU executes power down at affinity level 1, the `prepare_cluster_pwr_dwn()` retrieves the `cpu_ops` pointer and the corresponding `cluster_pwr_dwn()` is invoked. At runtime the platform hooks for power down are invoked by the PSCI service to perform platform specific operations during a power down sequence, for example turning off CCI coherency during a cluster power down. ### CPU specific register reporting during crash If the crash reporting is enabled in BL3-1, when a crash occurs, the crash reporting framework calls `do_cpu_reg_dump` which retrieves the matching `cpu_ops` using `get_cpu_ops_ptr()` function. The `cpu_reg_dump()` in `cpu_ops` is invoked, which then returns the CPU specific register values to be reported and a pointer to the ASCII list of register names in a format expected by the crash reporting framework. 8. Memory layout of BL images ----------------------------- Each bootloader image can be divided in 2 parts: * the static contents of the image. These are data actually stored in the binary on the disk. In the ELF terminology, they are called `PROGBITS` sections; * the run-time contents of the image. These are data that don't occupy any space in the binary on the disk. The ELF binary just contains some metadata indicating where these data will be stored at run-time and the corresponding sections need to be allocated and initialized at run-time. In the ELF terminology, they are called `NOBITS` sections. All PROGBITS sections are grouped together at the beginning of the image, followed by all NOBITS sections. This is true for all Trusted Firmware images and it is governed by the linker scripts. This ensures that the raw binary images are as small as possible. If a NOBITS section would sneak in between PROGBITS sections then the resulting binary file would contain a bunch of zero bytes at the location of this NOBITS section, making the image unnecessarily bigger. Smaller images allow faster loading from the FIP to the main memory. ### Linker scripts and symbols Each bootloader stage image layout is described by its own linker script. The linker scripts export some symbols into the program symbol table. Their values correspond to particular addresses. The trusted firmware code can refer to these symbols to figure out the image memory layout. Linker symbols follow the following naming convention in the trusted firmware. * `__

_START__` Start address of a given section named `
`. * `__
_END__` End address of a given section named `
`. If there is an alignment constraint on the section's end address then `__
_END__` corresponds to the end address of the section's actual contents, rounded up to the right boundary. Refer to the value of `__
_UNALIGNED_END__` to know the actual end address of the section's contents. * `__
_UNALIGNED_END__` End address of a given section named `
` without any padding or rounding up due to some alignment constraint. * `__
_SIZE__` Size (in bytes) of a given section named `
`. If there is an alignment constraint on the section's end address then `__
_SIZE__` corresponds to the size of the section's actual contents, rounded up to the right boundary. In other words, `__
_SIZE__ = __
_END__ - _
_START__`. Refer to the value of `__
_UNALIGNED_SIZE__` to know the actual size of the section's contents. * `__
_UNALIGNED_SIZE__` Size (in bytes) of a given section named `
` without any padding or rounding up due to some alignment constraint. In other words, `__
_UNALIGNED_SIZE__ = __
_UNALIGNED_END__ - __
_START__`. Some of the linker symbols are mandatory as the trusted firmware code relies on them to be defined. They are listed in the following subsections. Some of them must be provided for each bootloader stage and some are specific to a given bootloader stage. The linker scripts define some extra, optional symbols. They are not actually used by any code but they help in understanding the bootloader images' memory layout as they are easy to spot in the link map files. #### Common linker symbols Early setup code needs to know the extents of the BSS section to zero-initialise it before executing any C code. The following linker symbols are defined for this purpose: * `__BSS_START__` This address must be aligned on a 16-byte boundary. * `__BSS_SIZE__` Similarly, the coherent memory section must be zero-initialised. Also, the MMU setup code needs to know the extents of this section to set the right memory attributes for it. The following linker symbols are defined for this purpose: * `__COHERENT_RAM_START__` This address must be aligned on a page-size boundary. * `__COHERENT_RAM_END__` This address must be aligned on a page-size boundary. * `__COHERENT_RAM_UNALIGNED_SIZE__` #### BL1's linker symbols BL1's early setup code needs to know the extents of the .data section to relocate it from ROM to RAM before executing any C code. The following linker symbols are defined for this purpose: * `__DATA_ROM_START__` This address must be aligned on a 16-byte boundary. * `__DATA_RAM_START__` This address must be aligned on a 16-byte boundary. * `__DATA_SIZE__` BL1's platform setup code needs to know the extents of its read-write data region to figure out its memory layout. The following linker symbols are defined for this purpose: * `__BL1_RAM_START__` This is the start address of BL1 RW data. * `__BL1_RAM_END__` This is the end address of BL1 RW data. #### BL2's, BL3-1's and TSP's linker symbols BL2, BL3-1 and TSP need to know the extents of their read-only section to set the right memory attributes for this memory region in their MMU setup code. The following linker symbols are defined for this purpose: * `__RO_START__` * `__RO_END__` ### How to choose the right base addresses for each bootloader stage image There is currently no support for dynamic image loading in the Trusted Firmware. This means that all bootloader images need to be linked against their ultimate runtime locations and the base addresses of each image must be chosen carefully such that images don't overlap each other in an undesired way. As the code grows, the base addresses might need adjustments to cope with the new memory layout. The memory layout is completely specific to the platform and so there is no general recipe for choosing the right base addresses for each bootloader image. However, there are tools to aid in understanding the memory layout. These are the link map files: `build///bl/bl.map`, with `` being the stage bootloader. They provide a detailed view of the memory usage of each image. Among other useful information, they provide the end address of each image. * `bl1.map` link map file provides `__BL1_RAM_END__` address. * `bl2.map` link map file provides `__BL2_END__` address. * `bl31.map` link map file provides `__BL31_END__` address. * `bl32.map` link map file provides `__BL32_END__` address. For each bootloader image, the platform code must provide its start address as well as a limit address that it must not overstep. The latter is used in the linker scripts to check that the image doesn't grow past that address. If that happens, the linker will issue a message similar to the following: aarch64-none-elf-ld: BLx has exceeded its limit. Additionally, if the platform memory layout implies some image overlaying like on FVP, BL3-1 and TSP need to know the limit address that their PROGBITS sections must not overstep. The platform code must provide those. #### Memory layout on ARM FVPs The following list describes the memory layout on the FVP: * A 4KB page of shared memory is used to store the entrypoint mailboxes and the parameters passed between bootloaders. The shared memory can be allocated either at the top of Trusted SRAM or at the base of Trusted DRAM at build time. When allocated in Trusted SRAM, the amount of Trusted SRAM available to load the bootloader images will be reduced by the size of the shared memory. * BL1 is originally sitting in the Trusted ROM at address `0x0`. Its read-write data are relocated at the top of the Trusted SRAM at runtime. If the shared memory is allocated in Trusted SRAM, the BL1 read-write data is relocated just below the shared memory. * BL3-1 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will overwrite BL1 R/W data. * BL2 is loaded below BL3-1. * The TSP is loaded as the BL3-2 image at the base of either the Trusted SRAM or Trusted DRAM. When loaded into Trusted SRAM, its NOBITS sections are allowed to overlay BL2. When loaded into Trusted DRAM, an offset corresponding to the size of the shared memory is applied to avoid overlap. This memory layout is designed to give the BL3-2 image as much memory as possible when it is loaded into Trusted SRAM. Depending on the location of the shared memory page and the TSP, it will result in different memory maps, illustrated by the following diagrams. **Shared data & TSP in Trusted SRAM (default option):** Trusted SRAM 0x04040000 +----------+ | Shared | 0x0403F000 +----------+ loaded by BL2 ------------------ | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | |----------| <<<<<<<<<<<<< |----------------| | | <<<<<<<<<<<<< | BL3-1 PROGBITS | |----------| ------------------ | BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS | |----------| <<<<<<<<<<<<< |----------------| | | <<<<<<<<<<<<< | BL3-2 PROGBITS | 0x04000000 +----------+ ------------------ Trusted ROM 0x04000000 +----------+ | BL1 (ro) | 0x00000000 +----------+ **Shared data & TSP in Trusted DRAM:** Trusted DRAM 0x08000000 +----------+ | | | BL3-2 | | | 0x06001000 |----------| | Shared | 0x06000000 +----------+ Trusted SRAM 0x04040000 +----------+ loaded by BL2 ------------------ | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | |----------| <<<<<<<<<<<<< |----------------| | | <<<<<<<<<<<<< | BL3-1 PROGBITS | |----------| ------------------ | BL2 | |----------| | | 0x04000000 +----------+ Trusted ROM 0x04000000 +----------+ | BL1 (ro) | 0x00000000 +----------+ **Shared data in Trusted DRAM, TSP in Trusted SRAM:** Trusted DRAM 0x08000000 +----------+ | | | | | | 0x06001000 |----------| | Shared | 0x06000000 +----------+ Trusted SRAM 0x04040000 +----------+ loaded by BL2 ------------------ | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | |----------| <<<<<<<<<<<<< |----------------| | | <<<<<<<<<<<<< | BL3-1 PROGBITS | |----------| ------------------ | BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS | |----------| <<<<<<<<<<<<< |----------------| | | <<<<<<<<<<<<< | BL3-2 PROGBITS | 0x04000000 +----------+ ------------------ Trusted ROM 0x04000000 +----------+ | BL1 (ro) | 0x00000000 +----------+ Loading the TSP image in Trusted DRAM doesn't change the memory layout of the other boot loader images in Trusted SRAM. #### Memory layout on Juno ARM development platform Flash0 0x0C000000 +----------+ : : 0x0BED0000 |----------| | BL1 (ro) | 0x0BEC0000 |----------| : : | Bypass | 0x08000000 +----------+ Trusted SRAM 0x04040000 +----------+ | BL2 | BL3-1 is loaded 0x04033000 |----------| after BL3-0 has | BL3-2 | been sent to SCP 0x04023000 |----------| ------------------ | BL3-0 | <<<<<<<<<<<<< | BL3-1 | 0x04009000 |----------| ------------------ | BL1 (rw) | 0x04001000 |----------| | MHU | 0x04000000 +----------+ The Message Handling Unit (MHU) page contains the entrypoint mailboxes and a shared memory area. This shared memory is used as a communication channel between the AP and the SCP. BL1 code starts at `0x0BEC0000`. The BL1 data section is copied to trusted SRAM at `0x04001000`, right after the MHU page. Entrypoint mailboxes are stored in the first 128 bytes of the MHU page. 9. Firmware Image Package (FIP) --------------------------------- Using a Firmware Image Package (FIP) allows for packing bootloader images (and potentially other payloads) into a single archive that can be loaded by the ARM Trusted Firmware from non-volatile platform storage. A driver to load images from a FIP has been added to the storage layer and allows a package to be read from supported platform storage. A tool to create Firmware Image Packages is also provided and described below. ### Firmware Image Package layout The FIP layout consists of a table of contents (ToC) followed by payload data. The ToC itself has a header followed by one or more table entries. The ToC is terminated by an end marker entry. All ToC entries describe some payload data that has been appended to the end of the binary package. With the information provided in the ToC entry the corresponding payload data can be retrieved. ------------------ | ToC Header | |----------------| | ToC Entry 0 | |----------------| | ToC Entry 1 | |----------------| | ToC End Marker | |----------------| | | | Data 0 | | | |----------------| | | | Data 1 | | | ------------------ The ToC header and entry formats are described in the header file `include/firmware_image_package.h`. This file is used by both the tool and the ARM Trusted firmware. The ToC header has the following fields: `name`: The name of the ToC. This is currently used to validate the header. `serial_number`: A non-zero number provided by the creation tool `flags`: Flags associated with this data. None are yet defined. A ToC entry has the following fields: `uuid`: All files are referred to by a pre-defined Universally Unique IDentifier [UUID] . The UUIDs are defined in `include/firmware_image_package`. The platform translates the requested image name into the corresponding UUID when accessing the package. `offset_address`: The offset address at which the corresponding payload data can be found. The offset is calculated from the ToC base address. `size`: The size of the corresponding payload data in bytes. `flags`: Flags associated with this entry. Non are yet defined. ### Firmware Image Package creation tool The FIP creation tool can be used to pack specified images into a binary package that can be loaded by the ARM Trusted Firmware from platform storage. The tool currently only supports packing bootloader images. Additional image definitions can be added to the tool as required. The tool can be found in `tools/fip_create`. ### Loading from a Firmware Image Package (FIP) The Firmware Image Package (FIP) driver can load images from a binary package on non-volatile platform storage. For the FVPs this is currently NOR FLASH. Bootloader images are loaded according to the platform policy as specified in `plat//plat_io_storage.c`. For the FVPs this means the platform will attempt to load images from a Firmware Image Package located at the start of NOR FLASH0. Currently the FVP's policy only allows loading of a known set of images. The platform policy can be modified to allow additional images. 10. Code Structure ------------------- Trusted Firmware code is logically divided between the three boot loader stages mentioned in the previous sections. The code is also divided into the following categories (present as directories in the source code): * **Architecture specific.** This could be AArch32 or AArch64. * **Platform specific.** Choice of architecture specific code depends upon the platform. * **Common code.** This is platform and architecture agnostic code. * **Library code.** This code comprises of functionality commonly used by all other code. * **Stage specific.** Code specific to a boot stage. * **Drivers.** * **Services.** EL3 runtime services, e.g. PSCI or SPD. Specific SPD services reside in the `services/spd` directory (e.g. `services/spd/tspd`). Each boot loader stage uses code from one or more of the above mentioned categories. Based upon the above, the code layout looks like this: Directory Used by BL1? Used by BL2? Used by BL3-1? bl1 Yes No No bl2 No Yes No bl31 No No Yes arch Yes Yes Yes plat Yes Yes Yes drivers Yes No Yes common Yes Yes Yes lib Yes Yes Yes services No No Yes The build system provides a non configurable build option IMAGE_BLx for each boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be defined by the build system. This enables the Trusted Firmware to compile certain code only for specific boot loader stages All assembler files have the `.S` extension. The linker source files for each boot stage have the extension `.ld.S`. These are processed by GCC to create the linker scripts which have the extension `.ld`. FDTs provide a description of the hardware platform and are used by the Linux kernel at boot time. These can be found in the `fdts` directory. 11. References --------------- 1. Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available under NDA through your ARM account representative. 2. [Power State Coordination Interface PDD (ARM DEN 0022B.b)][PSCI]. 3. [SMC Calling Convention PDD (ARM DEN 0028A)][SMCCC]. 4. [ARM Trusted Firmware Interrupt Management Design guide][INTRG]. - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._ [PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022b/index.html "Power State Coordination Interface PDD (ARM DEN 0022B.b)" [SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" [UUID]: https://tools.ietf.org/rfc/rfc4122.txt "A Universally Unique IDentifier (UUID) URN Namespace" [User Guide]: ./user-guide.md [Porting Guide]: ./porting-guide.md [INTRG]: ./interrupt-framework-design.md [ERRW]: ./cpu-errata-workarounds.md arm-trusted-firmware-1.0-aw-6/docs/interrupt-framework-design.md000066400000000000000000001226421322600646200247630ustar00rootroot00000000000000ARM Trusted Firmware Interrupt Management Design guide ====================================================== Contents : 1. Introduction * Assumptions * Concepts - Interrupt Types - Routing Model - Valid Routing Models + Secure-EL1 Interrupts + Non-secure Interrupts - Mapping of Interrupt Type to Signal 2. Interrupt Management * Software Components * Interrupt Registration - EL3 Runtime Firmware - Secure Payload Dispatcher + Test Secure Payload Dispatcher behavior - Secure Payload + Secure Payload IHF design w.r.t Secure-EL1 interrupts + Secure Payload IHF design w.r.t Non-secure interrupts + Test Secure Payload behavior * Interrupt Handling - EL3 Runtime Firmware - Secure Payload Dispatcher + Interrupt Entry + Interrupt Exit + Test Secure Payload Dispatcher behavior - Secure Payload + Test Secure Payload behavior 1. Introduction ---------------- This document describes the design of the Interrupt management framework in ARM Trusted Firmware. This section briefly describes the requirements from this framework. It also briefly explains some concepts and assumptions. They will help in understanding the implementation of the framework explained in subsequent sections. This framework is responsible for managing interrupts routed to EL3. It also allows EL3 software to configure the interrupt routing behavior. Its main objective is to implement the following two requirements. 1. It should be possible to route interrupts meant to be handled by secure software (Secure interrupts) to EL3, when execution is in non-secure state (normal world). The framework should then take care of handing control of the interrupt to either software in EL3 or Secure-EL1 depending upon the software configuration and the GIC implementation. This requirement ensures that secure interrupts are under the control of the secure software with respect to their delivery and handling without the possibility of intervention from non-secure software. 2. It should be possible to route interrupts meant to be handled by non-secure software (Non-secure interrupts) to the last executed exception level in the normal world when the execution is in secure world at exception levels lower than EL3. This could be done with or without the knowledge of software executing in Secure-EL1/Secure-EL0. The choice of approach should be governed by the secure software. This requirement ensures that non-secure software is able to execute in tandem with the secure software without overriding it. ### 1.1 Assumptions The framework makes the following assumptions to simplify its implementation. 1. All secure interrupts are handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they cannot be handled in EL3. It will be possible to extend the framework to handle secure interrupts in EL3 in the future. 2. Interrupt exceptions (`PSTATE.I` and `F` bits) are masked during execution in EL3. ### 1.2 Concepts #### 1.2.1 Interrupt types The framework categorises an interrupt to be one of the following depending upon the exception level(s) it is handled in. 1. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1 depending upon the security state of the current execution context. It is always handled in Secure-EL1. 2. Non-secure interrupt. This type of interrupt can be routed to EL3, Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the current execution context. It is always handled in either Non-secure EL1 or EL2. 3. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1 depending upon the security state of the current execution context. It is always handled in EL3. In the current implementation of the framework, all secure interrupts are treated as Secure EL1 interrupts. It will be possible for EL3 software to configure a secure interrupt as an EL3 interrupt in future implementations. The following constants define the various interrupt types in the framework implementation. #define INTR_TYPE_S_EL1 0 #define INTR_TYPE_EL3 1 #define INTR_TYPE_NS 2 #### 1.2.2 Routing model A type of interrupt can be either generated as an FIQ or an IRQ. The target exception level of an interrupt type is configured through the FIQ and IRQ bits in the Secure Configuration Register at EL3 (`SCR_EL3.FIQ` and `SCR_EL3.IRQ` bits). When `SCR_EL3.FIQ`=1, FIQs are routed to EL3. Otherwise they are routed to the First Exception Level (FEL) capable of handling interrupts. When `SCR_EL3.IRQ`=1, IRQs are routed to EL3. Otherwise they are routed to the FEL. This register is configured independently by EL3 software for each security state prior to entry into a lower exception level in that security state. A routing model for a type of interrupt (generated as FIQ or IRQ) is defined as its target exception level for each security state. It is represented by a single bit for each security state. A value of `0` means that the interrupt should be routed to the FEL. A value of `1` means that the interrupt should be routed to EL3. A routing model is applicable only when execution is not in EL3. The default routing model for an interrupt type is to route it to the FEL in either security state. #### 1.2.3 Valid routing models The framework considers certain routing models for each type of interrupt to be incorrect as they conflict with the requirements mentioned in Section 1. The following sub-sections describe all the possible routing models and specify which ones are valid or invalid. Only the Secure-EL1 and Non-secure interrupt types are considered as EL3 interrupts are currently unsupported (See 1.1). The terminology used in the following sub-sections is explained below. 1. __CSS__. Current Security State. `0` when secure and `1` when non-secure 2. __TEL3__. Target Exception Level 3. `0` when targeted to the FEL. `1` when targeted to EL3. ##### 1.2.3.1 Secure-EL1 interrupts 1. __CSS=0, TEL3=0__. Interrupt is routed to the FEL when execution is in secure state. This is a valid routing model as secure software is in control of handling secure interrupts. 2. __CSS=0, TEL3=1__. Interrupt is routed to EL3 when execution is in secure state. This is a valid routing model as secure software in EL3 can handover the interrupt to Secure-EL1 for handling. 3. __CSS=1, TEL3=0__. Interrupt is routed to the FEL when execution is in non-secure state. This is an invalid routing model as a secure interrupt is not visible to the secure software which violates the motivation behind the ARM Security Extensions. 4. __CSS=1, TEL3=1__. Interrupt is routed to EL3 when execution is in non-secure state. This is a valid routing model as secure software in EL3 can handover the interrupt to Secure-EL1 for handling. ##### 1.2.3.2 Non-secure interrupts 1. __CSS=0, TEL3=0__. Interrupt is routed to the FEL when execution is in secure state. This allows the secure software to trap non-secure interrupts, perform its bookeeping and hand the interrupt to the non-secure software through EL3. This is a valid routing model as secure software is in control of how its execution is pre-empted by non-secure interrupts. 2. __CSS=0, TEL3=1__. Interrupt is routed to EL3 when execution is in secure state. This is a valid routing model as secure software in EL3 can save the state of software in Secure-EL1/Secure-EL0 before handing the interrupt to non-secure software. This model requires additional coordination between Secure-EL1 and EL3 software to ensure that the former's state is correctly saved by the latter. 3. __CSS=1, TEL3=0__. Interrupt is routed to FEL when execution is in non-secure state. This is an valid routing model as a non-secure interrupt is handled by non-secure software. 4. __CSS=1, TEL3=1__. Interrupt is routed to EL3 when execution is in non-secure state. This is an invalid routing model as there is no valid reason to route the interrupt to EL3 software and then hand it back to non-secure software for handling. #### 1.2.4 Mapping of interrupt type to signal The framework is meant to work with any interrupt controller implemented by a platform. A interrupt controller could generate a type of interrupt as either an FIQ or IRQ signal to the CPU depending upon the current security state.The mapping between the type and signal is known only to the platform. The framework uses this information to determine whether the IRQ or the FIQ bit should be programmed in `SCR_EL3` while applying the routing model for a type of interrupt. The platform provides this information through the `plat_interrupt_type_to_line()` API (described in the [Porting Guide]). For example, on the FVP port when the platform uses an ARM GICv2 interrupt controller, Secure-EL1 interrupts are signalled through the FIQ signal while Non-secure interrupts are signalled through the IRQ signal. This applies when execution is in either security state. 2. Interrupt management ----------------------- The following sections describe how interrupts are managed by the interrupt handling framework. This entails: 1. Providing an interface to allow registration of a handler and specification of the routing model for a type of interrupt. 2. Implementing support to hand control of an interrupt type to its registered handler when the interrupt is generated. Both aspects of interrupt management involve various components in the secure software stack spanning from EL3 to Secure-EL1. These components are described in the section 2.1. The framework stores information associated with each type of interrupt in the following data structure. ``` typedef struct intr_type_desc { interrupt_type_handler_t handler; uint32_t flags; uint32_t scr_el3[2]; } intr_type_desc_t; ``` The `flags` field stores the routing model for the interrupt type in bits[1:0]. Bit[0] stores the routing model when execution is in the secure state. Bit[1] stores the routing model when execution is in the non-secure state. As mentioned in Section 1.2.2, a value of `0` implies that the interrupt should be targeted to the FEL. A value of `1` implies that it should be targeted to EL3. The remaining bits are reserved and SBZ. The helper macro `set_interrupt_rm_flag()` should be used to set the bits in the `flags` parameter. The `scr_el3[2]` field also stores the routing model but as a mapping of the model in the `flags` field to the corresponding bit in the `SCR_EL3` for each security state. The framework also depends upon the platform port to configure the interrupt controller to distinguish between secure and non-secure interrupts. The platform is expected to be aware of the secure devices present in the system and their associated interrupt numbers. It should configure the interrupt controller to enable the secure interrupts, ensure that their priority is always higher than the non-secure interrupts and target them to the primary CPU. It should also export the interface described in the [Porting Guide] to enable handling of interrupts. In the remainder of this document, for the sake of simplicity it is assumed that the FIQ signal is used to generate Secure-EL1 interrupts and the IRQ signal is used to generate non-secure interrupts in either security state. ### 2.1 Software components Roles and responsibilities for interrupt management are sub-divided between the following components of software running in EL3 and Secure-EL1. Each component is briefly described below. 1. EL3 Runtime Firmware. This component is common to all ports of the ARM Trusted Firmware. 2. Secure Payload Dispatcher (SPD) service. This service interfaces with the Secure Payload (SP) software which runs in exception levels lower than EL3 i.e. Secure-EL1/Secure-EL0. It is responsible for switching execution between software running in secure and non-secure states at exception levels lower than EL3. A switch is triggered by a Secure Monitor Call from either state. It uses the APIs exported by the Context management library to implement this functionality. Switching execution between the two security states is a requirement for interrupt management as well. This results in a significant dependency on the SPD service. ARM Trusted firmware implements an example Test Secure Payload Dispatcher (TSPD) service. An SPD service plugs into the EL3 runtime firmware and could be common to some ports of the ARM Trusted Firmware. 3. Secure Payload (SP). On a production system, the Secure Payload corresponds to a Secure OS which runs in Secure-EL1/Secure-EL0. It interfaces with the SPD service to manage communication with non-secure software. ARM Trusted Firmware implements an example secure payload called Test Secure Payload (TSP) which runs only in Secure-EL1. A Secure payload implementation could be common to some ports of the ARM Trusted Firmware just like the SPD service. ### 2.2 Interrupt registration This section describes in detail the role of each software component (see 2.1) during the registration of a handler for an interrupt type. #### 2.2.1 EL3 runtime firmware This component declares the following prototype for a handler of an interrupt type. typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, uint32_t flags, void *handle, void *cookie); The value of the `id` parameter depends upon the definition of the `IMF_READ_INTERRUPT_ID` build time flag. When the flag is defined, `id` contains the number of the highest priority pending interrupt of the type that this handler was registered for. When the flag is not defined `id` contains `INTR_ID_UNAVAILABLE`. The `flags` parameter contains miscellaneous information as follows. 1. Security state, bit[0]. This bit indicates the security state of the lower exception level when the interrupt was generated. A value of `1` means that it was in the non-secure state. A value of `0` indicates that it was in the secure state. This bit can be used by the handler to ensure that interrupt was generated and routed as per the routing model specified during registration. 2. Reserved, bits[31:1]. The remaining bits are reserved for future use. The `handle` parameter points to the `cpu_context` structure of the current CPU for the security state specified in the `flags` parameter. Once the handler routine completes, execution will return to either the secure or non-secure state. The handler routine should return a pointer to `cpu_context` structure of the current CPU for the the target security state. It should treat all error conditions as critical errors and take appropriate action within its implementation e.g. use assertion failures. The runtime firmware provides the following API for registering a handler for a particular type of interrupt. A Secure Payload Dispatcher service should use this API to register a handler for Secure-EL1 and optionally for non-secure interrupts. This API also requires the caller to specify the routing model for the type of interrupt. int32_t register_interrupt_type_handler(uint32_t type, interrupt_type_handler handler, uint64_t flags); The `type` parameter can be one of the three interrupt types listed above i.e. `INTR_TYPE_S_EL1`, `INTR_TYPE_NS` & `INTR_TYPE_EL3` (currently unimplemented). The `flags` parameter is as described in Section 2. The function will return `0` upon a successful registration. It will return `-EALREADY` in case a handler for the interrupt type has already been registered. If the `type` is unrecognised or the `flags` or the `handler` are invalid it will return `-EINVAL`. It will return `-ENOTSUP` if the specified `type` is not supported by the framework i.e. `INTR_TYPE_EL3`. Interrupt routing is governed by the configuration of the `SCR_EL3.FIQ/IRQ` bits prior to entry into a lower exception level in either security state. The context management library maintains a copy of the `SCR_EL3` system register for each security state in the `cpu_context` structure of each CPU. It exports the following APIs to let EL3 Runtime Firmware program and retrieve the routing model for each security state for the current CPU. The value of `SCR_EL3` stored in the `cpu_context` is used by the `el3_exit()` function to program the `SCR_EL3` register prior to returning from the EL3 exception level. uint32_t cm_get_scr_el3(uint32_t security_state); void cm_write_scr_el3_bit(uint32_t security_state, uint32_t bit_pos, uint32_t value); `cm_get_scr_el3()` returns the value of the `SCR_EL3` register for the specified security state of the current CPU. `cm_write_scr_el3()` writes a `0` or `1` to the bit specified by `bit_pos`. `register_interrupt_type_handler()` invokes `set_routing_model()` API which programs the `SCR_EL3` according to the routing model using the `cm_get_scr_el3()` and `cm_write_scr_el3_bit()` APIs. It is worth noting that in the current implementation of the framework, the EL3 runtime firmware is responsible for programming the routing model. The SPD is responsible for ensuring that the routing model has been adhered to upon receiving an interrupt. #### 2.2.2 Secure payload dispatcher A SPD service is responsible for determining and maintaining the interrupt routing model supported by itself and the Secure Payload. It is also responsible for ferrying interrupts between secure and non-secure software depending upon the routing model. It could determine the routing model at build time or at runtime. It must use this information to register a handler for each interrupt type using the `register_interrupt_type_handler()` API in EL3 runtime firmware. If the routing model is not known to the SPD service at build time, then it must be provided by the SP as the result of its initialisation. The SPD should program the routing model only after SP initialisation has completed e.g. in the SPD initialisation function pointed to by the `bl32_init` variable. The SPD should determine the mechanism to pass control to the Secure Payload after receiving an interrupt from the EL3 runtime firmware. This information could either be provided to the SPD service at build time or by the SP at runtime. #### 2.2.2.1 Test secure payload dispatcher behavior The TSPD only handles Secure-EL1 interrupts and is provided with the following routing model at build time. * Secure-EL1 interrupts are routed to EL3 when execution is in non-secure state and are routed to the FEL when execution is in the secure state i.e __CSS=0, TEL3=0__ & __CSS=1, TEL3=1__ for Secure-EL1 interrupts * The default routing model is used for non-secure interrupts i.e they are routed to the FEL in either security state i.e __CSS=0, TEL3=0__ & __CSS=1, TEL3=0__ for Non-secure interrupts It performs the following actions in the `tspd_init()` function to fulfill the requirements mentioned earlier. 1. It passes control to the Test Secure Payload to perform its initialisation. The TSP provides the address of the vector table `tsp_vectors` in the SP which also includes the handler for Secure-EL1 interrupts in the `fiq_entry` field. The TSPD passes control to the TSP at this address when it receives a Secure-EL1 interrupt. The handover agreement between the TSP and the TSPD requires that the TSPD masks all interrupts (`PSTATE.DAIF` bits) when it calls `tsp_fiq_entry()`. The TSP has to preserve the callee saved general purpose, SP_EL1/Secure-EL0, LR, VFP and system registers. It can use `x0-x18` to enable its C runtime. 2. The TSPD implements a handler function for Secure-EL1 interrupts. It registers it with the EL3 runtime firmware using the `register_interrupt_type_handler()` API as follows /* Forward declaration */ interrupt_type_handler tspd_secure_el1_interrupt_handler; int32_t rc, flags = 0; set_interrupt_rm_flag(flags, NON_SECURE); rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, tspd_secure_el1_interrupt_handler, flags); assert(rc == 0); #### 2.2.3 Secure payload A Secure Payload must implement an interrupt handling framework at Secure-EL1 (Secure-EL1 IHF) to support its chosen interrupt routing model. Secure payload execution will alternate between the below cases. 1. In the code where IRQ, FIQ or both interrupts are enabled, if an interrupt type is targeted to the FEL, then it will be routed to the Secure-EL1 exception vector table. This is defined as the asynchronous model of handling interrupts. This mode applies to both Secure-EL1 and non-secure interrupts. 2. In the code where both interrupts are disabled, if an interrupt type is targeted to the FEL, then execution will eventually migrate to the non-secure state. Any non-secure interrupts will be handled as described in the routing model where __CSS=1 and TEL3=0__. Secure-EL1 interrupts will be routed to EL3 (as per the routing model where __CSS=1 and TEL3=1__) where the SPD service will hand them to the SP. This is defined as the synchronous mode of handling interrupts. The interrupt handling framework implemented by the SP should support one or both these interrupt handling models depending upon the chosen routing model. The following list briefly describes how the choice of a valid routing model (See 1.2.3) effects the implementation of the Secure-EL1 IHF. If the choice of the interrupt routing model is not known to the SPD service at compile time, then the SP should pass this information to the SPD service at runtime during its initialisation phase. As mentioned earlier, it is assumed that the FIQ signal is used to generate Secure-EL1 interrupts and the IRQ signal is used to generate non-secure interrupts in either security state. ##### 2.2.3.1 Secure payload IHF design w.r.t secure-EL1 interrupts 1. __CSS=0, TEL3=0__. If `PSTATE.F=0`, Secure-EL1 interrupts will be trigerred at one of the Secure-EL1 FIQ exception vectors. The Secure-EL1 IHF should implement support for handling FIQ interrupts asynchronously. If `PSTATE.F=1` then Secure-EL1 interrupts will be handled as per the synchronous interrupt handling model. The SP could implement this scenario by exporting a seperate entrypoint for Secure-EL1 interrupts to the SPD service during the registration phase. The SPD service would also need to know the state of the system, general purpose and the `PSTATE` registers in which it should arrange to return execution to the SP. The SP should provide this information in an implementation defined way during the registration phase if it is not known to the SPD service at build time. 2. __CSS=1, TEL3=1__. Interrupts are routed to EL3 when execution is in non-secure state. They should be handled through the synchronous interrupt handling model as described in 1. above. 3. __CSS=0, TEL3=1__. Secure interrupts are routed to EL3 when execution is in secure state. They will not be visible to the SP. The `PSTATE.F` bit in Secure-EL1/Secure-EL0 will not mask FIQs. The EL3 runtime firmware will call the handler registered by the SPD service for Secure-EL1 interrupts. Secure-EL1 IHF should then handle all Secure-EL1 interrupt through the synchronous interrupt handling model described in 1. above. ##### 2.2.3.2 Secure payload IHF design w.r.t non-secure interrupts 1. __CSS=0, TEL3=0__. If `PSTATE.I=0`, non-secure interrupts will be trigerred at one of the Secure-EL1 IRQ exception vectors . The Secure-EL1 IHF should co-ordinate with the SPD service to transfer execution to the non-secure state where the interrupt should be handled e.g the SP could allocate a function identifier to issue a SMC64 or SMC32 to the SPD service which indicates that the SP execution has been pre-empted by a non-secure interrupt. If this function identifier is not known to the SPD service at compile time then the SP could provide it during the registration phase. If `PSTATE.I=1` then the non-secure interrupt will pend until execution resumes in the non-secure state. 2. __CSS=0, TEL3=1__. Non-secure interrupts are routed to EL3. They will not be visible to the SP. The `PSTATE.I` bit in Secure-EL1/Secure-EL0 will have not effect. The SPD service should register a non-secure interrupt handler which should save the SP state correctly and resume execution in the non-secure state where the interrupt will be handled. The Secure-EL1 IHF does not need to take any action. 3. __CSS=1, TEL3=0__. Non-secure interrupts are handled in the FEL in non-secure state (EL1/EL2) and are not visible to the SP. This routing model does not affect the SP behavior. A Secure Payload must also ensure that all Secure-EL1 interrupts are correctly configured at the interrupt controller by the platform port of the EL3 runtime firmware. It should configure any additional Secure-EL1 interrupts which the EL3 runtime firmware is not aware of through its platform port. #### 2.2.3.3 Test secure payload behavior The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is described in Section 2.2.2. It is known to the TSPD service at build time. The TSP implements an entrypoint (`tsp_fiq_entry()`) for handling Secure-EL1 interrupts taken in non-secure state and routed through the TSPD service (synchronous handling model). It passes the reference to this entrypoint via `tsp_vectors` to the TSPD service. The TSP also replaces the default exception vector table referenced through the `early_exceptions` variable, with a vector table capable of handling FIQ and IRQ exceptions taken at the same (Secure-EL1) exception level. This table is referenced through the `tsp_exceptions` variable and programmed into the VBAR_EL1. It caters for the asynchronous handling model. The TSP also programs the Secure Physical Timer in the ARM Generic Timer block to raise a periodic interrupt (every half a second) for the purpose of testing interrupt management across all the software components listed in 2.1 ### 2.3 Interrupt handling This section describes in detail the role of each software component (see Section 2.1) in handling an interrupt of a particular type. #### 2.3.1 EL3 runtime firmware The EL3 runtime firmware populates the IRQ and FIQ exception vectors referenced by the `runtime_exceptions` variable as follows. 1. IRQ and FIQ exceptions taken from the current exception level with `SP_EL0` or `SP_EL3` are reported as irrecoverable error conditions. As mentioned earlier, EL3 runtime firmware always executes with the `PSTATE.I` and `PSTATE.F` bits set. 2. The following text describes how the IRQ and FIQ exceptions taken from a lower exception level using AArch64 or AArch32 are handled. When an interrupt is generated, the vector for each interrupt type is responsible for: 1. Saving the entire general purpose register context (x0-x30) immediately upon exception entry. The registers are saved in the per-cpu `cpu_context` data structure referenced by the `SP_EL3`register. 2. Saving the `ELR_EL3`, `SP_EL0` and `SPSR_EL3` system registers in the per-cpu `cpu_context` data structure referenced by the `SP_EL3` register. 3. Switching to the C runtime stack by restoring the `CTX_RUNTIME_SP` value from the per-cpu `cpu_context` data structure in `SP_EL0` and executing the `msr spsel, #0` instruction. 4. Determining the type of interrupt. Secure-EL1 interrupts will be signalled at the FIQ vector. Non-secure interrupts will be signalled at the IRQ vector. The platform should implement the following API to determine the type of the pending interrupt. uint32_t plat_ic_get_interrupt_type(void); It should return either `INTR_TYPE_S_EL1` or `INTR_TYPE_NS`. 5. Determining the handler for the type of interrupt that has been generated. The following API has been added for this purpose. interrupt_type_handler get_interrupt_type_handler(uint32_t interrupt_type); It returns the reference to the registered handler for this interrupt type. The `handler` is retrieved from the `intr_type_desc_t` structure as described in Section 2. `NULL` is returned if no handler has been registered for this type of interrupt. This scenario is reported as an irrecoverable error condition. 6. Calling the registered handler function for the interrupt type generated. The firmware also determines the interrupt id if the IMF_READ_INTERRUPT_ID build time flag is set. The id is set to `INTR_ID_UNAVAILABLE` if the flag is not set. The id along with the current security state and a reference to the `cpu_context_t` structure for the current security state are passed to the handler function as its arguments. The handler function returns a reference to the per-cpu `cpu_context_t` structure for the target security state. 7. Calling `el3_exit()` to return from EL3 into a lower exception level in the security state determined by the handler routine. The `el3_exit()` function is responsible for restoring the register context from the `cpu_context_t` data structure for the target security state. #### 2.3.2 Secure payload dispatcher ##### 2.3.2.1 Interrupt entry The SPD service begins handling an interrupt when the EL3 runtime firmware calls the handler function for that type of interrupt. The SPD service is responsible for the following: 1. Validating the interrupt. This involves ensuring that the interrupt was generating according to the interrupt routing model specified by the SPD service during registration. It should use the interrupt id and the security state of the exception level (passed in the `flags` parameter of the handler) where the interrupt was taken from to determine this. If the interrupt is not recognised then the handler should treat it as an irrecoverable error condition. A SPD service can register a handler for Secure-EL1 and/or Non-secure interrupts. The following text describes further error scenarios keeping this in mind: 1. __SPD service has registered a handler for Non-secure interrupts__: When an interrupt is received by the handler, it could check its id to ensure it has been configured as a non-secure interrupt at the interrupt controller. A secure interrupt should never be handed to the non-secure interrupt handler. A non-secure interrupt should never be routed to EL3 when execution is in non-secure state. The handler could check the security state flag to ensure this. 2. __SPD service has registered a handler for Secure-EL1 interrupts__: When an interrupt is received by the handler, it could check its id to ensure it has been configured as a secure interrupt at the interrupt controller. A non-secure interrupt should never be handed to the secure interrupt handler. If the routing model chosen is such that Secure-EL1 interrupts are not routed to EL3 when execution is in non-secure state, then a Secure-EL1 interrupt generated in the secure state would be invalid. The handler could use the security state flag to check this. The SPD service should use the platform API: `plat_ic_get_interrupt_type()` to determine the type of interrupt for the specified id. 2. Determining whether the security state of the exception level for handling the interrupt is the same as the security state of the exception level where the interrupt was generated. This depends upon the routing model and type of the interrupt. The SPD should use this information to determine if a context switch is required. The following two cases would require a context switch from secure to non-secure or vice-versa. 1. A Secure-EL1 interrupt taken from the non-secure state should be routed to the Secure Payload. 2. A non-secure interrupt taken from the secure state should be routed to the last known non-secure exception level. The SPD service must save the system register context of the current security state. It must then restore the system register context of the target security state. It should use the `cm_set_next_eret_context()` API to ensure that the next `cpu_context` to be restored is of the target security state. If the target state is secure then execution should be handed to the SP as per the synchronous interrupt handling model it implements. A Secure-EL1 interrupt can be routed to EL3 while execution is in the SP. This implies that SP execution can be preempted while handling an interrupt by a another higher priority Secure-EL1 interrupt (or a EL3 interrupt in the future). The SPD service should manage secure interrupt priorities before handing control to the SP to prevent this type of preemption which can leave the system in an inconsistent state. 3. Setting the return value of the handler to the per-cpu `cpu_context` if the interrupt has been successfully validated and ready to be handled at a lower exception level. The routing model allows non-secure interrupts to be taken to Secure-EL1 when in secure state. The SPD service and the SP should implement a mechanism for routing these interrupts to the last known exception level in the non-secure state. The former should save the SP context, restore the non-secure context and arrange for entry into the non-secure state so that the interrupt can be handled. ##### 2.3.2.2 Interrupt exit When the Secure Payload has finished handling a Secure-EL1 interrupt, it could return control back to the SPD service through a SMC32 or SMC64. The SPD service should handle this secure monitor call so that execution resumes in the exception level and the security state from where the Secure-EL1 interrupt was originally taken. ##### 2.3.2.3 Test secure payload dispatcher behavior The example TSPD service registers a handler for Secure-EL1 interrupts taken from the non-secure state. Its handler `tspd_secure_el1_interrupt_handler()` takes the following actions upon being invoked. 1. It uses the `id` parameter to query the interrupt controller to ensure that the interrupt is a Secure-EL1 interrupt. It asserts if this is not the case. 2. It uses the security state provided in the `flags` parameter to ensure that the secure interrupt originated from the non-secure state. It asserts if this is not the case. 3. It saves the system register context for the non-secure state by calling `cm_el1_sysregs_context_save(NON_SECURE);`. 4. It sets the `ELR_EL3` system register to `tsp_fiq_entry` and sets the `SPSR_EL3.DAIF` bits in the secure CPU context. It sets `x0` to `TSP_HANDLE_FIQ_AND_RETURN`. If the TSP was in the middle of handling a standard SMC, then the `ELR_EL3` and `SPSR_EL3` registers in the secure CPU context are saved first. 5. It restores the system register context for the secure state by calling `cm_el1_sysregs_context_restore(SECURE);`. 6. It ensures that the secure CPU context is used to program the next exception return from EL3 by calling `cm_set_next_eret_context(SECURE);`. 7. It returns the per-cpu `cpu_context` to indicate that the interrupt can now be handled by the SP. `x1` is written with the value of `elr_el3` register for the non-secure state. This information is used by the SP for debugging purposes. The figure below describes how the interrupt handling is implemented by the TSPD when a Secure-EL1 interrupt is generated when execution is in the non-secure state. ![Image 1](diagrams/sec-int-handling.png?raw=true) The TSP issues an SMC with `TSP_HANDLED_S_EL1_FIQ` as the function identifier to signal completion of interrupt handling. The TSP issues an SMC with `TSP_PREEMPTED` as the function identifier to signal generation of a non-secure interrupt in Secure-EL1. The TSPD service takes the following actions in `tspd_smc_handler()` function upon receiving an SMC with `TSP_HANDLED_S_EL1_FIQ` and `TSP_PREEMPTED` as the function identifiers: 1. It ensures that the call originated from the secure state otherwise execution returns to the non-secure state with `SMC_UNK` in `x0`. 2. If the function identifier is `TSP_HANDLED_S_EL1_FIQ`, it restores the saved `ELR_EL3` and `SPSR_EL3` system registers back to the secure CPU context (see step 4 above) in case the TSP had been preempted by a non secure interrupt earlier. It does not save the secure context since the TSP is expected to preserve it (see Section 2.2.2.1) 3. If the function identifier is `TSP_PREEMPTED`, it saves the system register context for the secure state by calling `cm_el1_sysregs_context_save(SECURE)`. 4. It restores the system register context for the non-secure state by calling `cm_el1_sysregs_context_restore(NON_SECURE)`. It sets `x0` to `SMC_PREEMPTED` if the incoming function identifier is `TSP_PREEMPTED`. The Normal World is expected to resume the TSP after the non-secure interrupt handling by issuing an SMC with `TSP_FID_RESUME` as the function identifier. 5. It ensures that the non-secure CPU context is used to program the next exception return from EL3 by calling `cm_set_next_eret_context(NON_SECURE)`. 6. `tspd_smc_handler()` returns a reference to the non-secure `cpu_context` as the return value. As mentioned in 4. above, if a non-secure interrupt preempts the TSP execution then the non-secure software issues an SMC with `TSP_FID_RESUME` as the function identifier to resume TSP execution. The TSPD service takes the following actions in `tspd_smc_handler()` function upon receiving this SMC: 1. It ensures that the call originated from the non secure state. An assertion is raised otherwise. 2. Checks whether the TSP needs a resume i.e check if it was preempted. It then saves the system register context for the secure state by calling `cm_el1_sysregs_context_save(NON_SECURE)`. 3. Restores the secure context by calling `cm_el1_sysregs_context_restore(SECURE)` 4. It ensures that the secure CPU context is used to program the next exception return from EL3 by calling `cm_set_next_eret_context(SECURE)`. 5. `tspd_smc_handler()` returns a reference to the secure `cpu_context` as the return value. The figure below describes how the TSP/TSPD handle a non-secure interrupt when it is generated during execution in the TSP with `PSTATE.I` = 0. ![Image 2](diagrams/non-sec-int-handling.png?raw=true) #### 2.3.3 Secure payload The SP should implement one or both of the synchronous and asynchronous interrupt handling models depending upon the interrupt routing model it has chosen (as described in 2.2.3). In the synchronous model, it should begin handling a Secure-EL1 interrupt after receiving control from the SPD service at an entrypoint agreed upon during build time or during the registration phase. Before handling the interrupt, the SP should save any Secure-EL1 system register context which is needed for resuming normal execution in the SP later e.g. `SPSR_EL1, `ELR_EL1`. After handling the interrupt, the SP could return control back to the exception level and security state where the interrupt was originally taken from. The SP should use an SMC32 or SMC64 to ask the SPD service to do this. In the asynchronous model, the Secure Payload is responsible for handling non-secure and Secure-EL1 interrupts at the IRQ and FIQ vectors in its exception vector table when `PSTATE.I` and `PSTATE.F` bits are 0. As described earlier, when a non-secure interrupt is generated, the SP should coordinate with the SPD service to pass control back to the non-secure state in the last known exception level. This will allow the non-secure interrupt to be handled in the non-secure state. ##### 2.3.3.1 Test secure payload behavior The TSPD hands control of a Secure-EL1 interrupt to the TSP at the `tsp_fiq_entry()`. The TSP handles the interrupt while ensuring that the handover agreement described in Section 2.2.2.1 is maintained. It updates some statistics by calling `tsp_update_sync_fiq_stats()`. It then calls `tsp_fiq_handler()` which. 1. Checks whether the interrupt is the secure physical timer interrupt. It uses the platform API `plat_ic_get_pending_interrupt_id()` to get the interrupt number. 2. Handles the interrupt by acknowledging it using the `plat_ic_acknowledge_interrupt()` platform API, calling `tsp_generic_timer_handler()` to reprogram the secure physical generic timer and calling the `plat_ic_end_of_interrupt()` platform API to signal end of interrupt processing. The TSP passes control back to the TSPD by issuing an SMC64 with `TSP_HANDLED_S_EL1_FIQ` as the function identifier. The TSP handles interrupts under the asynchronous model as follows. 1. Secure-EL1 interrupts are handled by calling the `tsp_fiq_handler()` function. The function has been described above. 2. Non-secure interrupts are handled by issuing an SMC64 with `TSP_PREEMPTED` as the function identifier. Execution resumes at the instruction that follows this SMC instruction when the TSPD hands control to the TSP in response to an SMC with `TSP_FID_RESUME` as the function identifier from the non-secure state (see section 2.3.2.1). - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ [Porting Guide]: ./porting-guide.md arm-trusted-firmware-1.0-aw-6/docs/porting-guide.md000066400000000000000000001640601322600646200222420ustar00rootroot00000000000000ARM Trusted Firmware Porting Guide ================================== Contents -------- 1. Introduction 2. Common Modifications * Common mandatory modifications * Handling reset * Common optional modifications 3. Boot Loader stage specific modifications * Boot Loader stage 1 (BL1) * Boot Loader stage 2 (BL2) * Boot Loader stage 3-1 (BL3-1) * PSCI implementation (in BL3-1) * Interrupt Management framework (in BL3-1) * Crash Reporting mechanism (in BL3-1) 4. C Library 5. Storage abstraction layer - - - - - - - - - - - - - - - - - - 1. Introduction ---------------- Porting the ARM Trusted Firmware to a new platform involves making some mandatory and optional modifications for both the cold and warm boot paths. Modifications consist of: * Implementing a platform-specific function or variable, * Setting up the execution context in a certain way, or * Defining certain constants (for example #defines). The platform-specific functions and variables are all declared in [include/plat/common/platform.h]. The firmware provides a default implementation of variables and functions to fulfill the optional requirements. These implementations are all weakly defined; they are provided to ease the porting effort. Each platform port can override them with its own implementation if the default implementation is inadequate. Some modifications are common to all Boot Loader (BL) stages. Section 2 discusses these in detail. The subsequent sections discuss the remaining modifications for each BL stage in detail. This document should be read in conjunction with the ARM Trusted Firmware [User Guide]. 2. Common modifications ------------------------ This section covers the modifications that should be made by the platform for each BL stage to correctly port the firmware stack. They are categorized as either mandatory or optional. 2.1 Common mandatory modifications ---------------------------------- A platform port must enable the Memory Management Unit (MMU) with identity mapped page tables, and enable both the instruction and data caches for each BL stage. In the ARM FVP port, each BL stage configures the MMU in its platform- specific architecture setup function, for example `blX_plat_arch_setup()`. Each platform must allocate a block of identity mapped secure memory with Device-nGnRE attributes aligned to page boundary (4K) for each BL stage. This memory is identified by the section name `tzfw_coherent_mem` so that its possible for the firmware to place variables in it using the following C code directive: __attribute__ ((section("tzfw_coherent_mem"))) Or alternatively the following assembler code directive: .section tzfw_coherent_mem The `tzfw_coherent_mem` section is used to allocate any data structures that are accessed both when a CPU is executing with its MMU and caches enabled, and when it's running with its MMU and caches disabled. Examples are given below. The following variables, functions and constants must be defined by the platform for the firmware to work correctly. ### File : platform_def.h [mandatory] Each platform must ensure that a header file of this name is in the system include path with the following constants defined. This may require updating the list of `PLAT_INCLUDES` in the `platform.mk` file. In the ARM FVP port, this file is found in [plat/fvp/include/platform_def.h]. * **#define : PLATFORM_LINKER_FORMAT** Defines the linker format used by the platform, for example `elf64-littleaarch64` used by the FVP. * **#define : PLATFORM_LINKER_ARCH** Defines the processor architecture for the linker by the platform, for example `aarch64` used by the FVP. * **#define : PLATFORM_STACK_SIZE** Defines the normal stack memory available to each CPU. This constant is used by [plat/common/aarch64/platform_mp_stack.S] and [plat/common/aarch64/platform_up_stack.S]. * **#define : FIRMWARE_WELCOME_STR** Defines the character string printed by BL1 upon entry into the `bl1_main()` function. * **#define : BL2_IMAGE_NAME** Name of the BL2 binary image on the host file-system. This name is used by BL1 to load BL2 into secure memory from non-volatile storage. * **#define : BL31_IMAGE_NAME** Name of the BL3-1 binary image on the host file-system. This name is used by BL2 to load BL3-1 into secure memory from platform storage. * **#define : BL33_IMAGE_NAME** Name of the BL3-3 binary image on the host file-system. This name is used by BL2 to load BL3-3 into non-secure memory from platform storage. * **#define : PLATFORM_CACHE_LINE_SIZE** Defines the size (in bytes) of the largest cache line across all the cache levels in the platform. * **#define : PLATFORM_CLUSTER_COUNT** Defines the total number of clusters implemented by the platform in the system. * **#define : PLATFORM_CORE_COUNT** Defines the total number of CPUs implemented by the platform across all clusters in the system. * **#define : PLATFORM_MAX_CPUS_PER_CLUSTER** Defines the maximum number of CPUs that can be implemented within a cluster on the platform. * **#define : PLATFORM_NUM_AFFS** Defines the total number of nodes in the affinity heirarchy at all affinity levels used by the platform. * **#define : BL1_RO_BASE** Defines the base address in secure ROM where BL1 originally lives. Must be aligned on a page-size boundary. * **#define : BL1_RO_LIMIT** Defines the maximum address in secure ROM that BL1's actual content (i.e. excluding any data section allocated at runtime) can occupy. * **#define : BL1_RW_BASE** Defines the base address in secure RAM where BL1's read-write data will live at runtime. Must be aligned on a page-size boundary. * **#define : BL1_RW_LIMIT** Defines the maximum address in secure RAM that BL1's read-write data can occupy at runtime. * **#define : BL2_BASE** Defines the base address in secure RAM where BL1 loads the BL2 binary image. Must be aligned on a page-size boundary. * **#define : BL2_LIMIT** Defines the maximum address in secure RAM that the BL2 image can occupy. * **#define : BL31_BASE** Defines the base address in secure RAM where BL2 loads the BL3-1 binary image. Must be aligned on a page-size boundary. * **#define : BL31_LIMIT** Defines the maximum address in secure RAM that the BL3-1 image can occupy. * **#define : NS_IMAGE_OFFSET** Defines the base address in non-secure DRAM where BL2 loads the BL3-3 binary image. Must be aligned on a page-size boundary. If a BL3-2 image is supported by the platform, the following constants must also be defined: * **#define : BL32_IMAGE_NAME** Name of the BL3-2 binary image on the host file-system. This name is used by BL2 to load BL3-2 into secure memory from platform storage. * **#define : BL32_BASE** Defines the base address in secure memory where BL2 loads the BL3-2 binary image. Must be aligned on a page-size boundary. * **#define : BL32_LIMIT** Defines the maximum address that the BL3-2 image can occupy. If the Test Secure-EL1 Payload (TSP) instantiation of BL3-2 is supported by the platform, the following constants must also be defined: * **#define : TSP_SEC_MEM_BASE** Defines the base address of the secure memory used by the TSP image on the platform. This must be at the same address or below `BL32_BASE`. * **#define : TSP_SEC_MEM_SIZE** Defines the size of the secure memory used by the BL3-2 image on the platform. `TSP_SEC_MEM_BASE` and `TSP_SEC_MEM_SIZE` must fully accomodate the memory required by the BL3-2 image, defined by `BL32_BASE` and `BL32_LIMIT`. * **#define : TSP_IRQ_SEC_PHY_TIMER** Defines the ID of the secure physical generic timer interrupt used by the TSP's interrupt handling code. If the platform port uses the IO storage framework, the following constants must also be defined: * **#define : MAX_IO_DEVICES** Defines the maximum number of registered IO devices. Attempting to register more devices than this value using `io_register_device()` will fail with IO_RESOURCES_EXHAUSTED. * **#define : MAX_IO_HANDLES** Defines the maximum number of open IO handles. Attempting to open more IO entities than this value using `io_open()` will fail with IO_RESOURCES_EXHAUSTED. The following constants are optional. They should be defined when the platform memory layout implies some image overlaying like on FVP. * **#define : BL31_PROGBITS_LIMIT** Defines the maximum address in secure RAM that the BL3-1's progbits sections can occupy. * **#define : TSP_PROGBITS_LIMIT** Defines the maximum address that the TSP's progbits sections can occupy. ### File : plat_macros.S [mandatory] Each platform must ensure a file of this name is in the system include path with the following macro defined. In the ARM FVP port, this file is found in [plat/fvp/include/plat_macros.S]. * **Macro : plat_print_gic_regs** This macro allows the crash reporting routine to print GIC registers in case of an unhandled exception in BL3-1. This aids in debugging and this macro can be defined to be empty in case GIC register reporting is not desired. * **Macro : plat_print_interconnect_regs** This macro allows the crash reporting routine to print interconnect registers in case of an unhandled exception in BL3-1. This aids in debugging and this macro can be defined to be empty in case interconnect register reporting is not desired. In the ARM FVP port, the CCI snoop control registers are reported. ### Other mandatory modifications The following mandatory modifications may be implemented in any file the implementer chooses. In the ARM FVP port, they are implemented in [plat/fvp/aarch64/plat_common.c]. * **Function : uint64_t plat_get_syscnt_freq(void)** This function is used by the architecture setup code to retrieve the counter frequency for the CPU's generic timer. This value will be programmed into the `CNTFRQ_EL0` register. In the ARM FVP port, it returns the base frequency of the system counter, which is retrieved from the first entry in the frequency modes table. 2.2 Handling Reset ------------------ BL1 by default implements the reset vector where execution starts from a cold or warm boot. BL3-1 can be optionally set as a reset vector using the RESET_TO_BL31 make variable. For each CPU, the reset vector code is responsible for the following tasks: 1. Distinguishing between a cold boot and a warm boot. 2. In the case of a cold boot and the CPU being a secondary CPU, ensuring that the CPU is placed in a platform-specific state until the primary CPU performs the necessary steps to remove it from this state. 3. In the case of a warm boot, ensuring that the CPU jumps to a platform- specific address in the BL3-1 image in the same processor mode as it was when released from reset. The following functions need to be implemented by the platform port to enable reset vector code to perform the above tasks. ### Function : platform_get_entrypoint() [mandatory] Argument : unsigned long Return : unsigned int This function is called with the `SCTLR.M` and `SCTLR.C` bits disabled. The CPU is identified by its `MPIDR`, which is passed as the argument. The function is responsible for distinguishing between a warm and cold reset using platform- specific means. If it's a warm reset then it returns the entrypoint into the BL3-1 image that the CPU must jump to. If it's a cold reset then this function must return zero. This function is also responsible for implementing a platform-specific mechanism to handle the condition where the CPU has been warm reset but there is no entrypoint to jump to. This function does not follow the Procedure Call Standard used by the Application Binary Interface for the ARM 64-bit architecture. The caller should not assume that callee saved registers are preserved across a call to this function. This function fulfills requirement 1 and 3 listed above. ### Function : plat_secondary_cold_boot_setup() [mandatory] Argument : void Return : void This function is called with the MMU and data caches disabled. It is responsible for placing the executing secondary CPU in a platform-specific state until the primary CPU performs the necessary actions to bring it out of that state and allow entry into the OS. In the ARM FVP port, each secondary CPU powers itself off. The primary CPU is responsible for powering up the secondary CPU when normal world software requires them. This function fulfills requirement 2 above. ### Function : platform_is_primary_cpu() [mandatory] Argument : unsigned long Return : unsigned int This function identifies a CPU by its `MPIDR`, which is passed as the argument, to determine whether this CPU is the primary CPU or a secondary CPU. A return value of zero indicates that the CPU is not the primary CPU, while a non-zero return value indicates that the CPU is the primary CPU. ### Function : platform_mem_init() [mandatory] Argument : void Return : void This function is called before any access to data is made by the firmware, in order to carry out any essential memory initialization. The ARM FVP port uses this function to initialize the mailbox memory used for providing the warm-boot entry-point addresses. 2.3 Common optional modifications --------------------------------- The following are helper functions implemented by the firmware that perform common platform-specific tasks. A platform may choose to override these definitions. ### Function : platform_get_core_pos() Argument : unsigned long Return : int A platform may need to convert the `MPIDR` of a CPU to an absolute number, which can be used as a CPU-specific linear index into blocks of memory (for example while allocating per-CPU stacks). This routine contains a simple mechanism to perform this conversion, using the assumption that each cluster contains a maximum of 4 CPUs: linear index = cpu_id + (cluster_id * 4) cpu_id = 8-bit value in MPIDR at affinity level 0 cluster_id = 8-bit value in MPIDR at affinity level 1 ### Function : platform_set_stack() Argument : unsigned long Return : void This function sets the current stack pointer to the normal memory stack that has been allocated for the CPU specificed by MPIDR. For BL images that only require a stack for the primary CPU the parameter is ignored. The size of the stack allocated to each CPU is specified by the platform defined constant `PLATFORM_STACK_SIZE`. Common implementations of this function for the UP and MP BL images are provided in [plat/common/aarch64/platform_up_stack.S] and [plat/common/aarch64/platform_mp_stack.S] ### Function : platform_get_stack() Argument : unsigned long Return : unsigned long This function returns the base address of the normal memory stack that has been allocated for the CPU specificed by MPIDR. For BL images that only require a stack for the primary CPU the parameter is ignored. The size of the stack allocated to each CPU is specified by the platform defined constant `PLATFORM_STACK_SIZE`. Common implementations of this function for the UP and MP BL images are provided in [plat/common/aarch64/platform_up_stack.S] and [plat/common/aarch64/platform_mp_stack.S] ### Function : plat_report_exception() Argument : unsigned int Return : void A platform may need to report various information about its status when an exception is taken, for example the current exception level, the CPU security state (secure/non-secure), the exception type, and so on. This function is called in the following circumstances: * In BL1, whenever an exception is taken. * In BL2, whenever an exception is taken. The default implementation doesn't do anything, to avoid making assumptions about the way the platform displays its status information. This function receives the exception type as its argument. Possible values for exceptions types are listed in the [include/runtime_svc.h] header file. Note that these constants are not related to any architectural exception code; they are just an ARM Trusted Firmware convention. ### Function : plat_reset_handler() Argument : void Return : void A platform may need to do additional initialization after reset. This function allows the platform to do the platform specific intializations. Platform specific errata workarounds could also be implemented here. The api should preserve the value in x10 register as it is used by the caller to store the return address. The default implementation doesn't do anything. ### Function : plat_disable_acp() Argument : void Return : void This api allows a platform to disable the Accelerator Coherency Port (if present) during a cluster power down sequence. The default weak implementation doesn't do anything. Since this api is called during the power down sequence, it has restrictions for stack usage and it can use the registers x0 - x17 as scratch registers. It should preserve the value in x18 register as it is used by the caller to store the return address. 3. Modifications specific to a Boot Loader stage ------------------------------------------------- 3.1 Boot Loader Stage 1 (BL1) ----------------------------- BL1 implements the reset vector where execution starts from after a cold or warm boot. For each CPU, BL1 is responsible for the following tasks: 1. Handling the reset as described in section 2.2 2. In the case of a cold boot and the CPU being the primary CPU, ensuring that only this CPU executes the remaining BL1 code, including loading and passing control to the BL2 stage. 3. Loading the BL2 image from non-volatile storage into secure memory at the address specified by the platform defined constant `BL2_BASE`. 4. Populating a `meminfo` structure with the following information in memory, accessible by BL2 immediately upon entry. meminfo.total_base = Base address of secure RAM visible to BL2 meminfo.total_size = Size of secure RAM visible to BL2 meminfo.free_base = Base address of secure RAM available for allocation to BL2 meminfo.free_size = Size of secure RAM available for allocation to BL2 BL1 places this `meminfo` structure at the beginning of the free memory available for its use. Since BL1 cannot allocate memory dynamically at the moment, its free memory will be available for BL2's use as-is. However, this means that BL2 must read the `meminfo` structure before it starts using its free memory (this is discussed in Section 3.2). In future releases of the ARM Trusted Firmware it will be possible for the platform to decide where it wants to place the `meminfo` structure for BL2. BL1 implements the `bl1_init_bl2_mem_layout()` function to populate the BL2 `meminfo` structure. The platform may override this implementation, for example if the platform wants to restrict the amount of memory visible to BL2. Details of how to do this are given below. The following functions need to be implemented by the platform port to enable BL1 to perform the above tasks. ### Function : bl1_plat_arch_setup() [mandatory] Argument : void Return : void This function performs any platform-specific and architectural setup that the platform requires. Platform-specific setup might include configuration of memory controllers, configuration of the interconnect to allow the cluster to service cache snoop requests from another cluster, and so on. In the ARM FVP port, this function enables CCI snoops into the cluster that the primary CPU is part of. It also enables the MMU. This function helps fulfill requirement 2 above. ### Function : bl1_platform_setup() [mandatory] Argument : void Return : void This function executes with the MMU and data caches enabled. It is responsible for performing any remaining platform-specific setup that can occur after the MMU and data cache have been enabled. This function is also responsible for initializing the storage abstraction layer which is used to load further bootloader images. This function helps fulfill requirement 3 above. ### Function : bl1_plat_sec_mem_layout() [mandatory] Argument : void Return : meminfo * This function should only be called on the cold boot path. It executes with the MMU and data caches enabled. The pointer returned by this function must point to a `meminfo` structure containing the extents and availability of secure RAM for the BL1 stage. meminfo.total_base = Base address of secure RAM visible to BL1 meminfo.total_size = Size of secure RAM visible to BL1 meminfo.free_base = Base address of secure RAM available for allocation to BL1 meminfo.free_size = Size of secure RAM available for allocation to BL1 This information is used by BL1 to load the BL2 image in secure RAM. BL1 also populates a similar structure to tell BL2 the extents of memory available for its own use. This function helps fulfill requirement 3 above. ### Function : bl1_init_bl2_mem_layout() [optional] Argument : meminfo *, meminfo *, unsigned int, unsigned long Return : void BL1 needs to tell the next stage the amount of secure RAM available for it to use. This information is populated in a `meminfo` structure. Depending upon where BL2 has been loaded in secure RAM (determined by `BL2_BASE`), BL1 calculates the amount of free memory available for BL2 to use. BL1 also ensures that its data sections resident in secure RAM are not visible to BL2. An illustration of how this is done in the ARM FVP port is given in the [User Guide], in the Section "Memory layout on Base FVP". ### Function : bl1_plat_set_bl2_ep_info() [mandatory] Argument : image_info *, entry_point_info * Return : void This function is called after loading BL2 image and it can be used to overwrite the entry point set by loader and also set the security state and SPSR which represents the entry point system state for BL2. On FVP, we are setting the security state and the SPSR for the BL2 entrypoint 3.2 Boot Loader Stage 2 (BL2) ----------------------------- The BL2 stage is executed only by the primary CPU, which is determined in BL1 using the `platform_is_primary_cpu()` function. BL1 passed control to BL2 at `BL2_BASE`. BL2 executes in Secure EL1 and is responsible for: 1. (Optional) Loading the BL3-0 binary image (if present) from platform provided non-volatile storage. To load the BL3-0 image, BL2 makes use of the `meminfo` returned by the `bl2_plat_get_bl30_meminfo()` function. The platform also defines the address in memory where BL3-0 is loaded through the optional constant `BL30_BASE`. BL2 uses this information to determine if there is enough memory to load the BL3-0 image. Subsequent handling of the BL3-0 image is platform-specific and is implemented in the `bl2_plat_handle_bl30()` function. If `BL30_BASE` is not defined then this step is not performed. 2. Loading the BL3-1 binary image into secure RAM from non-volatile storage. To load the BL3-1 image, BL2 makes use of the `meminfo` structure passed to it by BL1. This structure allows BL2 to calculate how much secure RAM is available for its use. The platform also defines the address in secure RAM where BL3-1 is loaded through the constant `BL31_BASE`. BL2 uses this information to determine if there is enough memory to load the BL3-1 image. 3. (Optional) Loading the BL3-2 binary image (if present) from platform provided non-volatile storage. To load the BL3-2 image, BL2 makes use of the `meminfo` returned by the `bl2_plat_get_bl32_meminfo()` function. The platform also defines the address in memory where BL3-2 is loaded through the optional constant `BL32_BASE`. BL2 uses this information to determine if there is enough memory to load the BL3-2 image. If `BL32_BASE` is not defined then this and the next step is not performed. 4. (Optional) Arranging to pass control to the BL3-2 image (if present) that has been pre-loaded at `BL32_BASE`. BL2 populates an `entry_point_info` structure in memory provided by the platform with information about how BL3-1 should pass control to the BL3-2 image. 5. Loading the normal world BL3-3 binary image into non-secure DRAM from platform storage and arranging for BL3-1 to pass control to this image. This address is determined using the `plat_get_ns_image_entrypoint()` function described below. 6. BL2 populates an `entry_point_info` structure in memory provided by the platform with information about how BL3-1 should pass control to the other BL images. The following functions must be implemented by the platform port to enable BL2 to perform the above tasks. ### Function : bl2_early_platform_setup() [mandatory] Argument : meminfo * Return : void This function executes with the MMU and data caches disabled. It is only called by the primary CPU. The arguments to this function is the address of the `meminfo` structure populated by BL1. The platform must copy the contents of the `meminfo` structure into a private variable as the original memory may be subsequently overwritten by BL2. The copied structure is made available to all BL2 code through the `bl2_plat_sec_mem_layout()` function. ### Function : bl2_plat_arch_setup() [mandatory] Argument : void Return : void This function executes with the MMU and data caches disabled. It is only called by the primary CPU. The purpose of this function is to perform any architectural initialization that varies across platforms, for example enabling the MMU (since the memory map differs across platforms). ### Function : bl2_platform_setup() [mandatory] Argument : void Return : void This function may execute with the MMU and data caches enabled if the platform port does the necessary initialization in `bl2_plat_arch_setup()`. It is only called by the primary CPU. The purpose of this function is to perform any platform initialization specific to BL2. Platform security components are configured if required. For the Base FVP the TZC-400 TrustZone controller is configured to only grant non-secure access to DRAM. This avoids aliasing between secure and non-secure accesses in the TLB and cache - secure execution states can use the NS attributes in the MMU translation tables to access the DRAM. This function is also responsible for initializing the storage abstraction layer which is used to load further bootloader images. ### Function : bl2_plat_sec_mem_layout() [mandatory] Argument : void Return : meminfo * This function should only be called on the cold boot path. It may execute with the MMU and data caches enabled if the platform port does the necessary initialization in `bl2_plat_arch_setup()`. It is only called by the primary CPU. The purpose of this function is to return a pointer to a `meminfo` structure populated with the extents of secure RAM available for BL2 to use. See `bl2_early_platform_setup()` above. ### Function : bl2_plat_get_bl30_meminfo() [mandatory] Argument : meminfo * Return : void This function is used to get the memory limits where BL2 can load the BL3-0 image. The meminfo provided by this is used by load_image() to validate whether the BL3-0 image can be loaded within the given memory from the given base. ### Function : bl2_plat_handle_bl30() [mandatory] Argument : image_info * Return : int This function is called after loading BL3-0 image and it is used to perform any platform-specific actions required to handle the SCP firmware. Typically it transfers the image into SCP memory using a platform-specific protocol and waits until SCP executes it and signals to the Application Processor (AP) for BL2 execution to continue. This function returns 0 on success, a negative error code otherwise. ### Function : bl2_plat_get_bl31_params() [mandatory] Argument : void Return : bl31_params * BL2 platform code needs to return a pointer to a `bl31_params` structure it will use for passing information to BL3-1. The `bl31_params` structure carries the following information. - Header describing the version information for interpreting the bl31_param structure - Information about executing the BL3-3 image in the `bl33_ep_info` field - Information about executing the BL3-2 image in the `bl32_ep_info` field - Information about the type and extents of BL3-1 image in the `bl31_image_info` field - Information about the type and extents of BL3-2 image in the `bl32_image_info` field - Information about the type and extents of BL3-3 image in the `bl33_image_info` field The memory pointed by this structure and its sub-structures should be accessible from BL3-1 initialisation code. BL3-1 might choose to copy the necessary content, or maintain the structures until BL3-3 is initialised. ### Funtion : bl2_plat_get_bl31_ep_info() [mandatory] Argument : void Return : entry_point_info * BL2 platform code returns a pointer which is used to populate the entry point information for BL3-1 entry point. The location pointed by it should be accessible from BL1 while processing the synchronous exception to run to BL3-1. On FVP this is allocated inside an bl2_to_bl31_params_mem structure which is allocated at an address pointed by PARAMS_BASE. ### Function : bl2_plat_set_bl31_ep_info() [mandatory] Argument : image_info *, entry_point_info * Return : void This function is called after loading BL3-1 image and it can be used to overwrite the entry point set by loader and also set the security state and SPSR which represents the entry point system state for BL3-1. On FVP, we are setting the security state and the SPSR for the BL3-1 entrypoint. ### Function : bl2_plat_set_bl32_ep_info() [mandatory] Argument : image_info *, entry_point_info * Return : void This function is called after loading BL3-2 image and it can be used to overwrite the entry point set by loader and also set the security state and SPSR which represents the entry point system state for BL3-2. On FVP, we are setting the security state and the SPSR for the BL3-2 entrypoint ### Function : bl2_plat_set_bl33_ep_info() [mandatory] Argument : image_info *, entry_point_info * Return : void This function is called after loading BL3-3 image and it can be used to overwrite the entry point set by loader and also set the security state and SPSR which represents the entry point system state for BL3-3. On FVP, we are setting the security state and the SPSR for the BL3-3 entrypoint ### Function : bl2_plat_get_bl32_meminfo() [mandatory] Argument : meminfo * Return : void This function is used to get the memory limits where BL2 can load the BL3-2 image. The meminfo provided by this is used by load_image() to validate whether the BL3-2 image can be loaded with in the given memory from the given base. ### Function : bl2_plat_get_bl33_meminfo() [mandatory] Argument : meminfo * Return : void This function is used to get the memory limits where BL2 can load the BL3-3 image. The meminfo provided by this is used by load_image() to validate whether the BL3-3 image can be loaded with in the given memory from the given base. ### Function : bl2_plat_flush_bl31_params() [mandatory] Argument : void Return : void Once BL2 has populated all the structures that needs to be read by BL1 and BL3-1 including the bl31_params structures and its sub-structures, the bl31_ep_info structure and any platform specific data. It flushes all these data to the main memory so that it is available when we jump to later Bootloader stages with MMU off ### Function : plat_get_ns_image_entrypoint() [mandatory] Argument : void Return : unsigned long As previously described, BL2 is responsible for arranging for control to be passed to a normal world BL image through BL3-1. This function returns the entrypoint of that image, which BL3-1 uses to jump to it. BL2 is responsible for loading the normal world BL3-3 image (e.g. UEFI). 3.2 Boot Loader Stage 3-1 (BL3-1) --------------------------------- During cold boot, the BL3-1 stage is executed only by the primary CPU. This is determined in BL1 using the `platform_is_primary_cpu()` function. BL1 passes control to BL3-1 at `BL31_BASE`. During warm boot, BL3-1 is executed by all CPUs. BL3-1 executes at EL3 and is responsible for: 1. Re-initializing all architectural and platform state. Although BL1 performs some of this initialization, BL3-1 remains resident in EL3 and must ensure that EL3 architectural and platform state is completely initialized. It should make no assumptions about the system state when it receives control. 2. Passing control to a normal world BL image, pre-loaded at a platform- specific address by BL2. BL3-1 uses the `entry_point_info` structure that BL2 populated in memory to do this. 3. Providing runtime firmware services. Currently, BL3-1 only implements a subset of the Power State Coordination Interface (PSCI) API as a runtime service. See Section 3.3 below for details of porting the PSCI implementation. 4. Optionally passing control to the BL3-2 image, pre-loaded at a platform- specific address by BL2. BL3-1 exports a set of apis that allow runtime services to specify the security state in which the next image should be executed and run the corresponding image. BL3-1 uses the `entry_point_info` structure populated by BL2 to do this. If BL3-1 is a reset vector, It also needs to handle the reset as specified in section 2.2 before the tasks described above. The following functions must be implemented by the platform port to enable BL3-1 to perform the above tasks. ### Function : bl31_early_platform_setup() [mandatory] Argument : bl31_params *, void * Return : void This function executes with the MMU and data caches disabled. It is only called by the primary CPU. The arguments to this function are: * The address of the `bl31_params` structure populated by BL2. * An opaque pointer that the platform may use as needed. The platform can copy the contents of the `bl31_params` structure and its sub-structures into private variables if the original memory may be subsequently overwritten by BL3-1 and similarly the `void *` pointing to the platform data also needs to be saved. On the ARM FVP port, BL2 passes a pointer to a `bl31_params` structure populated in the secure DRAM at address `0x6000000` in the bl31_params * argument and it does not use opaque pointer mentioned earlier. BL3-1 does not copy this information to internal data structures as it guarantees that the secure DRAM memory will not be overwritten. It maintains an internal reference to this information in the `bl2_to_bl31_params` variable. ### Function : bl31_plat_arch_setup() [mandatory] Argument : void Return : void This function executes with the MMU and data caches disabled. It is only called by the primary CPU. The purpose of this function is to perform any architectural initialization that varies across platforms, for example enabling the MMU (since the memory map differs across platforms). ### Function : bl31_platform_setup() [mandatory] Argument : void Return : void This function may execute with the MMU and data caches enabled if the platform port does the necessary initialization in `bl31_plat_arch_setup()`. It is only called by the primary CPU. The purpose of this function is to complete platform initialization so that both BL3-1 runtime services and normal world software can function correctly. The ARM FVP port does the following: * Initializes the generic interrupt controller. * Configures the CLCD controller. * Enables system-level implementation of the generic timer counter. * Grants access to the system counter timer module * Initializes the FVP power controller device * Detects the system topology. ### Function : bl31_get_next_image_info() [mandatory] Argument : unsigned int Return : entry_point_info * This function may execute with the MMU and data caches enabled if the platform port does the necessary initializations in `bl31_plat_arch_setup()`. This function is called by `bl31_main()` to retrieve information provided by BL2 for the next image in the security state specified by the argument. BL3-1 uses this information to pass control to that image in the specified security state. This function must return a pointer to the `entry_point_info` structure (that was copied during `bl31_early_platform_setup()`) if the image exists. It should return NULL otherwise. 3.3 Power State Coordination Interface (in BL3-1) ------------------------------------------------ The ARM Trusted Firmware's implementation of the PSCI API is based around the concept of an _affinity instance_. Each _affinity instance_ can be uniquely identified in a system by a CPU ID (the processor `MPIDR` is used in the PSCI interface) and an _affinity level_. A processing element (for example, a CPU) is at level 0. If the CPUs in the system are described in a tree where the node above a CPU is a logical grouping of CPUs that share some state, then affinity level 1 is that group of CPUs (for example, a cluster), and affinity level 2 is a group of clusters (for example, the system). The implementation assumes that the affinity level 1 ID can be computed from the affinity level 0 ID (for example, a unique cluster ID can be computed from the CPU ID). The current implementation computes this on the basis of the recommended use of `MPIDR` affinity fields in the ARM Architecture Reference Manual. BL3-1's platform initialization code exports a pointer to the platform-specific power management operations required for the PSCI implementation to function correctly. This information is populated in the `plat_pm_ops` structure. The PSCI implementation calls members of the `plat_pm_ops` structure for performing power management operations for each affinity instance. For example, the target CPU is specified by its `MPIDR` in a PSCI `CPU_ON` call. The `affinst_on()` handler (if present) is called for each affinity instance as the PSCI implementation powers up each affinity level implemented in the `MPIDR` (for example, CPU, cluster and system). The following functions must be implemented to initialize PSCI functionality in the ARM Trusted Firmware. ### Function : plat_get_aff_count() [mandatory] Argument : unsigned int, unsigned long Return : unsigned int This function may execute with the MMU and data caches enabled if the platform port does the necessary initializations in `bl31_plat_arch_setup()`. It is only called by the primary CPU. This function is called by the PSCI initialization code to detect the system topology. Its purpose is to return the number of affinity instances implemented at a given `affinity level` (specified by the first argument) and a given `MPIDR` (specified by the second argument). For example, on a dual-cluster system where first cluster implements 2 CPUs and the second cluster implements 4 CPUs, a call to this function with an `MPIDR` corresponding to the first cluster (`0x0`) and affinity level 0, would return 2. A call to this function with an `MPIDR` corresponding to the second cluster (`0x100`) and affinity level 0, would return 4. ### Function : plat_get_aff_state() [mandatory] Argument : unsigned int, unsigned long Return : unsigned int This function may execute with the MMU and data caches enabled if the platform port does the necessary initializations in `bl31_plat_arch_setup()`. It is only called by the primary CPU. This function is called by the PSCI initialization code. Its purpose is to return the state of an affinity instance. The affinity instance is determined by the affinity ID at a given `affinity level` (specified by the first argument) and an `MPIDR` (specified by the second argument). The state can be one of `PSCI_AFF_PRESENT` or `PSCI_AFF_ABSENT`. The latter state is used to cater for system topologies where certain affinity instances are unimplemented. For example, consider a platform that implements a single cluster with 4 CPUs and another CPU implemented directly on the interconnect with the cluster. The `MPIDR`s of the cluster would range from `0x0-0x3`. The `MPIDR` of the single CPU would be 0x100 to indicate that it does not belong to cluster 0. Cluster 1 is missing but needs to be accounted for to reach this single CPU in the topology tree. Hence it is marked as `PSCI_AFF_ABSENT`. ### Function : plat_get_max_afflvl() [mandatory] Argument : void Return : int This function may execute with the MMU and data caches enabled if the platform port does the necessary initializations in `bl31_plat_arch_setup()`. It is only called by the primary CPU. This function is called by the PSCI implementation both during cold and warm boot, to determine the maximum affinity level that the power management operations should apply to. ARMv8-A has support for 4 affinity levels. It is likely that hardware will implement fewer affinity levels. This function allows the PSCI implementation to consider only those affinity levels in the system that the platform implements. For example, the Base AEM FVP implements two clusters with a configurable number of CPUs. It reports the maximum affinity level as 1, resulting in PSCI power control up to the cluster level. ### Function : platform_setup_pm() [mandatory] Argument : const plat_pm_ops ** Return : int This function may execute with the MMU and data caches enabled if the platform port does the necessary initializations in `bl31_plat_arch_setup()`. It is only called by the primary CPU. This function is called by PSCI initialization code. Its purpose is to export handler routines for platform-specific power management actions by populating the passed pointer with a pointer to BL3-1's private `plat_pm_ops` structure. A description of each member of this structure is given below. Please refer to the ARM FVP specific implementation of these handlers in [plat/fvp/fvp_pm.c] as an example. A platform port may choose not implement some of the power management operations. #### plat_pm_ops.affinst_standby() Perform the platform-specific setup to enter the standby state indicated by the passed argument. #### plat_pm_ops.affinst_on() Perform the platform specific setup to power on an affinity instance, specified by the `MPIDR` (first argument) and `affinity level` (fourth argument). The `state` (fifth argument) contains the current state of that affinity instance (ON or OFF). This is useful to determine whether any action must be taken. For example, while powering on a CPU, the cluster that contains this CPU might already be in the ON state. The platform decides what actions must be taken to transition from the current state to the target state (indicated by the power management operation). #### plat_pm_ops.affinst_off() Perform the platform specific setup to power off an affinity instance in the `MPIDR` of the calling CPU. It is called by the PSCI `CPU_OFF` API implementation. The `MPIDR` (first argument), `affinity level` (second argument) and `state` (third argument) have a similar meaning as described in the `affinst_on()` operation. They are used to identify the affinity instance on which the call is made and its current state. This gives the platform port an indication of the state transition it must make to perform the requested action. For example, if the calling CPU is the last powered on CPU in the cluster, after powering down affinity level 0 (CPU), the platform port should power down affinity level 1 (the cluster) as well. #### plat_pm_ops.affinst_suspend() Perform the platform specific setup to power off an affinity instance in the `MPIDR` of the calling CPU. It is called by the PSCI `CPU_SUSPEND` API implementation. The `MPIDR` (first argument), `affinity level` (third argument) and `state` (fifth argument) have a similar meaning as described in the `affinst_on()` operation. They are used to identify the affinity instance on which the call is made and its current state. This gives the platform port an indication of the state transition it must make to perform the requested action. For example, if the calling CPU is the last powered on CPU in the cluster, after powering down affinity level 0 (CPU), the platform port should power down affinity level 1 (the cluster) as well. The difference between turning an affinity instance off versus suspending it is that in the former case, the affinity instance is expected to re-initialize its state when its next powered on (see `affinst_on_finish()`). In the latter case, the affinity instance is expected to save enough state so that it can resume execution by restoring this state when its powered on (see `affinst_suspend_finish()`). #### plat_pm_ops.affinst_on_finish() This function is called by the PSCI implementation after the calling CPU is powered on and released from reset in response to an earlier PSCI `CPU_ON` call. It performs the platform-specific setup required to initialize enough state for this CPU to enter the normal world and also provide secure runtime firmware services. The `MPIDR` (first argument), `affinity level` (second argument) and `state` (third argument) have a similar meaning as described in the previous operations. #### plat_pm_ops.affinst_on_suspend() This function is called by the PSCI implementation after the calling CPU is powered on and released from reset in response to an asynchronous wakeup event, for example a timer interrupt that was programmed by the CPU during the `CPU_SUSPEND` call. It performs the platform-specific setup required to restore the saved state for this CPU to resume execution in the normal world and also provide secure runtime firmware services. The `MPIDR` (first argument), `affinity level` (second argument) and `state` (third argument) have a similar meaning as described in the previous operations. BL3-1 platform initialization code must also detect the system topology and the state of each affinity instance in the topology. This information is critical for the PSCI runtime service to function correctly. More details are provided in the description of the `plat_get_aff_count()` and `plat_get_aff_state()` functions above. 3.4 Interrupt Management framework (in BL3-1) ---------------------------------------------- BL3-1 implements an Interrupt Management Framework (IMF) to manage interrupts generated in either security state and targeted to EL1 or EL2 in the non-secure state or EL3/S-EL1 in the secure state. The design of this framework is described in the [IMF Design Guide] A platform should export the following APIs to support the IMF. The following text briefly describes each api and its implementation on the FVP port. The API implementation depends upon the type of interrupt controller present in the platform. The FVP implements an ARM Generic Interrupt Controller (ARM GIC) as per the version 2.0 of the [ARM GIC Architecture Specification] ### Function : plat_interrupt_type_to_line() [mandatory] Argument : uint32_t, uint32_t Return : uint32_t The ARM processor signals an interrupt exception either through the IRQ or FIQ interrupt line. The specific line that is signaled depends on how the interrupt controller (IC) reports different interrupt types from an execution context in either security state. The IMF uses this API to determine which interrupt line the platform IC uses to signal each type of interrupt supported by the framework from a given security state. The first parameter will be one of the `INTR_TYPE_*` values (see [IMF Design Guide]) indicating the target type of the interrupt, the second parameter is the security state of the originating execution context. The return result is the bit position in the `SCR_EL3` register of the respective interrupt trap: IRQ=1, FIQ=2. The FVP port configures the ARM GIC to signal S-EL1 interrupts as FIQs and Non-secure interrupts as IRQs from either security state. ### Function : plat_ic_get_pending_interrupt_type() [mandatory] Argument : void Return : uint32_t This API returns the type of the highest priority pending interrupt at the platform IC. The IMF uses the interrupt type to retrieve the corresponding handler function. `INTR_TYPE_INVAL` is returned when there is no interrupt pending. The valid interrupt types that can be returned are `INTR_TYPE_EL3`, `INTR_TYPE_S_EL1` and `INTR_TYPE_NS`. The FVP port reads the _Highest Priority Pending Interrupt Register_ (`GICC_HPPIR`) to determine the id of the pending interrupt. The type of interrupt depends upon the id value as follows. 1. id < 1022 is reported as a S-EL1 interrupt 2. id = 1022 is reported as a Non-secure interrupt. 3. id = 1023 is reported as an invalid interrupt type. ### Function : plat_ic_get_pending_interrupt_id() [mandatory] Argument : void Return : uint32_t This API returns the id of the highest priority pending interrupt at the platform IC. The IMF passes the id returned by this API to the registered handler for the pending interrupt if the `IMF_READ_INTERRUPT_ID` build time flag is set. INTR_ID_UNAVAILABLE is returned when there is no interrupt pending. The FVP port reads the _Highest Priority Pending Interrupt Register_ (`GICC_HPPIR`) to determine the id of the pending interrupt. The id that is returned by API depends upon the value of the id read from the interrupt controller as follows. 1. id < 1022. id is returned as is. 2. id = 1022. The _Aliased Highest Priority Pending Interrupt Register_ (`GICC_AHPPIR`) is read to determine the id of the non-secure interrupt. This id is returned by the API. 3. id = 1023. `INTR_ID_UNAVAILABLE` is returned. ### Function : plat_ic_acknowledge_interrupt() [mandatory] Argument : void Return : uint32_t This API is used by the CPU to indicate to the platform IC that processing of the highest pending interrupt has begun. It should return the id of the interrupt which is being processed. The FVP port reads the _Interrupt Acknowledge Register_ (`GICC_IAR`). This changes the state of the highest priority pending interrupt from pending to active in the interrupt controller. It returns the value read from the `GICC_IAR`. This value is the id of the interrupt whose state has been changed. The TSP uses this API to start processing of the secure physical timer interrupt. ### Function : plat_ic_end_of_interrupt() [mandatory] Argument : uint32_t Return : void This API is used by the CPU to indicate to the platform IC that processing of the interrupt corresponding to the id (passed as the parameter) has finished. The id should be the same as the id returned by the `plat_ic_acknowledge_interrupt()` API. The FVP port writes the id to the _End of Interrupt Register_ (`GICC_EOIR`). This deactivates the corresponding interrupt in the interrupt controller. The TSP uses this API to finish processing of the secure physical timer interrupt. ### Function : plat_ic_get_interrupt_type() [mandatory] Argument : uint32_t Return : uint32_t This API returns the type of the interrupt id passed as the parameter. `INTR_TYPE_INVAL` is returned if the id is invalid. If the id is valid, a valid interrupt type (one of `INTR_TYPE_EL3`, `INTR_TYPE_S_EL1` and `INTR_TYPE_NS`) is returned depending upon how the interrupt has been configured by the platform IC. The FVP port configures S-EL1 interrupts as Group0 interrupts and Non-secure interrupts as Group1 interrupts. It reads the group value corresponding to the interrupt id from the relevant _Interrupt Group Register_ (`GICD_IGROUPRn`). It uses the group value to determine the type of interrupt. 3.5 Crash Reporting mechanism (in BL3-1) ---------------------------------------------- BL3-1 implements a crash reporting mechanism which prints the various registers of the CPU to enable quick crash analysis and debugging. It requires that a console is designated as the crash console by the platform which will be used to print the register dump. The following functions must be implemented by the platform if it wants crash reporting mechanism in BL3-1. The functions are implemented in assembly so that they can be invoked without a C Runtime stack. ### Function : plat_crash_console_init Argument : void Return : int This API is used by the crash reporting mechanism to initialize the crash console. It should only use the general purpose registers x0 to x2 to do the initialization and returns 1 on success. The FVP port designates the `PL011_UART0` as the crash console and calls the console_core_init() to initialize the console. ### Function : plat_crash_console_putc Argument : int Return : int This API is used by the crash reporting mechanism to print a character on the designated crash console. It should only use general purpose registers x1 and x2 to do its work. The parameter and the return value are in general purpose register x0. The FVP port designates the `PL011_UART0` as the crash console and calls the console_core_putc() to print the character on the console. 4. C Library ------------- To avoid subtle toolchain behavioral dependencies, the header files provided by the compiler are not used. The software is built with the `-nostdinc` flag to ensure no headers are included from the toolchain inadvertently. Instead the required headers are included in the ARM Trusted Firmware source tree. The library only contains those C library definitions required by the local implementation. If more functionality is required, the needed library functions will need to be added to the local implementation. Versions of [FreeBSD] headers can be found in `include/stdlib`. Some of these headers have been cut down in order to simplify the implementation. In order to minimize changes to the header files, the [FreeBSD] layout has been maintained. The generic C library definitions can be found in `include/stdlib` with more system and machine specific declarations in `include/stdlib/sys` and `include/stdlib/machine`. The local C library implementations can be found in `lib/stdlib`. In order to extend the C library these files may need to be modified. It is recommended to use a release version of [FreeBSD] as a starting point. The C library header files in the [FreeBSD] source tree are located in the `include` and `sys/sys` directories. [FreeBSD] machine specific definitions can be found in the `sys/` directories. These files define things like 'the size of a pointer' and 'the range of an integer'. Since an AArch64 port for [FreeBSD] does not yet exist, the machine specific definitions are based on existing machine types with similar properties (for example SPARC64). Where possible, C library function implementations were taken from [FreeBSD] as found in the `lib/libc` directory. A copy of the [FreeBSD] sources can be downloaded with `git`. git clone git://github.com/freebsd/freebsd.git -b origin/release/9.2.0 5. Storage abstraction layer ----------------------------- In order to improve platform independence and portability an storage abstraction layer is used to load data from non-volatile platform storage. Each platform should register devices and their drivers via the Storage layer. These drivers then need to be initialized by bootloader phases as required in their respective `blx_platform_setup()` functions. Currently storage access is only required by BL1 and BL2 phases. The `load_image()` function uses the storage layer to access non-volatile platform storage. It is mandatory to implement at least one storage driver. For the FVP the Firmware Image Package(FIP) driver is provided as the default means to load data from storage (see the "Firmware Image Package" section in the [User Guide]). The storage layer is described in the header file `include/io_storage.h`. The implementation of the common library is in `lib/io_storage.c` and the driver files are located in `drivers/io/`. Each IO driver must provide `io_dev_*` structures, as described in `drivers/io/io_driver.h`. These are returned via a mandatory registration function that is called on platform initialization. The semi-hosting driver implementation in `io_semihosting.c` can be used as an example. The Storage layer provides mechanisms to initialize storage devices before IO operations are called. The basic operations supported by the layer include `open()`, `close()`, `read()`, `write()`, `size()` and `seek()`. Drivers do not have to implement all operations, but each platform must provide at least one driver for a device capable of supporting generic operations such as loading a bootloader image. The current implementation only allows for known images to be loaded by the firmware. These images are specified by using their names, as defined in [include/plat/common/platform.h]. The platform layer (`plat_get_image_source()`) then returns a reference to a device and a driver-specific `spec` which will be understood by the driver to allow access to the image data. The layer is designed in such a way that is it possible to chain drivers with other drivers. For example, file-system drivers may be implemented on top of physical block devices, both represented by IO devices with corresponding drivers. In such a case, the file-system "binding" with the block device may be deferred until the file-system device is initialised. The abstraction currently depends on structures being statically allocated by the drivers and callers, as the system does not yet provide a means of dynamically allocating memory. This may also have the affect of limiting the amount of open resources per driver. - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._ [ARM GIC Architecture Specification]: http://arminfo.emea.arm.com/help/topic/com.arm.doc.ihi0048b/IHI0048B_gic_architecture_specification.pdf [IMF Design Guide]: interrupt-framework-design.md [User Guide]: user-guide.md [FreeBSD]: http://www.freebsd.org [plat/common/aarch64/platform_mp_stack.S]: ../plat/common/aarch64/platform_mp_stack.S [plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S [plat/fvp/include/platform_def.h]: ../plat/fvp/include/platform_def.h [plat/fvp/include/plat_macros.S]: ../plat/fvp/include/plat_macros.S [plat/fvp/aarch64/plat_common.c]: ../plat/fvp/aarch64/plat_common.c [plat/fvp/plat_pm.c]: ../plat/fvp/plat_pm.c [include/runtime_svc.h]: ../include/runtime_svc.h [include/plat/common/platform.h]: ../include/plat/common/platform.h arm-trusted-firmware-1.0-aw-6/docs/rt-svc-writers-guide.md000066400000000000000000000323201322600646200234640ustar00rootroot00000000000000EL3 Runtime Service Writers Guide for ARM Trusted Firmware ========================================================== Contents -------- 1. Introduction 2. Owning Entities, Call Types and Function IDs 3. Getting started 4. Registering a runtime service 5. Initializing a runtime service 6. Handling runtime service requests 7. Services that contain multiple sub-services 8. Secure-EL1 Payload Dispatcher service (SPD) - - - - - - - - - - - - - - - - - - 1. Introduction ---------------- This document describes how to add a runtime service to the EL3 Runtime Firmware component of ARM Trusted Firmware (BL3-1). Software executing in the normal world and in the trusted world at exception levels lower than EL3 will request runtime services using the Secure Monitor Call (SMC) instruction. These requests will follow the convention described in the SMC Calling Convention PDD ([SMCCC]). The [SMCCC] assigns function identifiers to each SMC request and describes how arguments are passed and results are returned. SMC Functions are grouped together based on the implementor of the service, for example a subset of the Function IDs are designated as "OEM Calls" (see [SMCCC] for full details). The EL3 runtime services framework in BL3-1 enables the independent implementation of services for each group, which are then compiled into the BL3-1 image. This simplifies the integration of common software from ARM to support [PSCI], Secure Monitor for a Trusted OS and SoC specific software. The common runtime services framework ensures that SMC Functions are dispatched to their respective service implementation - the [Firmware Design] provides details of how this is achieved. The interface and operation of the runtime services depends heavily on the concepts and definitions described in the [SMCCC], in particular SMC Function IDs, Owning Entity Numbers (OEN), Fast and Standard calls, and the SMC32 and SMC64 calling conventions. Please refer to that document for a full explanation of these terms. 2. Owning Entities, Call Types and Function IDs ------------------------------------------------ The SMC Function Identifier includes a OEN field. These values and their meaning are described in [SMCCC] and summarized in table 1 below. Some entities are allocated a range of of OENs. The OEN must be interpreted in conjunction with the SMC call type, which is either _Fast_ or _Standard_. Fast calls are uninterruptible whereas Standard calls can be pre-empted. The majority of Owning Entities only have allocated ranges for Fast calls: Standard calls are reserved exclusively for Trusted OS providers or for interoperability with legacy 32-bit software that predates the [SMCCC]. Type OEN Service Fast 0 ARM Architecture calls Fast 1 CPU Service calls Fast 2 SiP Service calls Fast 3 OEM Service calls Fast 4 Standard Service calls Fast 5-47 Reserved for future use Fast 48-49 Trusted Application calls Fast 50-63 Trusted OS calls Std 0- 1 Reserved for existing ARMv7 calls Std 2-63 Trusted OS Standard Calls _Table 1: Service types and their corresponding Owning Entity Numbers_ Each individual entity can allocate the valid identifiers within the entity range as they need - it is not necessary to coordinate with other entities of the same type. For example, two SoC providers can use the same Function ID within the SiP Service calls OEN range to mean different things - as these calls should be specific to the SoC. The Standard Runtime Calls OEN is used for services defined by ARM standards, such as [PSCI]. The SMC Function ID also indicates whether the call has followed the SMC32 calling convention, where all parameters are 32-bit, or the SMC64 calling convention, where the parameters are 64-bit. The framework identifies and rejects invalid calls that use the SMC64 calling convention but that originate from an AArch32 caller. The EL3 runtime services framework uses the call type and OEN to identify a specific handler for each SMC call, but it is expected that an individual handler will be responsible for all SMC Functions within a given service type. 3. Getting started ------------------- ARM Trusted Firmware has a [`services`] directory in the source tree under which each owning entity can place the implementation of its runtime service. The [PSCI] implementation is located here in the [`services/std_svc/psci`] directory. Runtime service sources will need to include the [`runtime_svc.h`] header file. 4. Registering a runtime service --------------------------------- A runtime service is registered using the `DECLARE_RT_SVC()` macro, specifying the name of the service, the range of OENs covered, the type of service and initialization and call handler functions. #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) * `_name` is used to identify the data structure declared by this macro, and is also used for diagnostic purposes * `_start` and `_end` values must be based on the `OEN_*` values defined in [`runtime_svc.h`] * `_type` must be one of `SMC_TYPE_FAST` or `SMC_TYPE_STD` * `_setup` is the initialization function with the `rt_svc_init` signature: typedef int32_t (*rt_svc_init)(void); * `_smch` is the SMC handler function with the `rt_svc_handle` signature: typedef uint64_t (*rt_svc_handle)(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *reserved, void *handle, uint64_t flags); Details of the requirements and behavior of the two callbacks is provided in the following sections. During initialization the services framework validates each declared service to ensure that the following conditions are met: 1. The `_start` OEN is not greater than the `_end` OEN 2. The `_end` OEN does not exceed the maximum OEN value (63) 3. The `_type` is one of `SMC_TYPE_FAST` or `SMC_TYPE_STD` 4. `_setup` and `_smch` routines have been specified [`std_svc_setup.c`] provides an example of registering a runtime service: /* Register Standard Service Calls as runtime service */ DECLARE_RT_SVC( std_svc, OEN_STD_START, OEN_STD_END, SMC_TYPE_FAST, std_svc_setup, std_svc_smc_handler ); 5. Initializing a runtime service --------------------------------- Runtime services are initialized once, during cold boot, by the primary CPU after platform and architectural initialization is complete. The framework performs basic validation of the declared service before calling the service initialization function (`_setup` in the declaration). This function must carry out any essential EL3 initialization prior to receiving a SMC Function call via the handler function. On success, the initialization function must return `0`. Any other return value will cause the framework to issue a diagnostic: Error initializing runtime service and then ignore the service - the system will continue to boot but SMC calls will not be passed to the service handler and instead return the _Unknown SMC Function ID_ result `0xFFFFFFFF`. If the system must not be allowed to proceed without the service, the initialization function must itself cause the firmware boot to be halted. If the service uses per-CPU data this must either be initialized for all CPUs during this call, or be done lazily when a CPU first issues an SMC call to that service. 6. Handling runtime service requests ------------------------------------- SMC calls for a service are forwarded by the framework to the service's SMC handler function (`_smch` in the service declaration). This function must have the following signature: typedef uint64_t (*rt_svc_handle)(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *reserved, void *handle, uint64_t flags); The handler is responsible for: 1. Determining that `smc_fid` is a valid and supported SMC Function ID, otherwise completing the request with the _Unknown SMC Function ID_: SMC_RET1(handle, SMC_UNK); 2. Determining if the requested function is valid for the calling security state. SMC Calls can be made from both the normal and trusted worlds and the framework will forward all calls to the service handler. The `flags` parameter to this function indicates the caller security state in bit[0], where a value of `1` indicates a non-secure caller. The `is_caller_secure(flags)` and `is_caller_non_secure(flags)` can be used to test this condition. If invalid, the request should be completed with: SMC_RET1(handle, SMC_UNK); 3. Truncating parameters for calls made using the SMC32 calling convention. Such calls can be determined by checking the CC field in bit[30] of the `smc_fid` parameter, for example by using: if (GET_SMC_CC(smc_fid) == SMC_32) ... For such calls, the upper bits of the parameters x1-x4 and the saved parameters X5-X7 are UNDEFINED and must be explicitly ignored by the handler. This can be done by truncating the values to a suitable 32-bit integer type before use, for example by ensuring that functions defined to handle individual SMC Functions use appropriate 32-bit parameters. 4. Providing the service requested by the SMC Function, utilizing the immediate parameters x1-x4 and/or the additional saved parameters X5-X7. The latter can be retrieved using the `SMC_GET_GP(handle, ref)` function, supplying the appropriate `CTX_GPREG_Xn` reference, e.g. uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 5. Implementing the standard SMC32 Functions that provide information about the implementation of the service. These are the Call Count, Implementor UID and Revision Details for each service documented in section 6 of the [SMCCC]. The ARM Trusted Firmware expects owning entities to follow this recommendation. 5. Returning the result to the caller. The [SMCCC] allows for up to 256 bits of return value in SMC64 using X0-X3 and 128 bits in SMC32 using W0-W3. The framework provides a family of macros to set the multi-register return value and complete the handler: SMC_RET1(handle, x0); SMC_RET2(handle, x0, x1); SMC_RET3(handle, x0, x1, x2); SMC_RET4(handle, x0, x1, x2, x3); The `reserved` parameter to the handler is reserved for future use and can be ignored. The value returned by a SMC handler is also reserved for future use - completion of the handler function must always be via one of the `SMC_RETn()` macros. NOTE: The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow all of the above requirements yet. 7. Services that contain multiple sub-services ----------------------------------------------- It is possible that a single owning entity implements multiple sub-services. For example, the Standard calls service handles `0x84000000`-`0x8400FFFF` and `0xC4000000`-`0xC400FFFF` functions. Within that range, the [PSCI] service handles the `0x84000000`-`0x8400001F` and `0xC4000000`-`0xC400001F` functions. In that respect, [PSCI] is a 'sub-service' of the Standard calls service. In future, there could be additional such sub-services in the Standard calls service which perform independent functions. In this situation it may be valuable to introduce a second level framework to enable independent implementation of sub-services. Such a framework might look very similar to the current runtime services framework, but using a different part of the SMC Function ID to identify the sub-service. Trusted Firmware does not provide such a framework at present. 8. Secure-EL1 Payload Dispatcher service (SPD) ----------------------------------------------- Services that handle SMC Functions targeting a Trusted OS, Trusted Application, or other Secure-EL1 Payload are special. These services need to manage the Secure-EL1 context, provide the _Secure Monitor_ functionality of switching between the normal and secure worlds, deliver SMC Calls through to Secure-EL1 and generally manage the Secure-EL1 Payload through CPU power-state transitions. TODO: Provide details of the additional work required to implement a SPD and the BL3-1 support for these services. Or a reference to the document that will provide this information.... - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ [Firmware Design]: ./firmware-design.md [`services`]: ../services [`services/std_svc/psci`]: ../services/std_svc/psci [`std_svc_setup.c`]: ../services/std_svc/std_svc_setup.c [`runtime_svc.h`]: ../include/runtime_svc.h [PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022b/index.html "Power State Coordination Interface PDD (ARM DEN 0022B.b)" [SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" arm-trusted-firmware-1.0-aw-6/docs/user-guide.md000066400000000000000000001205511322600646200215330ustar00rootroot00000000000000ARM Trusted Firmware User Guide =============================== Contents : 1. Introduction 2. Host machine requirements 3. Tools 4. Building the Trusted Firmware 5. Obtaining the normal world software 6. Preparing the images to run on FVP 7. Running the software on FVP 8. Preparing the images to run on Juno 9. Running the software on Juno 1. Introduction ---------------- This document describes how to build ARM Trusted Firmware and run it with a tested set of other software components using defined configurations on the Juno ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is possible to use other software components, configurations and platforms but that is outside the scope of this document. This document should be used in conjunction with the [Firmware Design]. 2. Host machine requirements ----------------------------- The minimum recommended machine specification for building the software and running the FVP models is a dual-core processor running at 2GHz with 12GB of RAM. For best performance, use a machine with a quad-core processor running at 2.6GHz with 16GB of RAM. The software has been tested on Ubuntu 12.04.04 (64-bit). Packages used for building the software were installed from that distribution unless otherwise specified. 3. Tools --------- The following tools are required to use the ARM Trusted Firmware: * `git` package to obtain source code. * `build-essential`, `uuid-dev` and `iasl` packages for building UEFI and the Firmware Image Package (FIP) tool. * `bc` and `ncurses-dev` packages for building Linux. * `device-tree-compiler` package for building the Flattened Device Tree (FDT) source files (`.dts` files) provided with this software. * Baremetal GNU GCC tools. Verified packages can be downloaded from [Linaro] [Linaro Toolchain]. The rest of this document assumes that the `gcc-linaro-aarch64-none-elf-4.9-2014.07_linux.tar.xz` tools are used. wget http://releases.linaro.org/14.07/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.9-2014.07_linux.tar.xz tar -xf gcc-linaro-aarch64-none-elf-4.9-2014.07_linux.tar.xz * (Optional) For debugging, ARM [Development Studio 5 (DS-5)][DS-5] v5.19. 4. Building the Trusted Firmware --------------------------------- To build the Trusted Firmware images, follow these steps: 1. Clone the ARM Trusted Firmware repository from GitHub: git clone https://github.com/ARM-software/arm-trusted-firmware.git 2. Change to the trusted firmware directory: cd arm-trusted-firmware 3. Set the compiler path, specify a Non-trusted Firmware image (BL3-3) and a valid platform, and then build: CROSS_COMPILE=/bin/aarch64-none-elf- \ BL33=/ \ make PLAT= all fip If `PLAT` is not specified, `fvp` is assumed by default. See the "Summary of build options" for more information on available build options. The BL3-3 image corresponds to the software that is executed after switching to the non-secure world. UEFI can be used as the BL3-3 image. Refer to the "Obtaining the normal world software" section below. The TSP (Test Secure Payload), corresponding to the BL3-2 image, is not compiled in by default. Refer to the "Building the Test Secure Payload" section below. By default this produces a release version of the build. To produce a debug version instead, refer to the "Debugging options" section below. The build process creates products in a `build` directory tree, building the objects and binaries for each boot loader stage in separate sub-directories. The following boot loader binary files are created from the corresponding ELF files: * `build///bl1.bin` * `build///bl2.bin` * `build///bl31.bin` where `` is the name of the chosen platform and `` is either `debug` or `release`. A Firmare Image Package (FIP) will be created as part of the build. It contains all boot loader images except for `bl1.bin`. * `build///fip.bin` For more information on FIPs, see the "Firmware Image Package" section in the [Firmware Design]. 4. (Optional) Some platforms may require a BL3-0 image to boot. This image can be included in the FIP when building the Trusted Firmware by specifying the `BL30` build option: BL30=/ 5. Output binary files `bl1.bin` and `fip.bin` are both required to boot the system. How these files are used is platform specific. Refer to the platform documentation on how to use the firmware images. 6. (Optional) Build products for a specific build variant can be removed using: make DEBUG= PLAT= clean ... where `` is `0` or `1`, as specified when building. The build tree can be removed completely using: make realclean ### Summary of build options ARM Trusted Firmware build system supports the following build options. Unless mentioned otherwise, these options are expected to be specified at the build command line and are not to be modified in any component makefiles. Note that the build system doesn't track dependency for build options. Therefore, if any of the build options are changed from a previous build, a clean build must be performed. #### Common build options * `BL30`: Path to BL3-0 image in the host file system. This image is optional. If a BL3-0 image is present then this option must be passed for the `fip` target. * `BL33`: Path to BL33 image in the host file system. This is mandatory for `fip` target. * `CROSS_COMPILE`: Prefix to toolchain binaries. Please refer to examples in this document for usage. * `DEBUG`: Chooses between a debug and release build. It can take either 0 (release) or 1 (debug) as values. 0 is the default. * `LOG_LEVEL`: Chooses the log level, which controls the amount of console log output compiled into the build. This should be one of the following: 0 (LOG_LEVEL_NONE) 10 (LOG_LEVEL_NOTICE) 20 (LOG_LEVEL_ERROR) 30 (LOG_LEVEL_WARNING) 40 (LOG_LEVEL_INFO) 50 (LOG_LEVEL_VERBOSE) All log output up to and including the log level is compiled into the build. The default value is 40 in debug builds and 20 in release builds. * `NS_TIMER_SWITCH`: Enable save and restore for non-secure timer register contents upon world switch. It can take either 0 (don't save and restore) or 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it wants the timer registers to be saved and restored. * `PLAT`: Choose a platform to build ARM Trusted Firmware for. The chosen platform name must be the name of one of the directories under the `plat/` directory other than `common`. * `SPD`: Choose a Secure Payload Dispatcher component to be built into the Trusted Firmware. The value should be the path to the directory containing the SPD source, relative to `services/spd/`; the directory is expected to contain a makefile called `.mk`. * `V`: Verbose build. If assigned anything other than 0, the build commands are printed. Default is 0. * `ARM_GIC_ARCH`: Choice of ARM GIC architecture version used by the ARM GIC driver for implementing the platform GIC API. This API is used by the interrupt management framework. Default is 2 (that is, version 2.0). * `IMF_READ_INTERRUPT_ID`: Boolean flag used by the interrupt management framework to enable passing of the interrupt id to its handler. The id is read using a platform GIC API. `INTR_ID_UNAVAILABLE` is passed instead if this option set to 0. Default is 0. * `RESET_TO_BL31`: Enable BL3-1 entrypoint as the CPU reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 entrypoint) or 1 (CPU reset to BL3-1 entrypoint). The default value is 0. * `CRASH_REPORTING`: A non-zero value enables a console dump of processor register state when an unexpected exception occurs during execution of BL3-1. This option defaults to the value of `DEBUG` - i.e. by default this is only enabled for a debug build of the firmware. * `ASM_ASSERTION`: This flag determines whether the assertion checks within assembly source files are enabled or not. This option defaults to the value of `DEBUG` - that is, by default this is only enabled for a debug build of the firmware. * `TSP_INIT_ASYNC`: Choose BL3-2 initialization method as asynchronous or synchronous, (see "Initializing a BL3-2 Image" section in [Firmware Design]). It can take the value 0 (BL3-2 is initialized using synchronous method) or 1 (BL3-2 is initialized using asynchronous method). Default is 0. #### FVP specific build options * `FVP_SHARED_DATA_LOCATION`: location of the shared memory page. Available options: - `tsram` (default) : top of Trusted SRAM - `tdram` : base of Trusted DRAM * `FVP_TSP_RAM_LOCATION`: location of the TSP binary. Options: - `tsram` (default) : base of Trusted SRAM - `tdram` : Trusted DRAM (above shared data) For a better understanding of FVP options, the FVP memory map is explained in the [Firmware Design]. ### Creating a Firmware Image Package FIPs are automatically created as part of the build instructions described in the previous section. It is also possible to independently build the FIP creation tool and FIPs if required. To do this, follow these steps: Build the tool: make -C tools/fip_create It is recommended to remove the build artifacts before rebuilding: make -C tools/fip_create clean Create a Firmware package that contains existing BL2 and BL3-1 images: # fip_create --help to print usage information # fip_create [--dump to show result] ./tools/fip_create/fip_create fip.bin --dump \ --bl2 build//debug/bl2.bin --bl31 build//debug/bl31.bin Firmware Image Package ToC: --------------------------- - Trusted Boot Firmware BL2: offset=0x88, size=0x81E8 file: 'build//debug/bl2.bin' - EL3 Runtime Firmware BL3-1: offset=0x8270, size=0xC218 file: 'build//debug/bl31.bin' --------------------------- Creating "fip.bin" View the contents of an existing Firmware package: ./tools/fip_create/fip_create fip.bin --dump Firmware Image Package ToC: --------------------------- - Trusted Boot Firmware BL2: offset=0x88, size=0x81E8 - EL3 Runtime Firmware BL3-1: offset=0x8270, size=0xC218 --------------------------- Existing package entries can be individially updated: # Change the BL2 from Debug to Release version ./tools/fip_create/fip_create fip.bin --dump \ --bl2 build//release/bl2.bin Firmware Image Package ToC: --------------------------- - Trusted Boot Firmware BL2: offset=0x88, size=0x7240 file: 'build//release/bl2.bin' - EL3 Runtime Firmware BL3-1: offset=0x72C8, size=0xC218 --------------------------- Updating "fip.bin" ### Debugging options To compile a debug version and make the build more verbose use CROSS_COMPILE=/bin/aarch64-none-elf- \ BL33=/ \ make PLAT= DEBUG=1 V=1 all fip AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for example DS-5) might not support this and may need an older version of DWARF symbols to be emitted by GCC. This can be achieved by using the `-gdwarf-` flag, with the version being set to 2 or 3. Setting the version to 2 is recommended for DS-5 versions older than 5.16. When debugging logic problems it might also be useful to disable all compiler optimizations by using `-O0`. NOTE: Using `-O0` could cause output images to be larger and base addresses might need to be recalculated (see the "Memory layout of BL images" section in the [Firmware Design]). Extra debug options can be passed to the build system by setting `CFLAGS`: CFLAGS='-O0 -gdwarf-2' \ CROSS_COMPILE=/bin/aarch64-none-elf- \ BL33=/ \ make PLAT= DEBUG=1 V=1 all fip ### Building the Test Secure Payload The TSP is coupled with a companion runtime service in the BL3-1 firmware, called the TSPD. Therefore, if you intend to use the TSP, the BL3-1 image must be recompiled as well. For more information on SPs and SPDs, see the "Secure-EL1 Payloads and Dispatchers" section in the [Firmware Design]. First clean the Trusted Firmware build directory to get rid of any previous BL3-1 binary. Then to build the TSP image and include it into the FIP use: CROSS_COMPILE=/bin/aarch64-none-elf- \ BL33=/ \ make PLAT= SPD=tspd all fip An additional boot loader binary file is created in the `build` directory: * `build///bl32.bin` The FIP will now contain the additional BL3-2 image. Here is an example output from an FVP build in release mode including BL3-2 and using FVP_AARCH64_EFI.fd as BL3-3 image: Firmware Image Package ToC: --------------------------- - Trusted Boot Firmware BL2: offset=0xD8, size=0x6000 file: './build/fvp/release/bl2.bin' - EL3 Runtime Firmware BL3-1: offset=0x60D8, size=0x9000 file: './build/fvp/release/bl31.bin' - Secure Payload BL3-2 (Trusted OS): offset=0xF0D8, size=0x3000 file: './build/fvp/release/bl32.bin' - Non-Trusted Firmware BL3-3: offset=0x120D8, size=0x280000 file: '../FVP_AARCH64_EFI.fd' --------------------------- Creating "build/fvp/release/fip.bin" ### Checking source code style When making changes to the source for submission to the project, the source must be in compliance with the Linux style guide, and to assist with this check the project Makefile contains two targets, which both utilise the `checkpatch.pl` script that ships with the Linux source tree. To check the entire source tree, you must first download a copy of `checkpatch.pl` (or the full Linux source), set the `CHECKPATCH` environment variable to point to the script and build the target checkcodebase: make CHECKPATCH=/linux/scripts/checkpatch.pl checkcodebase To just check the style on the files that differ between your local branch and the remote master, use: make CHECKPATCH=/linux/scripts/checkpatch.pl checkpatch If you wish to check your patch against something other than the remote master, set the `BASE_COMMIT` variable to your desired branch. By default, `BASE_COMMIT` is set to `origin/master`. 5. Obtaining the normal world software --------------------------------------- ### Obtaining EDK2 Potentially any kind of non-trusted firmware may be used with the ARM Trusted Firmware but the software has only been tested with the EFI Development Kit 2 (EDK2) open source implementation of the UEFI specification. To build the software to be compatible with the Foundation and Base FVPs, or the Juno platform, follow these steps: 1. Clone the [EDK2 source code][EDK2] from GitHub: git clone -n https://github.com/tianocore/edk2.git Not all required features are available in the EDK2 mainline yet. These can be obtained from the ARM-software EDK2 repository instead: cd edk2 git remote add -f --tags arm-software https://github.com/ARM-software/edk2.git git checkout --detach v1.2 2. Copy build config templates to local workspace # in edk2/ . edksetup.sh 3. Build the EDK2 host tools make -C BaseTools clean make -C BaseTools 4. Build the EDK2 software 1. Build for FVP GCC49_AARCH64_PREFIX=/bin/aarch64-none-elf- \ make -f ArmPlatformPkg/Scripts/Makefile EDK2_ARCH=AARCH64 \ EDK2_DSC=ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc \ EDK2_TOOLCHAIN=GCC49 EDK2_BUILD=RELEASE \ EDK2_MACROS="-n 6 -D ARM_FOUNDATION_FVP=1" The EDK2 binary for use with the ARM Trusted Firmware can then be found here: Build/ArmVExpress-FVP-AArch64/RELEASE_GCC49/FV/FVP_AARCH64_EFI.fd 2. Build for Juno GCC49_AARCH64_PREFIX=/bin/aarch64-none-elf- \ make -f ArmPlatformPkg/ArmJunoPkg/Makefile EDK2_ARCH=AARCH64 \ EDK2_TOOLCHAIN=GCC49 EDK2_BUILD=RELEASE The EDK2 binary for use with the ARM Trusted Firmware can then be found here: Build/ArmJuno/RELEASE_GCC49/FV/BL33_AP_UEFI.fd The EDK2 binary should be specified as `BL33` in in the `make` command line when building the Trusted Firmware. See the "Building the Trusted Firmware" section above. 5. (Optional) To build EDK2 in debug mode, remove `EDK2_BUILD=RELEASE` from the command line. 6. (Optional) To boot Linux using a VirtioBlock file-system, the command line passed from EDK2 to the Linux kernel must be modified as described in the "Obtaining a root file-system" section below. 7. (Optional) If legacy GICv2 locations are used, the EDK2 platform description must be updated. This is required as EDK2 does not support probing for the GIC location. To do this, first clean the EDK2 build directory. make -f ArmPlatformPkg/Scripts/Makefile EDK2_ARCH=AARCH64 \ EDK2_DSC=ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc \ EDK2_TOOLCHAIN=ARMGCC clean Then rebuild EDK2 as described in step 3, using the following flag: -D ARM_FVP_LEGACY_GICV2_LOCATION=1 Finally rebuild the Trusted Firmware to generate a new FIP using the instructions in the "Building the Trusted Firmware" section. ### Obtaining a Linux kernel Preparing a Linux kernel for use on the FVPs can be done as follows (GICv2 support only): 1. Clone Linux: git clone git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Not all required features are available in the kernel mainline yet. These can be obtained from the ARM-software EDK2 repository instead: cd linux git remote add -f --tags arm-software https://github.com/ARM-software/linux.git git checkout --detach 1.1-Juno 2. Build with the Linaro GCC tools. # in linux/ make mrproper make ARCH=arm64 defconfig CROSS_COMPILE=/bin/aarch64-none-elf- \ make -j6 ARCH=arm64 The compiled Linux image will now be found at `arch/arm64/boot/Image`. 6. Preparing the images to run on FVP -------------------------------------- ### Obtaining the Flattened Device Trees Depending on the FVP configuration and Linux configuration used, different FDT files are required. FDTs for the Foundation and Base FVPs can be found in the Trusted Firmware source directory under `fdts/`. The Foundation FVP has a subset of the Base FVP components. For example, the Foundation FVP lacks CLCD and MMC support, and has only one CPU cluster. * `fvp-base-gicv2-psci.dtb` (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base memory map configuration. * `fvp-base-gicv2legacy-psci.dtb` For use with AEMv8 Base FVP with legacy VE GIC memory map configuration. * `fvp-base-gicv3-psci.dtb` For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base memory map configuration and Linux GICv3 support. * `fvp-foundation-gicv2-psci.dtb` (Default) For use with Foundation FVP with Base memory map configuration. * `fvp-foundation-gicv2legacy-psci.dtb` For use with Foundation FVP with legacy VE GIC memory map configuration. * `fvp-foundation-gicv3-psci.dtb` For use with Foundation FVP with Base memory map configuration and Linux GICv3 support. Copy the chosen FDT blob as `fdt.dtb` to the directory from which the FVP is launched. Alternatively a symbolic link may be used. ### Preparing the kernel image Copy the kernel image file `arch/arm64/boot/Image` to the directory from which the FVP is launched. Alternatively a symbolic link may be used. ### Obtaining a root file-system To prepare a Linaro LAMP based Open Embedded file-system, the following instructions can be used as a guide. The file-system can be provided to Linux via VirtioBlock or as a RAM-disk. Both methods are described below. #### Prepare VirtioBlock To prepare a VirtioBlock file-system, do the following: 1. Download and unpack the disk image. NOTE: The unpacked disk image grows to 3 GiB in size. wget http://releases.linaro.org/14.07/openembedded/aarch64/vexpress64-openembedded_lamp-armv8-gcc-4.9_20140727-682.img.gz gunzip vexpress64-openembedded_lamp-armv8-gcc-4.9_20140727-682.img.gz 2. Make sure the Linux kernel has Virtio support enabled using `make ARCH=arm64 menuconfig`. Device Drivers ---> Virtio drivers ---> <*> Platform bus driver for memory mapped virtio devices Device Drivers ---> [*] Block devices ---> <*> Virtio block driver File systems ---> <*> The Extended 4 (ext4) filesystem If some of these configurations are missing, enable them, save the kernel configuration, then rebuild the kernel image using the instructions provided in the section "Obtaining a Linux kernel". 3. Change the Kernel command line to include `root=/dev/vda2`. This can either be done in the EDK2 boot menu or in the platform file. Editing the platform file and rebuilding EDK2 will make the change persist. To do this: 1. In EDK2, edit the following file: ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc 2. Add `root=/dev/vda2` to: gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"" 3. Remove the entry: gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|"" 4. Rebuild EDK2 (see "Obtaining UEFI" section above). 4. The file-system image file should be provided to the model environment by passing it the correct command line option. In the FVPs the following option should be provided in addition to the ones described in the "Running the software on FVP" section below. NOTE: A symbolic link to this file cannot be used with the FVP; the path to the real file must be provided. On the Base FVPs: -C bp.virtioblockdevice.image_path="/" On the Foundation FVP: --block-device="/" 5. Ensure that the FVP doesn't output any error messages. If the following error message is displayed: ERROR: BlockDevice: Failed to open "/"! then make sure the path to the file-system image in the model parameter is correct and that read permission is correctly set on the file-system image file. #### Prepare RAM-disk To prepare a RAM-disk root file-system, do the following: 1. Download the file-system image: wget http://releases.linaro.org/14.07/openembedded/aarch64/linaro-image-lamp-genericarmv8-20140727-701.rootfs.tar.gz 2. Modify the Linaro image: # Prepare for use as RAM-disk. Normally use MMC, NFS or VirtioBlock. # Be careful, otherwise you could damage your host file-system. mkdir tmp; cd tmp sudo sh -c "zcat ../linaro-image-lamp-genericarmv8-20140727-701.rootfs.tar.gz | cpio -id" sudo ln -s sbin/init . sudo sh -c "echo 'devtmpfs /dev devtmpfs mode=0755,nosuid 0 0' >> etc/fstab" sudo sh -c "find . | cpio --quiet -H newc -o | gzip -3 -n > ../filesystem.cpio.gz" cd .. 3. Copy the resultant `filesystem.cpio.gz` to the directory where the FVP is launched from. Alternatively a symbolic link may be used. 7. Running the software on FVP ------------------------------- This version of the ARM Trusted Firmware has been tested on the following ARM FVPs (64-bit versions only). * `Foundation_v8` (Version 2.1, Build 9.0.24) * `FVP_Base_AEMv8A-AEMv8A` (Version 5.8, Build 0.8.5802) * `FVP_Base_Cortex-A57x4-A53x4` (Version 5.8, Build 0.8.5802) * `FVP_Base_Cortex-A57x1-A53x1` (Version 5.8, Build 0.8.5802) * `FVP_Base_Cortex-A57x2-A53x4` (Version 5.8, Build 0.8.5802) NOTE: The build numbers quoted above are those reported by launching the FVP with the `--version` parameter. NOTE: The software will not work on Version 1.0 of the Foundation FVP. The commands below would report an `unhandled argument` error in this case. NOTE: The Foundation FVP does not provide a debugger interface. Please refer to the FVP documentation for a detailed description of the model parameter options. A brief description of the important ones that affect the ARM Trusted Firmware and normal world software behavior is provided below. The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be downloaded for free from [ARM's website][ARM FVP website]. ### Running on the Foundation FVP with reset to BL1 entrypoint The following `Foundation_v8` parameters should be used to boot Linux with 4 CPUs using the ARM Trusted Firmware. NOTE: Using the `--block-device` parameter is not necessary if a Linux RAM-disk file-system is used (see the "Obtaining a File-system" section above). NOTE: The `--data=""@0x8000000` parameter is used to load a Firmware Image Package at the start of NOR FLASH0 (see the "Building the Trusted Firmware" section above). /Foundation_v8 \ --cores=4 \ --no-secure-memory \ --visualization \ --gicv3 \ --data="/"@0x0 \ --data="/"@0x8000000 \ --block-device="/" The default use-case for the Foundation FVP is to enable the GICv3 device in the model but use the GICv2 FDT, in order for Linux to drive the GIC in GICv2 emulation mode. The memory mapped addresses `0x0` and `0x8000000` correspond to the start of trusted ROM and NOR FLASH0 respectively. ### Notes regarding Base FVP configuration options Please refer to these notes in the subsequent "Running on the Base FVP" sections. 1. The `-C bp.flashloader0.fname` parameter is used to load a Firmware Image Package at the start of NOR FLASH0 (see the "Building the Trusted Firmware" section above). 2. Using `cache_state_modelled=1` makes booting very slow. The software will still work (and run much faster) without this option but this will hide any cache maintenance defects in the software. 3. Using the `-C bp.virtioblockdevice.image_path` parameter is not necessary if a Linux RAM-disk file-system is used (see the "Obtaining a root file-system" section above). 4. Setting the `-C bp.secure_memory` parameter to `1` is only supported on Base FVP versions 5.4 and newer. Setting this parameter to `0` is also supported. The `-C bp.tzc_400.diagnostics=1` parameter is optional. It instructs the FVP to provide some helpful information if a secure memory violation occurs. 5. This and the following notes only apply when the firmware is built with the `RESET_TO_BL31` option. The `--data=""@` parameter is used to load bootloader images into Base FVP memory (see the "Building the Trusted Firmware" section above). The base addresses used should match the image base addresses in `platform_def.h` used while linking the images. The BL3-2 image is only needed if BL3-1 has been built to expect a Secure-EL1 Payload. 6. The `-C cluster.cpu.RVBAR=@` parameter, where X and Y are the cluster and CPU numbers respectively, is used to set the reset vector for each core. 7. Changing the default value of `FVP_SHARED_DATA_LOCATION` will also require changing the value of `--data=""@` and `-C cluster.cpu.RVBAR=@`, to the new value of `BL31_BASE` in `platform_def.h`. 8. Changing the default value of `FVP_TSP_RAM_LOCATION` will also require changing the value of `--data=""@` to the new value of `BL32_BASE` in `platform_def.h`. ### Running on the AEMv8 Base FVP with reset to BL1 entrypoint Please read "Notes regarding Base FVP configuration options" section above for information about some of the options to run the software. The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux with 8 CPUs using the ARM Trusted Firmware. /FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C bp.pl011_uart0.untimed_fifos=1 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ -C bp.virtioblockdevice.image_path="/" ### Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint Please read "Notes regarding Base FVP configuration options" section above for information about some of the options to run the software. The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to boot Linux with 8 CPUs using the ARM Trusted Firmware. /FVP_Base_Cortex-A57x4-A53x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C bp.pl011_uart0.untimed_fifos=1 \ -C bp.secureflashloader.fname="/" \ -C bp.flashloader0.fname="/" \ -C bp.virtioblockdevice.image_path="/" ### Running on the AEMv8 Base FVP with reset to BL3-1 entrypoint Please read "Notes regarding Base FVP configuration options" section above for information about some of the options to run the software. The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux with 8 CPUs using the ARM Trusted Firmware. /FVP_Base_AEMv8A-AEMv8A \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cluster0.NUM_CORES=4 \ -C cluster1.NUM_CORES=4 \ -C cache_state_modelled=1 \ -C bp.pl011_uart0.untimed_fifos=1 \ -C cluster0.cpu0.RVBAR=0x04022000 \ -C cluster0.cpu1.RVBAR=0x04022000 \ -C cluster0.cpu2.RVBAR=0x04022000 \ -C cluster0.cpu3.RVBAR=0x04022000 \ -C cluster1.cpu0.RVBAR=0x04022000 \ -C cluster1.cpu1.RVBAR=0x04022000 \ -C cluster1.cpu2.RVBAR=0x04022000 \ -C cluster1.cpu3.RVBAR=0x04022000 \ --data cluster0.cpu0="/"@0x04022000 \ --data cluster0.cpu0="/"@0x04000000 \ --data cluster0.cpu0="/"@0x88000000 \ -C bp.virtioblockdevice.image_path="/" ### Running on the Cortex-A57-A53 Base FVP with reset to BL3-1 entrypoint Please read "Notes regarding Base FVP configuration options" section above for information about some of the options to run the software. The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to boot Linux with 8 CPUs using the ARM Trusted Firmware. /FVP_Base_Cortex-A57x4-A53x4 \ -C pctl.startup=0.0.0.0 \ -C bp.secure_memory=1 \ -C bp.tzc_400.diagnostics=1 \ -C cache_state_modelled=1 \ -C bp.pl011_uart0.untimed_fifos=1 \ -C cluster0.cpu0.RVBARADDR=0x04022000 \ -C cluster0.cpu1.RVBARADDR=0x04022000 \ -C cluster0.cpu2.RVBARADDR=0x04022000 \ -C cluster0.cpu3.RVBARADDR=0x04022000 \ -C cluster1.cpu0.RVBARADDR=0x04022000 \ -C cluster1.cpu1.RVBARADDR=0x04022000 \ -C cluster1.cpu2.RVBARADDR=0x04022000 \ -C cluster1.cpu3.RVBARADDR=0x04022000 \ --data cluster0.cpu0="/"@0x04022000 \ --data cluster0.cpu0="/"@0x04000000 \ --data cluster0.cpu0="/"@0x88000000 \ -C bp.virtioblockdevice.image_path="/" ### Configuring the GICv2 memory map The Base FVP models support GICv2 with the default model parameters at the following addresses. The Foundation FVP also supports these addresses when configured for GICv3 in GICv2 emulation mode. GICv2 Distributor Interface 0x2f000000 GICv2 CPU Interface 0x2c000000 GICv2 Virtual CPU Interface 0x2c010000 GICv2 Hypervisor Interface 0x2c02f000 The AEMv8 Base FVP can be configured to support GICv2 at addresses corresponding to the legacy (Versatile Express) memory map as follows. These are the default addresses when using the Foundation FVP in GICv2 mode. GICv2 Distributor Interface 0x2c001000 GICv2 CPU Interface 0x2c002000 GICv2 Virtual CPU Interface 0x2c004000 GICv2 Hypervisor Interface 0x2c006000 The choice of memory map is reflected in the build variant field (bits[15:12]) in the `SYS_ID` register (Offset `0x0`) in the Versatile Express System registers memory map (`0x1c010000`). * `SYS_ID.Build[15:12]` `0x1` corresponds to the presence of the Base GIC memory map. This is the default value on the Base FVPs. * `SYS_ID.Build[15:12]` `0x0` corresponds to the presence of the Legacy VE GIC memory map. This is the default value on the Foundation FVP. This register can be configured as described in the following sections. NOTE: If the legacy VE GIC memory map is used, then the corresponding FDT and BL3-3 images should be used. #### Configuring AEMv8 Foundation FVP GIC for legacy VE memory map The following parameters configure the Foundation FVP to use GICv2 with the legacy VE memory map: /Foundation_v8 \ --cores=4 \ --no-secure-memory \ --visualization \ --no-gicv3 \ --data="/"@0x0 \ --data="/"@0x8000000 \ --block-device="/" Explicit configuration of the `SYS_ID` register is not required. #### Configuring AEMv8 Base FVP GIC for legacy VE memory map The following parameters configure the AEMv8 Base FVP to use GICv2 with the legacy VE memory map. They must added to the parameters described in the "Running on the AEMv8 Base FVP" section above: -C cluster0.gic.GICD-offset=0x1000 \ -C cluster0.gic.GICC-offset=0x2000 \ -C cluster0.gic.GICH-offset=0x4000 \ -C cluster0.gic.GICH-other-CPU-offset=0x5000 \ -C cluster0.gic.GICV-offset=0x6000 \ -C cluster0.gic.PERIPH-size=0x8000 \ -C cluster1.gic.GICD-offset=0x1000 \ -C cluster1.gic.GICC-offset=0x2000 \ -C cluster1.gic.GICH-offset=0x4000 \ -C cluster1.gic.GICH-other-CPU-offset=0x5000 \ -C cluster1.gic.GICV-offset=0x6000 \ -C cluster1.gic.PERIPH-size=0x8000 \ -C gic_distributor.GICD-alias=0x2c001000 \ -C bp.variant=0x0 The `bp.variant` parameter corresponds to the build variant field of the `SYS_ID` register. Setting this to `0x0` allows the ARM Trusted Firmware to detect the legacy VE memory map while configuring the GIC. 8. Preparing the images to run on Juno --------------------------------------- ### Preparing Trusted Firmware images The Juno platform requires a BL3-0 image to boot up. This image contains the runtime firmware that runs on the SCP (System Control Processor). It can be downloaded from [this ARM website] [SCP download] (requires registration). Rebuild the Trusted Firmware specifying the BL3-0 image. Refer to the section "Building the Trusted Firmware". Alternatively, the FIP image can be updated manually with the BL3-0 image: fip_create --dump --bl30 / / ### Obtaining the Flattened Device Tree Juno's device tree blob is built along with the kernel. It is located in: /arch/arm64/boot/dts/juno.dtb ### Deploying a root filesystem on a USB mass storage device 1. Format the partition on the USB mass storage as ext4 filesystem. A 2GB or larger USB mass storage device is required. If another filesystem type is preferred then support needs to be enabled in the kernel. For example, if the USB mass storage corresponds to /dev/sdb device on your computer, use the following command to format partition 1 as ext4: sudo mkfs.ext4 /dev/sdb1 Note: Please be cautious with this command as it could format your hard drive instead if you specify the wrong device. 2. Mount the USB mass storage on the computer (if not done automatically): sudo mount /dev/sdb1 /media/usb_storage where '/media/usb_storage' corresponds to the mount point (the directory must exist prior to using the mount command). 3. Download the rootfs specified in section "Prepare RAM-disk" and extract the files as root user onto the formatted partition: sudo tar zxf .tar.gz -C /media/usb_storage/ Note: It is not necessary to modify the Linaro image as described in that section since we are not using a RAM-disk. 5. Unmount the USB mass storage: sudo umount /media/usb_storage 9. Running the software on Juno -------------------------------- The steps to install and run the binaries on Juno are as follows: 1. Connect a serial cable to the UART0 port (the top UART port on the back panel). The UART settings are 115200 bauds, 8 bits data, no parity, 1 stop bit. 2. Mount the Juno board storage via the CONFIG USB port This is the only USB type B port on the board, labelled DBG_USB and located on the back panel next to the ON/OFF and HW RESET buttons. Plug a type B USB cable into this port on the Juno board and plug the other end into a host PC, and then issue the following command in the UART0 session: Cmd> usb_on If the board doesn't show the Cmd> prompt then press the black HW RESET button once. Once the Juno board storage is detected by your PC, mount it (if not automatically done by your operating system). mount /dev/sdbX /media/JUNO For the rest of the installation instructions, we will assume that the Juno board storage has been mounted under the /media/JUNO directory. 3. Copy the files obtained from the build process into /media/JUNO/SOFTWARE: bl1.bin fip.bin Image juno.dtb 4. Umount the Juno board storage umount /media/JUNO 5. Reboot the board. In the UART0 session, type: Cmd> reboot - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._ [Firmware Design]: ./firmware-design.md [ARM FVP website]: http://www.arm.com/fvp [SCP download]: https://silver.arm.com/download/download.tm?pv=1764630 [Linaro Toolchain]: http://releases.linaro.org/14.07/components/toolchain/binaries/ [EDK2]: http://github.com/tianocore/edk2 [DS-5]: http://www.arm.com/products/tools/software-tools/ds-5/index.php arm-trusted-firmware-1.0-aw-6/drivers/000077500000000000000000000000001322600646200176625ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/drivers/arm/000077500000000000000000000000001322600646200204415ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/drivers/arm/cci400/000077500000000000000000000000001322600646200214235ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/drivers/arm/cci400/cci400.c000066400000000000000000000072771322600646200225660ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #define MAX_CLUSTERS 2 static unsigned long cci_base_addr; static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS]; void cci_init(unsigned long cci_base, int slave_iface3_cluster_ix, int slave_iface4_cluster_ix) { /* * Check the passed arguments are valid. The cluster indices must be * less than MAX_CLUSTERS, not the same as each other and at least one * of them must be refer to a valid cluster index. */ assert(cci_base); assert(slave_iface3_cluster_ix < MAX_CLUSTERS); assert(slave_iface4_cluster_ix < MAX_CLUSTERS); assert(slave_iface3_cluster_ix != slave_iface4_cluster_ix); assert((slave_iface3_cluster_ix >= 0) || (slave_iface3_cluster_ix >= 0)); cci_base_addr = cci_base; if (slave_iface3_cluster_ix >= 0) cci_cluster_ix_to_iface[slave_iface3_cluster_ix] = SLAVE_IFACE3_OFFSET; if (slave_iface4_cluster_ix >= 0) cci_cluster_ix_to_iface[slave_iface4_cluster_ix] = SLAVE_IFACE4_OFFSET; } static inline unsigned long get_slave_iface_base(unsigned long mpidr) { /* * We assume the TF topology code allocates affinity instances * consecutively from zero. * It is a programming error if this is called without initializing * the slave interface to use for this cluster. */ unsigned int cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; assert(cluster_id < MAX_CLUSTERS); assert(cci_cluster_ix_to_iface[cluster_id] != 0); return cci_base_addr + cci_cluster_ix_to_iface[cluster_id]; } void cci_enable_cluster_coherency(unsigned long mpidr) { assert(cci_base_addr); /* Enable Snoops and DVM messages */ mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, DVM_EN_BIT | SNOOP_EN_BIT); /* Wait for the dust to settle down */ while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) ; } void cci_disable_cluster_coherency(unsigned long mpidr) { assert(cci_base_addr); /* Disable Snoops and DVM messages */ mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, ~(DVM_EN_BIT | SNOOP_EN_BIT)); /* Wait for the dust to settle down */ while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) ; } arm-trusted-firmware-1.0-aw-6/drivers/arm/gic/000077500000000000000000000000001322600646200212035ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/drivers/arm/gic/arm_gic.c000066400000000000000000000345201322600646200227540ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include static unsigned int g_gicc_base; static unsigned int g_gicd_base; static unsigned long g_gicr_base; static const unsigned int *g_irq_sec_ptr; static unsigned int g_num_irqs; /******************************************************************************* * This function does some minimal GICv3 configuration. The Firmware itself does * not fully support GICv3 at this time and relies on GICv2 emulation as * provided by GICv3. This function allows software (like Linux) in later stages * to use full GICv3 features. ******************************************************************************/ static void gicv3_cpuif_setup(void) { unsigned int scr_val, val; uintptr_t base; /* * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep * bit set. In order to allow interrupts to get routed to the CPU we * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep * to clear (GICv3 Architecture specification 5.4.23). * GICR_WAKER is NOT banked per CPU, compute the correct base address * per CPU. */ assert(g_gicr_base); base = gicv3_get_rdist(g_gicr_base, read_mpidr()); if (base == (uintptr_t)NULL) { /* No re-distributor base address. This interface cannot be * configured. */ panic(); } val = gicr_read_waker(base); val &= ~WAKER_PS; gicr_write_waker(base, val); dsb(); /* We need to wait for ChildrenAsleep to clear. */ val = gicr_read_waker(base); while (val & WAKER_CA) val = gicr_read_waker(base); /* * We need to set SCR_EL3.NS in order to see GICv3 non-secure state. * Restore SCR_EL3.NS again before exit. */ scr_val = read_scr(); write_scr(scr_val | SCR_NS_BIT); isb(); /* ensure NS=1 takes effect before accessing ICC_SRE_EL2 */ /* * By default EL2 and NS-EL1 software should be able to enable GICv3 * System register access without any configuration at EL3. But it turns * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So * we need to set it here again. In order to do that we need to enable * register access. We leave it enabled as it should be fine and might * prevent problems with later software trying to access GIC System * Registers. */ val = read_icc_sre_el3(); write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE); val = read_icc_sre_el2(); write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE); write_icc_pmr_el1(GIC_PRI_MASK); isb(); /* commit ICC_* changes before setting NS=0 */ /* Restore SCR_EL3 */ write_scr(scr_val); isb(); /* ensure NS=0 takes effect immediately */ } /******************************************************************************* * This function does some minimal GICv3 configuration when cores go * down. ******************************************************************************/ static void gicv3_cpuif_deactivate(void) { unsigned int val; uintptr_t base; /* * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and * wait for GICR_WAKER.ChildrenAsleep to get set. * (GICv3 Architecture specification 5.4.23). * GICR_WAKER is NOT banked per CPU, compute the correct base address * per CPU. */ assert(g_gicr_base); base = gicv3_get_rdist(g_gicr_base, read_mpidr()); if (base == (uintptr_t)NULL) { /* No re-distributor base address. This interface cannot be * configured. */ panic(); } val = gicr_read_waker(base); val |= WAKER_PS; gicr_write_waker(base, val); dsb(); /* We need to wait for ChildrenAsleep to set. */ val = gicr_read_waker(base); while ((val & WAKER_CA) == 0) val = gicr_read_waker(base); } /******************************************************************************* * Enable secure interrupts and use FIQs to route them. Disable legacy bypass * and set the priority mask register to allow all interrupts to trickle in. ******************************************************************************/ void arm_gic_cpuif_setup(void) { unsigned int val; assert(g_gicc_base); val = gicc_read_iidr(g_gicc_base); /* * If GICv3 we need to do a bit of additional setup. We want to * allow default GICv2 behaviour but allow the next stage to * enable full gicv3 features. */ if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) gicv3_cpuif_setup(); val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0; val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; gicc_write_pmr(g_gicc_base, GIC_PRI_MASK); gicc_write_ctlr(g_gicc_base, val); } /******************************************************************************* * Place the cpu interface in a state where it can never make a cpu exit wfi as * as result of an asserted interrupt. This is critical for powering down a cpu ******************************************************************************/ void arm_gic_cpuif_deactivate(void) { unsigned int val; /* Disable secure, non-secure interrupts and disable their bypass */ assert(g_gicc_base); val = gicc_read_ctlr(g_gicc_base); val &= ~(ENABLE_GRP0 | ENABLE_GRP1); val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; gicc_write_ctlr(g_gicc_base, val); val = gicc_read_iidr(g_gicc_base); /* * If GICv3 we need to do a bit of additional setup. Make sure the * RDIST is put to sleep. */ if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) gicv3_cpuif_deactivate(); } /******************************************************************************* * Per cpu gic distributor setup which will be done by all cpus after a cold * boot/hotplug. This marks out the secure interrupts & enables them. ******************************************************************************/ void arm_gic_pcpu_distif_setup(void) { unsigned int index, irq_num; assert(g_gicd_base); gicd_write_igroupr(g_gicd_base, 0, ~0); assert(!g_num_irqs || g_irq_sec_ptr); for (index = 0; index < g_num_irqs; index++) { irq_num = g_irq_sec_ptr[index]; if (irq_num < MIN_SPI_ID) { /* We have an SGI or a PPI */ gicd_clr_igroupr(g_gicd_base, irq_num); gicd_set_ipriorityr(g_gicd_base, irq_num, GIC_HIGHEST_SEC_PRIORITY); gicd_set_isenabler(g_gicd_base, irq_num); } } } /******************************************************************************* * Global gic distributor setup which will be done by the primary cpu after a * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It * then enables the secure GIC distributor interface. ******************************************************************************/ static void arm_gic_distif_setup(void) { unsigned int num_ints, ctlr, index, irq_num; /* Disable the distributor before going further */ assert(g_gicd_base); ctlr = gicd_read_ctlr(g_gicd_base); ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1); gicd_write_ctlr(g_gicd_base, ctlr); /* * Mark out non-secure interrupts. Calculate number of * IGROUPR registers to consider. Will be equal to the * number of IT_LINES */ num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK; num_ints++; for (index = 0; index < num_ints; index++) gicd_write_igroupr(g_gicd_base, index << IGROUPR_SHIFT, ~0); /* Configure secure interrupts now */ assert(!g_num_irqs || g_irq_sec_ptr); for (index = 0; index < g_num_irqs; index++) { irq_num = g_irq_sec_ptr[index]; if (irq_num >= MIN_SPI_ID) { /* We have an SPI */ gicd_clr_igroupr(g_gicd_base, irq_num); gicd_set_ipriorityr(g_gicd_base, irq_num, GIC_HIGHEST_SEC_PRIORITY); gicd_set_itargetsr(g_gicd_base, irq_num, platform_get_core_pos(read_mpidr())); gicd_set_isenabler(g_gicd_base, irq_num); } } arm_gic_pcpu_distif_setup(); gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0); } /******************************************************************************* * Initialize the ARM GIC driver with the provided platform inputs ******************************************************************************/ void arm_gic_init(unsigned int gicc_base, unsigned int gicd_base, unsigned long gicr_base, const unsigned int *irq_sec_ptr, unsigned int num_irqs ) { assert(gicc_base); assert(gicd_base); assert(!num_irqs || irq_sec_ptr); g_gicc_base = gicc_base; g_gicd_base = gicd_base; g_gicr_base = gicr_base; g_irq_sec_ptr = irq_sec_ptr; g_num_irqs = num_irqs; } /******************************************************************************* * Setup the ARM GIC CPU and distributor interfaces. ******************************************************************************/ void arm_gic_setup(void) { arm_gic_cpuif_setup(); arm_gic_distif_setup(); } /******************************************************************************* * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. * The interrupt controller knows which pin/line it uses to signal a type of * interrupt. This function provides a common implementation of * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use * across platforms. It lets the interrupt management framework determine * for a type of interrupt and security state, which line should be used in the * SCR_EL3 to control its routing to EL3. The interrupt line is represented as * the bit position of the IRQ or FIQ bit in the SCR_EL3. ******************************************************************************/ uint32_t arm_gic_interrupt_type_to_line(uint32_t type, uint32_t security_state) { assert(type == INTR_TYPE_S_EL1 || type == INTR_TYPE_EL3 || type == INTR_TYPE_NS); assert(sec_state_is_valid(security_state)); /* * We ignore the security state parameter under the assumption that * both normal and secure worlds are using ARM GICv2. This parameter * will be used when the secure world starts using GICv3. */ #if ARM_GIC_ARCH == 2 return gicv2_interrupt_type_to_line(g_gicc_base, type); #else #error "Invalid ARM GIC architecture version specified for platform port" #endif /* ARM_GIC_ARCH */ } #if ARM_GIC_ARCH == 2 /******************************************************************************* * This function returns the type of the highest priority pending interrupt at * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no * interrupt pending. ******************************************************************************/ uint32_t arm_gic_get_pending_interrupt_type(void) { uint32_t id; assert(g_gicc_base); id = gicc_read_hppir(g_gicc_base); /* Assume that all secure interrupts are S-EL1 interrupts */ if (id < 1022) return INTR_TYPE_S_EL1; if (id == GIC_SPURIOUS_INTERRUPT) return INTR_TYPE_INVAL; return INTR_TYPE_NS; } /******************************************************************************* * This function returns the id of the highest priority pending interrupt at * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no * interrupt pending. ******************************************************************************/ uint32_t arm_gic_get_pending_interrupt_id(void) { uint32_t id; assert(g_gicc_base); id = gicc_read_hppir(g_gicc_base); if (id < 1022) return id; if (id == 1023) return INTR_ID_UNAVAILABLE; /* * Find out which non-secure interrupt it is under the assumption that * the GICC_CTLR.AckCtl bit is 0. */ return gicc_read_ahppir(g_gicc_base); } /******************************************************************************* * This functions reads the GIC cpu interface Interrupt Acknowledge register * to start handling the pending interrupt. It returns the contents of the IAR. ******************************************************************************/ uint32_t arm_gic_acknowledge_interrupt(void) { assert(g_gicc_base); return gicc_read_IAR(g_gicc_base); } /******************************************************************************* * This functions writes the GIC cpu interface End Of Interrupt register with * the passed value to finish handling the active interrupt ******************************************************************************/ void arm_gic_end_of_interrupt(uint32_t id) { assert(g_gicc_base); gicc_write_EOIR(g_gicc_base, id); } /******************************************************************************* * This function returns the type of the interrupt id depending upon the group * this interrupt has been configured under by the interrupt controller i.e. * group0 or group1. ******************************************************************************/ uint32_t arm_gic_get_interrupt_type(uint32_t id) { uint32_t group; assert(g_gicd_base); group = gicd_get_igroupr(g_gicd_base, id); /* Assume that all secure interrupts are S-EL1 interrupts */ if (group == GRP0) return INTR_TYPE_S_EL1; else return INTR_TYPE_NS; } #else #error "Invalid ARM GIC architecture version specified for platform port" #endif /* ARM_GIC_ARCH */ arm-trusted-firmware-1.0-aw-6/drivers/arm/gic/gic_v2.c000066400000000000000000000240471322600646200225270ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include /******************************************************************************* * GIC Distributor interface accessors for reading entire registers ******************************************************************************/ unsigned int gicd_read_igroupr(unsigned int base, unsigned int id) { unsigned n = id >> IGROUPR_SHIFT; return mmio_read_32(base + GICD_IGROUPR + (n << 2)); } unsigned int gicd_read_isenabler(unsigned int base, unsigned int id) { unsigned n = id >> ISENABLER_SHIFT; return mmio_read_32(base + GICD_ISENABLER + (n << 2)); } unsigned int gicd_read_icenabler(unsigned int base, unsigned int id) { unsigned n = id >> ICENABLER_SHIFT; return mmio_read_32(base + GICD_ICENABLER + (n << 2)); } unsigned int gicd_read_ispendr(unsigned int base, unsigned int id) { unsigned n = id >> ISPENDR_SHIFT; return mmio_read_32(base + GICD_ISPENDR + (n << 2)); } unsigned int gicd_read_icpendr(unsigned int base, unsigned int id) { unsigned n = id >> ICPENDR_SHIFT; return mmio_read_32(base + GICD_ICPENDR + (n << 2)); } unsigned int gicd_read_isactiver(unsigned int base, unsigned int id) { unsigned n = id >> ISACTIVER_SHIFT; return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); } unsigned int gicd_read_icactiver(unsigned int base, unsigned int id) { unsigned n = id >> ICACTIVER_SHIFT; return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); } unsigned int gicd_read_ipriorityr(unsigned int base, unsigned int id) { unsigned n = id >> IPRIORITYR_SHIFT; return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); } unsigned int gicd_read_itargetsr(unsigned int base, unsigned int id) { unsigned n = id >> ITARGETSR_SHIFT; return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); } unsigned int gicd_read_icfgr(unsigned int base, unsigned int id) { unsigned n = id >> ICFGR_SHIFT; return mmio_read_32(base + GICD_ICFGR + (n << 2)); } unsigned int gicd_read_cpendsgir(unsigned int base, unsigned int id) { unsigned n = id >> CPENDSGIR_SHIFT; return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); } unsigned int gicd_read_spendsgir(unsigned int base, unsigned int id) { unsigned n = id >> SPENDSGIR_SHIFT; return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); } /******************************************************************************* * GIC Distributor interface accessors for writing entire registers ******************************************************************************/ void gicd_write_igroupr(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> IGROUPR_SHIFT; mmio_write_32(base + GICD_IGROUPR + (n << 2), val); } void gicd_write_isenabler(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> ISENABLER_SHIFT; mmio_write_32(base + GICD_ISENABLER + (n << 2), val); } void gicd_write_icenabler(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> ICENABLER_SHIFT; mmio_write_32(base + GICD_ICENABLER + (n << 2), val); } void gicd_write_ispendr(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> ISPENDR_SHIFT; mmio_write_32(base + GICD_ISPENDR + (n << 2), val); } void gicd_write_icpendr(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> ICPENDR_SHIFT; mmio_write_32(base + GICD_ICPENDR + (n << 2), val); } void gicd_write_isactiver(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> ISACTIVER_SHIFT; mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); } void gicd_write_icactiver(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> ICACTIVER_SHIFT; mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); } void gicd_write_ipriorityr(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> IPRIORITYR_SHIFT; mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); } void gicd_write_itargetsr(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> ITARGETSR_SHIFT; mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); } void gicd_write_icfgr(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> ICFGR_SHIFT; mmio_write_32(base + GICD_ICFGR + (n << 2), val); } void gicd_write_cpendsgir(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> CPENDSGIR_SHIFT; mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); } void gicd_write_spendsgir(unsigned int base, unsigned int id, unsigned int val) { unsigned n = id >> SPENDSGIR_SHIFT; mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); } /******************************************************************************* * GIC Distributor interface accessors for individual interrupt manipulation ******************************************************************************/ unsigned int gicd_get_igroupr(unsigned int base, unsigned int id) { unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); unsigned int reg_val = gicd_read_igroupr(base, id); return (reg_val >> bit_num) & 0x1; } void gicd_set_igroupr(unsigned int base, unsigned int id) { unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); unsigned int reg_val = gicd_read_igroupr(base, id); gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); } void gicd_clr_igroupr(unsigned int base, unsigned int id) { unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); unsigned int reg_val = gicd_read_igroupr(base, id); gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); } void gicd_set_isenabler(unsigned int base, unsigned int id) { unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); gicd_write_isenabler(base, id, (1 << bit_num)); } void gicd_set_icenabler(unsigned int base, unsigned int id) { unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); gicd_write_icenabler(base, id, (1 << bit_num)); } void gicd_set_ispendr(unsigned int base, unsigned int id) { unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); gicd_write_ispendr(base, id, (1 << bit_num)); } void gicd_set_icpendr(unsigned int base, unsigned int id) { unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); gicd_write_icpendr(base, id, (1 << bit_num)); } void gicd_set_isactiver(unsigned int base, unsigned int id) { unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); gicd_write_isactiver(base, id, (1 << bit_num)); } void gicd_set_icactiver(unsigned int base, unsigned int id) { unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); gicd_write_icactiver(base, id, (1 << bit_num)); } /* * Make sure that the interrupt's group is set before expecting * this function to do its job correctly. */ void gicd_set_ipriorityr(unsigned int base, unsigned int id, unsigned int pri) { unsigned int reg = base + GICD_IPRIORITYR + (id & ~3); unsigned int shift = (id & 3) << 3; unsigned int reg_val = mmio_read_32(reg); /* * Enforce ARM recommendation to manage priority values such * that group1 interrupts always have a lower priority than * group0 interrupts. * Note, lower numerical values are higher priorities so the comparison * checks below are reversed from what might be expected. */ assert(gicd_get_igroupr(base, id) == GRP1 ? pri >= GIC_HIGHEST_NS_PRIORITY && pri <= GIC_LOWEST_NS_PRIORITY : pri >= GIC_HIGHEST_SEC_PRIORITY && pri <= GIC_LOWEST_SEC_PRIORITY); reg_val &= ~(GIC_PRI_MASK << shift); reg_val |= (pri & GIC_PRI_MASK) << shift; mmio_write_32(reg, reg_val); } void gicd_set_itargetsr(unsigned int base, unsigned int id, unsigned int iface) { unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1); unsigned int reg_val = gicd_read_itargetsr(base, id); gicd_write_itargetsr(base, id, reg_val | (1 << iface) << (byte_off << 3)); } /******************************************************************************* * This function allows the interrupt management framework to determine (through * the platform) which interrupt line (IRQ/FIQ) to use for an interrupt type to * route it to EL3. The interrupt line is represented as the bit position of the * IRQ or FIQ bit in the SCR_EL3. ******************************************************************************/ uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type) { uint32_t gicc_ctlr; /* Non-secure interrupts are signalled on the IRQ line always */ if (type == INTR_TYPE_NS) return __builtin_ctz(SCR_IRQ_BIT); /* * Secure interrupts are signalled using the IRQ line if the FIQ_EN * bit is not set else they are signalled using the FIQ line. */ gicc_ctlr = gicc_read_ctlr(cpuif_base); if (gicc_ctlr & FIQ_EN) return __builtin_ctz(SCR_FIQ_BIT); else return __builtin_ctz(SCR_IRQ_BIT); } arm-trusted-firmware-1.0-aw-6/drivers/arm/gic/gic_v3.c000066400000000000000000000056141322600646200225270ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr) { uint32_t cpu_aff, gicr_aff; uint64_t gicr_typer; uintptr_t addr; /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level * mask is the same. */ cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) << GICV3_AFF0_SHIFT; cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) << GICV3_AFF1_SHIFT; cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) << GICV3_AFF2_SHIFT; cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) << GICV3_AFF3_SHIFT; addr = gicr_base; do { gicr_typer = gicr_read_typer(addr); gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) & GICR_TYPER_AFF_MASK; if (cpu_aff == gicr_aff) { /* Disable this print for now as it appears every time * when using PSCI CPU_SUSPEND. * TODO: Print this only the first time for each CPU. * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n", * mpidr, addr); */ return addr; } /* TODO: * For GICv4 we need to adjust the Base address based on * GICR_TYPER.VLPIS */ addr += (1 << GICR_PCPUBASE_SHIFT); } while (!(gicr_typer & GICR_TYPER_LAST)); /* If we get here we did not find a match. */ ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr); return (uintptr_t)NULL; } arm-trusted-firmware-1.0-aw-6/drivers/arm/pl011/000077500000000000000000000000001322600646200212765ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/drivers/arm/pl011/pl011_console.S000066400000000000000000000133141322600646200240030ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include .globl console_init .globl console_putc .globl console_core_init .globl console_core_putc .globl console_getc /* * The console base is in the data section and not in .bss * even though it is zero-init. In particular, this allows * the console functions to start using this variable before * the runtime memory is initialized for images which do not * need to copy the .data section from ROM to RAM. */ .section .data.console_base ; .align 3 console_base: .quad 0x0 /* ----------------------------------------------- * int console_init(unsigned long base_addr, * unsigned int uart_clk, unsigned int baud_rate) * Function to initialize the console without a * C Runtime to print debug information. It saves * the console base to the data section. * In: x0 - console base address * w1 - Uart clock in Hz * w2 - Baud rate * out: return 1 on success. * Clobber list : x1 - x3 * ----------------------------------------------- */ func console_init adrp x3, console_base str x0, [x3, :lo12:console_base] b console_core_init /* ----------------------------------------------- * int console_core_init(unsigned long base_addr, * unsigned int uart_clk, unsigned int baud_rate) * Function to initialize the console without a * C Runtime to print debug information. This * function will be accessed by console_init and * crash reporting. * In: x0 - console base address * w1 - Uart clock in Hz * w2 - Baud rate * Out: return 1 on success * Clobber list : x1, x2 * ----------------------------------------------- */ func console_core_init /* Check the input base address */ cbz x0, init_fail /* Check baud rate and uart clock for sanity */ cbz w1, init_fail cbz w2, init_fail /* Program the baudrate */ /* Divisor = (Uart clock * 4) / baudrate */ lsl w1, w1, #2 udiv w2, w1, w2 /* IBRD = Divisor >> 6 */ lsr w1, w2, #6 /* Write the IBRD */ str w1, [x0, #UARTIBRD] /* FBRD = Divisor & 0x3F */ and w1, w2, #0x3f /* Write the FBRD */ str w1, [x0, #UARTFBRD] mov w1, #PL011_LINE_CONTROL str w1, [x0, #UARTLCR_H] /* Clear any pending errors */ str wzr, [x0, #UARTECR] /* Enable tx, rx, and uart overall */ mov w1, #(PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN) str w1, [x0, #UARTCR] mov w0, #1 init_fail: ret /* --------------------------------------------- * int console_putc(int c) * Function to output a character over the * console. It returns the character printed on * success or -1 on error. * In : x0 - character to be printed * Out : return -1 on error else return character. * Clobber list : x1, x2 * --------------------------------------------- */ func console_putc adrp x2, console_base ldr x1, [x2, :lo12:console_base] b console_core_putc /* -------------------------------------------------------- * int console_core_putc(int c, unsigned int base_addr) * Function to output a character over the console. It * returns the character printed on success or -1 on error. * In : w0 - character to be printed * x1 - console base address * Out : return -1 on error else return character. * Clobber list : x2 * -------------------------------------------------------- */ func console_core_putc /* Check the input parameter */ cbz x1, putc_error /* Prepend '\r' to '\n' */ cmp w0, #0xA b.ne 2f 1: /* Check if the transmit FIFO is full */ ldr w2, [x1, #UARTFR] tbnz w2, #PL011_UARTFR_TXFF_BIT, 1b mov w2, #0xD str w2, [x1, #UARTDR] 2: /* Check if the transmit FIFO is full */ ldr w2, [x1, #UARTFR] tbnz w2, #PL011_UARTFR_TXFF_BIT, 2b str w0, [x1, #UARTDR] ret putc_error: mov w0, #-1 ret /* --------------------------------------------- * int console_getc(void) * Function to get a character from the console. * It returns the character grabbed on success * or -1 on error. * Clobber list : x0, x1 * --------------------------------------------- */ func console_getc adrp x0, console_base ldr x1, [x0, :lo12:console_base] cbz x1, getc_error 1: /* Check if the receive FIFO is empty */ ldr w0, [x1, #UARTFR] tbnz w0, #PL011_UARTFR_RXFE_BIT, 1b ldr w0, [x1, #UARTDR] ret getc_error: mov w0, #-1 ret arm-trusted-firmware-1.0-aw-6/drivers/arm/tzc400/000077500000000000000000000000001322600646200214655ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/drivers/arm/tzc400/tzc400.c000066400000000000000000000205411322600646200226570ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include /* * Implementation defined values used to validate inputs later. * Filters : max of 4 ; 0 to 3 * Regions : max of 9 ; 0 to 8 * Address width : Values between 32 to 64 */ typedef struct tzc_instance { uint64_t base; uint8_t addr_width; uint8_t num_filters; uint8_t num_regions; } tzc_instance_t; tzc_instance_t tzc; static inline uint32_t tzc_read_build_config(uint64_t base) { return mmio_read_32(base + BUILD_CONFIG_OFF); } static inline uint32_t tzc_read_gate_keeper(uint64_t base) { return mmio_read_32(base + GATE_KEEPER_OFF); } static inline void tzc_write_gate_keeper(uint64_t base, uint32_t val) { mmio_write_32(base + GATE_KEEPER_OFF, val); } static inline void tzc_write_action(uint64_t base, tzc_action_t action) { mmio_write_32(base + ACTION_OFF, action); } static inline void tzc_write_region_base_low(uint64_t base, uint32_t region, uint32_t val) { mmio_write_32(base + REGION_BASE_LOW_OFF + REGION_NUM_OFF(region), val); } static inline void tzc_write_region_base_high(uint64_t base, uint32_t region, uint32_t val) { mmio_write_32(base + REGION_BASE_HIGH_OFF + REGION_NUM_OFF(region), val); } static inline void tzc_write_region_top_low(uint64_t base, uint32_t region, uint32_t val) { mmio_write_32(base + REGION_TOP_LOW_OFF + REGION_NUM_OFF(region), val); } static inline void tzc_write_region_top_high(uint64_t base, uint32_t region, uint32_t val) { mmio_write_32(base + REGION_TOP_HIGH_OFF + REGION_NUM_OFF(region), val); } static inline void tzc_write_region_attributes(uint64_t base, uint32_t region, uint32_t val) { mmio_write_32(base + REGION_ATTRIBUTES_OFF + REGION_NUM_OFF(region), val); } static inline void tzc_write_region_id_access(uint64_t base, uint32_t region, uint32_t val) { mmio_write_32(base + REGION_ID_ACCESS_OFF + REGION_NUM_OFF(region), val); } static uint32_t tzc_read_component_id(uint64_t base) { uint32_t id; id = mmio_read_8(base + CID0_OFF); id |= (mmio_read_8(base + CID1_OFF) << 8); id |= (mmio_read_8(base + CID2_OFF) << 16); id |= (mmio_read_8(base + CID3_OFF) << 24); return id; } static uint32_t tzc_get_gate_keeper(uint64_t base, uint8_t filter) { uint32_t tmp; tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & GATE_KEEPER_OS_MASK; return (tmp >> filter) & GATE_KEEPER_FILTER_MASK; } /* This function is not MP safe. */ static void tzc_set_gate_keeper(uint64_t base, uint8_t filter, uint32_t val) { uint32_t tmp; /* Upper half is current state. Lower half is requested state. */ tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & GATE_KEEPER_OS_MASK; if (val) tmp |= (1 << filter); else tmp &= ~(1 << filter); tzc_write_gate_keeper(base, (tmp & GATE_KEEPER_OR_MASK) << GATE_KEEPER_OR_SHIFT); /* Wait here until we see the change reflected in the TZC status. */ while (((tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & GATE_KEEPER_OS_MASK) != tmp) ; } void tzc_init(uint64_t base) { uint32_t tzc_id, tzc_build; assert(base); tzc.base = base; /* * We expect to see a tzc400. Check component ID. The TZC-400 TRM shows * component ID is expected to be "0xB105F00D". */ tzc_id = tzc_read_component_id(tzc.base); if (tzc_id != TZC400_COMPONENT_ID) { ERROR("TZC : Wrong device ID (0x%x).\n", tzc_id); panic(); } /* Save values we will use later. */ tzc_build = tzc_read_build_config(tzc.base); tzc.num_filters = ((tzc_build >> BUILD_CONFIG_NF_SHIFT) & BUILD_CONFIG_NF_MASK) + 1; tzc.addr_width = ((tzc_build >> BUILD_CONFIG_AW_SHIFT) & BUILD_CONFIG_AW_MASK) + 1; tzc.num_regions = ((tzc_build >> BUILD_CONFIG_NR_SHIFT) & BUILD_CONFIG_NR_MASK) + 1; } /* * `tzc_configure_region` is used to program regions into the TrustZone * controller. A region can be associated with more than one filter. The * associated filters are passed in as a bitmap (bit0 = filter0). * NOTE: * The region 0 covers the whole address space and is enabled on all filters, * this cannot be changed. It is, however, possible to change some region 0 * permissions. */ void tzc_configure_region(uint32_t filters, uint8_t region, uint64_t region_base, uint64_t region_top, tzc_region_attributes_t sec_attr, uint32_t ns_device_access) { assert(tzc.base); /* Do range checks on filters and regions. */ assert(((filters >> tzc.num_filters) == 0) && (region < tzc.num_regions)); /* * Do address range check based on TZC configuration. A 64bit address is * the max and expected case. */ assert(((region_top <= (UINT64_MAX >> (64 - tzc.addr_width))) && (region_base < region_top))); /* region_base and (region_top + 1) must be 4KB aligned */ assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0); assert(sec_attr <= TZC_REGION_S_RDWR); /* * Inputs look ok, start programming registers. * All the address registers are 32 bits wide and have a LOW and HIGH * component used to construct a up to a 64bit address. */ tzc_write_region_base_low(tzc.base, region, (uint32_t)(region_base)); tzc_write_region_base_high(tzc.base, region, (uint32_t)(region_base >> 32)); tzc_write_region_top_low(tzc.base, region, (uint32_t)(region_top)); tzc_write_region_top_high(tzc.base, region, (uint32_t)(region_top >> 32)); /* Assign the region to a filter and set secure attributes */ tzc_write_region_attributes(tzc.base, region, (sec_attr << REGION_ATTRIBUTES_SEC_SHIFT) | filters); /* * Specify which non-secure devices have permission to access this * region. */ tzc_write_region_id_access(tzc.base, region, ns_device_access); } void tzc_set_action(tzc_action_t action) { assert(tzc.base); /* * - Currently no handler is provided to trap an error via interrupt * or exception. * - The interrupt action has not been tested. */ tzc_write_action(tzc.base, action); } void tzc_enable_filters(void) { uint32_t state; uint32_t filter; assert(tzc.base); for (filter = 0; filter < tzc.num_filters; filter++) { state = tzc_get_gate_keeper(tzc.base, filter); if (state) { /* The TZC filter is already configured. Changing the * programmer's view in an active system can cause * unpredictable behavior therefore panic for now rather * than try to determine whether this is safe in this * instance. See: * http://infocenter.arm.com/help/index.jsp?\ * topic=/com.arm.doc.ddi0504c/CJHHECBF.html */ ERROR("TZC : Filter %d Gatekeeper already enabled.\n", filter); panic(); } tzc_set_gate_keeper(tzc.base, filter, 1); } } void tzc_disable_filters(void) { uint32_t filter; assert(tzc.base); /* * We don't do the same state check as above as the Gatekeepers are * disabled after reset. */ for (filter = 0; filter < tzc.num_filters; filter++) tzc_set_gate_keeper(tzc.base, filter, 0); } arm-trusted-firmware-1.0-aw-6/drivers/io/000077500000000000000000000000001322600646200202715ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/drivers/io/io_fip.c000066400000000000000000000265761322600646200217220ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include /* Useful for printing UUIDs when debugging.*/ #define PRINT_UUID2(x) \ "%08x-%04hx-%04hx-%02hhx%02hhx-%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", \ x.time_low, x.time_mid, x.time_hi_and_version, \ x.clock_seq_hi_and_reserved, x.clock_seq_low, \ x.node[0], x.node[1], x.node[2], x.node[3], \ x.node[4], x.node[5] typedef struct { const char *name; const uuid_t uuid; } plat_fip_name_uuid_t; typedef struct { /* Put file_pos above the struct to allow {0} on static init. * It is a workaround for a known bug in GCC * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119 */ unsigned int file_pos; fip_toc_entry_t entry; } file_state_t; static const plat_fip_name_uuid_t name_uuid[] = { {BL2_IMAGE_NAME, UUID_TRUSTED_BOOT_FIRMWARE_BL2}, #ifdef BL30_IMAGE_NAME /* BL3-0 is optional in the platform */ {BL30_IMAGE_NAME, UUID_SCP_FIRMWARE_BL30}, #endif /* BL30_IMAGE_NAME */ {BL31_IMAGE_NAME, UUID_EL3_RUNTIME_FIRMWARE_BL31}, #ifdef BL32_IMAGE_NAME /* BL3-2 is optional in the platform */ {BL32_IMAGE_NAME, UUID_SECURE_PAYLOAD_BL32}, #endif /* BL32_IMAGE_NAME */ {BL33_IMAGE_NAME, UUID_NON_TRUSTED_FIRMWARE_BL33}, }; static const uuid_t uuid_null = {0}; static file_state_t current_file = {0}; static uintptr_t backend_dev_handle; static uintptr_t backend_image_spec; /* Firmware Image Package driver functions */ static int fip_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); static int fip_file_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); static int fip_file_len(io_entity_t *entity, size_t *length); static int fip_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); static int fip_file_close(io_entity_t *entity); static int fip_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params); static int fip_dev_close(io_dev_info_t *dev_info); static inline int copy_uuid(uuid_t *dst, const uuid_t *src) { memcpy(dst, src, sizeof(uuid_t)); return 0; } /* Return 0 for equal uuids. */ static inline int compare_uuids(const uuid_t *uuid1, const uuid_t *uuid2) { return memcmp(uuid1, uuid2, sizeof(uuid_t)); } /* TODO: We could check version numbers or do a package checksum? */ static inline int is_valid_header(fip_toc_header_t *header) { if ((header->name == TOC_HEADER_NAME) && (header->serial_number != 0)) { return 1; } else { return 0; } } static int file_to_uuid(const char *filename, uuid_t *uuid) { int i; int status = -EINVAL; for (i = 0; i < (sizeof(name_uuid) / sizeof(name_uuid[0])); i++) { if (strcmp(filename, name_uuid[i].name) == 0) { copy_uuid(uuid, &name_uuid[i].uuid); status = 0; break; } } return status; } /* Identify the device type as a virtual driver */ io_type_t device_type_fip(void) { return IO_TYPE_FIRMWARE_IMAGE_PACKAGE; } static const io_dev_connector_t fip_dev_connector = { .dev_open = fip_dev_open }; static const io_dev_funcs_t fip_dev_funcs = { .type = device_type_fip, .open = fip_file_open, .seek = NULL, .size = fip_file_len, .read = fip_file_read, .write = NULL, .close = fip_file_close, .dev_init = fip_dev_init, .dev_close = fip_dev_close, }; /* No state associated with this device so structure can be const */ static const io_dev_info_t fip_dev_info = { .funcs = &fip_dev_funcs, .info = (uintptr_t)NULL }; /* Open a connection to the FIP device */ static int fip_dev_open(const uintptr_t dev_spec __attribute__((unused)), io_dev_info_t **dev_info) { assert(dev_info != NULL); *dev_info = (io_dev_info_t *)&fip_dev_info; /* cast away const */ return IO_SUCCESS; } /* Do some basic package checks. */ static int fip_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params) { int result = IO_FAIL; char *image_name = (char *)init_params; uintptr_t backend_handle; fip_toc_header_t header; size_t bytes_read; /* Obtain a reference to the image by querying the platform layer */ result = plat_get_image_source(image_name, &backend_dev_handle, &backend_image_spec); if (result != IO_SUCCESS) { WARN("Failed to obtain reference to image '%s' (%i)\n", image_name, result); result = IO_FAIL; goto fip_dev_init_exit; } /* Attempt to access the FIP image */ result = io_open(backend_dev_handle, backend_image_spec, &backend_handle); if (result != IO_SUCCESS) { WARN("Failed to access image '%s' (%i)\n", image_name, result); result = IO_FAIL; goto fip_dev_init_exit; } result = io_read(backend_handle, (uintptr_t)&header, sizeof(header), &bytes_read); if (result == IO_SUCCESS) { if (!is_valid_header(&header)) { WARN("Firmware Image Package header check failed.\n"); result = IO_FAIL; } else { VERBOSE("FIP header looks OK.\n"); } } io_close(backend_handle); fip_dev_init_exit: return result; } /* Close a connection to the FIP device */ static int fip_dev_close(io_dev_info_t *dev_info) { /* TODO: Consider tracking open files and cleaning them up here */ /* Clear the backend. */ backend_dev_handle = (uintptr_t)NULL; backend_image_spec = (uintptr_t)NULL; return IO_SUCCESS; } /* Open a file for access from package. */ static int fip_file_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity) { int result = IO_FAIL; uintptr_t backend_handle; uuid_t file_uuid; const io_file_spec_t *file_spec = (io_file_spec_t *)spec; size_t bytes_read; int found_file = 0; assert(file_spec != NULL); assert(entity != NULL); /* Can only have one file open at a time for the moment. We need to * track state like file cursor position. We know the header lives at * offset zero, so this entry should never be zero for an active file. * When the system supports dynamic memory allocation we can allow more * than one open file at a time if needed. */ if (current_file.entry.offset_address != 0) { WARN("fip_file_open : Only one open file at a time.\n"); return IO_RESOURCES_EXHAUSTED; } /* Attempt to access the FIP image */ result = io_open(backend_dev_handle, backend_image_spec, &backend_handle); if (result != IO_SUCCESS) { WARN("Failed to open Firmware Image Package (%i)\n", result); result = IO_FAIL; goto fip_file_open_exit; } /* Seek past the FIP header into the Table of Contents */ result = io_seek(backend_handle, IO_SEEK_SET, sizeof(fip_toc_header_t)); if (result != IO_SUCCESS) { WARN("fip_file_open: failed to seek\n"); result = IO_FAIL; goto fip_file_open_close; } file_to_uuid(file_spec->path, &file_uuid); found_file = 0; do { result = io_read(backend_handle, (uintptr_t)¤t_file.entry, sizeof(current_file.entry), &bytes_read); if (result == IO_SUCCESS) { if (compare_uuids(¤t_file.entry.uuid, &file_uuid) == 0) { found_file = 1; break; } } else { WARN("Failed to read FIP (%i)\n", result); goto fip_file_open_close; } } while (compare_uuids(¤t_file.entry.uuid, &uuid_null) != 0); if (found_file == 1) { /* All fine. Update entity info with file state and return. Set * the file position to 0. The 'current_file.entry' holds the * base and size of the file. */ current_file.file_pos = 0; entity->info = (uintptr_t)¤t_file; } else { /* Did not find the file in the FIP. */ current_file.entry.offset_address = 0; result = IO_FAIL; } fip_file_open_close: io_close(backend_handle); fip_file_open_exit: return result; } /* Return the size of a file in package */ static int fip_file_len(io_entity_t *entity, size_t *length) { assert(entity != NULL); assert(length != NULL); *length = ((file_state_t *)entity->info)->entry.size; return IO_SUCCESS; } /* Read data from a file in package */ static int fip_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) { int result = IO_FAIL; file_state_t *fp; size_t file_offset; size_t bytes_read; uintptr_t backend_handle; assert(entity != NULL); assert(buffer != (uintptr_t)NULL); assert(length_read != NULL); assert(entity->info != (uintptr_t)NULL); /* Open the backend, attempt to access the blob image */ result = io_open(backend_dev_handle, backend_image_spec, &backend_handle); if (result != IO_SUCCESS) { WARN("Failed to open FIP (%i)\n", result); result = IO_FAIL; goto fip_file_read_exit; } fp = (file_state_t *)entity->info; /* Seek to the position in the FIP where the payload lives */ file_offset = fp->entry.offset_address + fp->file_pos; result = io_seek(backend_handle, IO_SEEK_SET, file_offset); if (result != IO_SUCCESS) { WARN("fip_file_read: failed to seek\n"); result = IO_FAIL; goto fip_file_read_close; } result = io_read(backend_handle, buffer, length, &bytes_read); if (result != IO_SUCCESS) { /* We cannot read our data. Fail. */ WARN("Failed to read payload (%i)\n", result); result = IO_FAIL; goto fip_file_read_close; } else { /* Set caller length and new file position. */ *length_read = bytes_read; fp->file_pos += bytes_read; } /* Close the backend. */ fip_file_read_close: io_close(backend_handle); fip_file_read_exit: return result; } /* Close a file in package */ static int fip_file_close(io_entity_t *entity) { /* Clear our current file pointer. * If we had malloc() we would free() here. */ if (current_file.entry.offset_address != 0) { memset(¤t_file, 0, sizeof(current_file)); } /* Clear the Entity info. */ entity->info = 0; return IO_SUCCESS; } /* Exported functions */ /* Register the Firmware Image Package driver with the IO abstraction */ int register_io_dev_fip(const io_dev_connector_t **dev_con) { int result = IO_FAIL; assert(dev_con != NULL); result = io_register_device(&fip_dev_info); if (result == IO_SUCCESS) *dev_con = &fip_dev_connector; return result; } arm-trusted-firmware-1.0-aw-6/drivers/io/io_memmap.c000066400000000000000000000153601322600646200224050ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include /* As we need to be able to keep state for seek, only one file can be open * at a time. Make this a structure and point to the entity->info. When we * can malloc memory we can change this to support more open files. */ typedef struct { /* Use the 'in_use' flag as any value for base and file_pos could be * valid. */ int in_use; uintptr_t base; size_t file_pos; } file_state_t; static file_state_t current_file = {0}; /* Identify the device type as memmap */ io_type_t device_type_memmap(void) { return IO_TYPE_MEMMAP; } /* Memmap device functions */ static int memmap_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset); static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, size_t length, size_t *length_written); static int memmap_block_close(io_entity_t *entity); static int memmap_dev_close(io_dev_info_t *dev_info); static const io_dev_connector_t memmap_dev_connector = { .dev_open = memmap_dev_open }; static const io_dev_funcs_t memmap_dev_funcs = { .type = device_type_memmap, .open = memmap_block_open, .seek = memmap_block_seek, .size = NULL, .read = memmap_block_read, .write = memmap_block_write, .close = memmap_block_close, .dev_init = NULL, .dev_close = memmap_dev_close, }; /* No state associated with this device so structure can be const */ static const io_dev_info_t memmap_dev_info = { .funcs = &memmap_dev_funcs, .info = (uintptr_t)NULL }; /* Open a connection to the memmap device */ static int memmap_dev_open(const uintptr_t dev_spec __attribute__((unused)), io_dev_info_t **dev_info) { assert(dev_info != NULL); *dev_info = (io_dev_info_t *)&memmap_dev_info; /* cast away const */ return IO_SUCCESS; } /* Close a connection to the memmap device */ static int memmap_dev_close(io_dev_info_t *dev_info) { /* NOP */ /* TODO: Consider tracking open files and cleaning them up here */ return IO_SUCCESS; } /* Open a file on the memmap device */ /* TODO: Can we do any sensible limit checks on requested memory */ static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity) { int result = IO_FAIL; const io_block_spec_t *block_spec = (io_block_spec_t *)spec; /* Since we need to track open state for seek() we only allow one open * spec at a time. When we have dynamic memory we can malloc and set * entity->info. */ if (current_file.in_use == 0) { assert(block_spec != NULL); assert(entity != NULL); current_file.in_use = 1; current_file.base = block_spec->offset; /* File cursor offset for seek and incremental reads etc. */ current_file.file_pos = 0; entity->info = (uintptr_t)¤t_file; result = IO_SUCCESS; } else { WARN("A Memmap device is already active. Close first.\n"); result = IO_RESOURCES_EXHAUSTED; } return result; } /* Seek to a particular file offset on the memmap device */ static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset) { int result = IO_FAIL; /* We only support IO_SEEK_SET for the moment. */ if (mode == IO_SEEK_SET) { assert(entity != NULL); /* TODO: can we do some basic limit checks on seek? */ ((file_state_t *)entity->info)->file_pos = offset; result = IO_SUCCESS; } else { result = IO_FAIL; } return result; } /* Read data from a file on the memmap device */ static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) { file_state_t *fp; assert(entity != NULL); assert(buffer != (uintptr_t)NULL); assert(length_read != NULL); fp = (file_state_t *)entity->info; memcpy((void *)buffer, (void *)(fp->base + fp->file_pos), length); *length_read = length; /* advance the file 'cursor' for incremental reads */ fp->file_pos += length; return IO_SUCCESS; } /* Write data to a file on the memmap device */ static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, size_t length, size_t *length_written) { file_state_t *fp; assert(entity != NULL); assert(buffer != (uintptr_t)NULL); assert(length_written != NULL); fp = (file_state_t *)entity->info; memcpy((void *)(fp->base + fp->file_pos), (void *)buffer, length); *length_written = length; /* advance the file 'cursor' for incremental writes */ fp->file_pos += length; return IO_SUCCESS; } /* Close a file on the memmap device */ static int memmap_block_close(io_entity_t *entity) { assert(entity != NULL); entity->info = 0; /* This would be a mem free() if we had malloc.*/ memset((void *)¤t_file, 0, sizeof(current_file)); return IO_SUCCESS; } /* Exported functions */ /* Register the memmap driver with the IO abstraction */ int register_io_dev_memmap(const io_dev_connector_t **dev_con) { int result = IO_FAIL; assert(dev_con != NULL); result = io_register_device(&memmap_dev_info); if (result == IO_SUCCESS) *dev_con = &memmap_dev_connector; return result; } arm-trusted-firmware-1.0-aw-6/drivers/io/io_semihosting.c000066400000000000000000000143071322600646200234620ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include /* Identify the device type as semihosting */ static io_type_t device_type_sh(void) { return IO_TYPE_SEMIHOSTING; } /* Semi-hosting functions, device info and handle */ static int sh_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); static int sh_file_open(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset); static int sh_file_len(io_entity_t *entity, size_t *length); static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); static int sh_file_write(io_entity_t *entity, const uintptr_t buffer, size_t length, size_t *length_written); static int sh_file_close(io_entity_t *entity); static const io_dev_connector_t sh_dev_connector = { .dev_open = sh_dev_open }; static const io_dev_funcs_t sh_dev_funcs = { .type = device_type_sh, .open = sh_file_open, .seek = sh_file_seek, .size = sh_file_len, .read = sh_file_read, .write = sh_file_write, .close = sh_file_close, .dev_init = NULL, /* NOP */ .dev_close = NULL, /* NOP */ }; /* No state associated with this device so structure can be const */ static const io_dev_info_t sh_dev_info = { .funcs = &sh_dev_funcs, .info = (uintptr_t)NULL }; /* Open a connection to the semi-hosting device */ static int sh_dev_open(const uintptr_t dev_spec __unused, io_dev_info_t **dev_info) { int result = IO_SUCCESS; assert(dev_info != NULL); *dev_info = (io_dev_info_t *)&sh_dev_info; /* cast away const */ return result; } /* Open a file on the semi-hosting device */ static int sh_file_open(io_dev_info_t *dev_info __attribute__((unused)), const uintptr_t spec, io_entity_t *entity) { int result = IO_FAIL; long sh_result = -1; const io_file_spec_t *file_spec = (const io_file_spec_t *)spec; assert(file_spec != NULL); assert(entity != NULL); sh_result = semihosting_file_open(file_spec->path, file_spec->mode); if (sh_result > 0) { entity->info = (uintptr_t)sh_result; result = IO_SUCCESS; } else { result = IO_FAIL; } return result; } /* Seek to a particular file offset on the semi-hosting device */ static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset) { int result = IO_FAIL; long file_handle, sh_result; assert(entity != NULL); file_handle = (long)entity->info; sh_result = semihosting_file_seek(file_handle, offset); result = (sh_result == 0) ? IO_SUCCESS : IO_FAIL; return result; } /* Return the size of a file on the semi-hosting device */ static int sh_file_len(io_entity_t *entity, size_t *length) { int result = IO_FAIL; assert(entity != NULL); assert(length != NULL); long sh_handle = (long)entity->info; long sh_result = semihosting_file_length(sh_handle); if (sh_result >= 0) { result = IO_SUCCESS; *length = (size_t)sh_result; } return result; } /* Read data from a file on the semi-hosting device */ static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read) { int result = IO_FAIL; long sh_result = -1; size_t bytes = length; long file_handle; assert(entity != NULL); assert(buffer != (uintptr_t)NULL); assert(length_read != NULL); file_handle = (long)entity->info; sh_result = semihosting_file_read(file_handle, &bytes, buffer); if (sh_result >= 0) { *length_read = (bytes != length) ? bytes : length; result = IO_SUCCESS; } else result = IO_FAIL; return result; } /* Write data to a file on the semi-hosting device */ static int sh_file_write(io_entity_t *entity, const uintptr_t buffer, size_t length, size_t *length_written) { int result = IO_FAIL; long sh_result = -1; long file_handle; size_t bytes = length; assert(entity != NULL); assert(buffer != (uintptr_t)NULL); assert(length_written != NULL); file_handle = (long)entity->info; sh_result = semihosting_file_write(file_handle, &bytes, buffer); if (sh_result >= 0) { *length_written = sh_result; result = IO_SUCCESS; } else result = IO_FAIL; return result; } /* Close a file on the semi-hosting device */ static int sh_file_close(io_entity_t *entity) { int result = IO_FAIL; long sh_result = -1; long file_handle; assert(entity != NULL); file_handle = (long)entity->info; sh_result = semihosting_file_close(file_handle); result = (sh_result >= 0) ? IO_SUCCESS : IO_FAIL; return result; } /* Exported functions */ /* Register the semi-hosting driver with the IO abstraction */ int register_io_dev_sh(const io_dev_connector_t **dev_con) { int result = IO_FAIL; assert(dev_con != NULL); result = io_register_device(&sh_dev_info); if (result == IO_SUCCESS) *dev_con = &sh_dev_connector; return result; } arm-trusted-firmware-1.0-aw-6/drivers/io/io_storage.c000066400000000000000000000222751322600646200226000ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include /* Storage for a fixed maximum number of IO entities, definable by platform */ static io_entity_t entity_pool[MAX_IO_HANDLES]; /* Simple way of tracking used storage - each entry is NULL or a pointer to an * entity */ static io_entity_t *entity_map[MAX_IO_HANDLES]; /* Track number of allocated entities */ static unsigned int entity_count; /* Array of fixed maximum of registered devices, definable by platform */ static const io_dev_info_t *devices[MAX_IO_DEVICES]; /* Number of currently registered devices */ static unsigned int dev_count; #if DEBUG /* Extra validation functions only used in debug builds */ /* Return a boolean value indicating whether a device connector is valid */ static int is_valid_dev_connector(const io_dev_connector_t *dev_con) { int result = (dev_con != NULL) && (dev_con->dev_open != NULL); return result; } /* Return a boolean value indicating whether a device handle is valid */ static int is_valid_dev(const uintptr_t dev_handle) { const io_dev_info_t *dev = (io_dev_info_t *)dev_handle; int result = (dev != NULL) && (dev->funcs != NULL) && (dev->funcs->type != NULL) && (dev->funcs->type() < IO_TYPE_MAX); return result; } /* Return a boolean value indicating whether an IO entity is valid */ static int is_valid_entity(const uintptr_t handle) { const io_entity_t *entity = (io_entity_t *)handle; int result = (entity != NULL) && (is_valid_dev((uintptr_t)entity->dev_handle)); return result; } /* Return a boolean value indicating whether a seek mode is valid */ static int is_valid_seek_mode(io_seek_mode_t mode) { return ((mode != IO_SEEK_INVALID) && (mode < IO_SEEK_MAX)); } #endif /* End of debug-only validation functions */ /* Open a connection to a specific device */ static int dev_open(const io_dev_connector_t *dev_con, const uintptr_t dev_spec, io_dev_info_t **dev_info) { int result = IO_FAIL; assert(dev_info != NULL); assert(is_valid_dev_connector(dev_con)); result = dev_con->dev_open(dev_spec, dev_info); return result; } /* Set a handle to track an entity */ static void set_handle(uintptr_t *handle, io_entity_t *entity) { assert(handle != NULL); *handle = (uintptr_t)entity; } /* Locate an entity in the pool, specified by address */ static int find_first_entity(const io_entity_t *entity, unsigned int *index_out) { int result = IO_FAIL; for (int index = 0; index < MAX_IO_HANDLES; ++index) { if (entity_map[index] == entity) { result = IO_SUCCESS; *index_out = index; break; } } return result; } /* Allocate an entity from the pool and return a pointer to it */ static int allocate_entity(io_entity_t **entity) { int result = IO_FAIL; assert(entity != NULL); if (entity_count < MAX_IO_HANDLES) { unsigned int index = 0; result = find_first_entity(NULL, &index); assert(result == IO_SUCCESS); *entity = entity_map[index] = &entity_pool[index]; ++entity_count; } else result = IO_RESOURCES_EXHAUSTED; return result; } /* Release an entity back to the pool */ static int free_entity(const io_entity_t *entity) { int result = IO_FAIL; unsigned int index = 0; assert(entity != NULL); result = find_first_entity(entity, &index); if (result == IO_SUCCESS) { entity_map[index] = NULL; --entity_count; } return result; } /* Exported API */ /* Register a device driver */ int io_register_device(const io_dev_info_t *dev_info) { int result = IO_FAIL; assert(dev_info != NULL); if (dev_count < MAX_IO_DEVICES) { devices[dev_count] = dev_info; dev_count++; result = IO_SUCCESS; } else { result = IO_RESOURCES_EXHAUSTED; } return result; } /* Open a connection to an IO device */ int io_dev_open(const io_dev_connector_t *dev_con, const uintptr_t dev_spec, uintptr_t *handle) { int result = IO_FAIL; assert(handle != NULL); result = dev_open(dev_con, dev_spec, (io_dev_info_t **)handle); return result; } /* Initialise an IO device explicitly - to permit lazy initialisation or * re-initialisation */ int io_dev_init(uintptr_t dev_handle, const uintptr_t init_params) { int result = IO_FAIL; assert(dev_handle != (uintptr_t)NULL); assert(is_valid_dev(dev_handle)); io_dev_info_t *dev = (io_dev_info_t *)dev_handle; if (dev->funcs->dev_init != NULL) { result = dev->funcs->dev_init(dev, init_params); } else { /* Absence of registered function implies NOP here */ result = IO_SUCCESS; } return result; } /* TODO: Consider whether an explicit "shutdown" API should be included */ /* Close a connection to a device */ int io_dev_close(uintptr_t dev_handle) { int result = IO_FAIL; assert(dev_handle != (uintptr_t)NULL); assert(is_valid_dev(dev_handle)); io_dev_info_t *dev = (io_dev_info_t *)dev_handle; if (dev->funcs->dev_close != NULL) { result = dev->funcs->dev_close(dev); } else { /* Absence of registered function implies NOP here */ result = IO_SUCCESS; } return result; } /* Synchronous operations */ /* Open an IO entity */ int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle) { int result = IO_FAIL; assert((spec != (uintptr_t)NULL) && (handle != NULL)); assert(is_valid_dev(dev_handle)); io_dev_info_t *dev = (io_dev_info_t *)dev_handle; io_entity_t *entity; result = allocate_entity(&entity); if (result == IO_SUCCESS) { assert(dev->funcs->open != NULL); result = dev->funcs->open(dev, spec, entity); if (result == IO_SUCCESS) { entity->dev_handle = dev; set_handle(handle, entity); } else free_entity(entity); } return result; } /* Seek to a specific position in an IO entity */ int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset) { int result = IO_FAIL; assert(is_valid_entity(handle) && is_valid_seek_mode(mode)); io_entity_t *entity = (io_entity_t *)handle; io_dev_info_t *dev = entity->dev_handle; if (dev->funcs->seek != NULL) result = dev->funcs->seek(entity, mode, offset); else result = IO_NOT_SUPPORTED; return result; } /* Determine the length of an IO entity */ int io_size(uintptr_t handle, size_t *length) { int result = IO_FAIL; assert(is_valid_entity(handle) && (length != NULL)); io_entity_t *entity = (io_entity_t *)handle; io_dev_info_t *dev = entity->dev_handle; if (dev->funcs->size != NULL) result = dev->funcs->size(entity, length); else result = IO_NOT_SUPPORTED; return result; } /* Read data from an IO entity */ int io_read(uintptr_t handle, uintptr_t buffer, size_t length, size_t *length_read) { int result = IO_FAIL; assert(is_valid_entity(handle) && (buffer != (uintptr_t)NULL)); io_entity_t *entity = (io_entity_t *)handle; io_dev_info_t *dev = entity->dev_handle; if (dev->funcs->read != NULL) result = dev->funcs->read(entity, buffer, length, length_read); else result = IO_NOT_SUPPORTED; return result; } /* Write data to an IO entity */ int io_write(uintptr_t handle, const uintptr_t buffer, size_t length, size_t *length_written) { int result = IO_FAIL; assert(is_valid_entity(handle) && (buffer != (uintptr_t)NULL)); io_entity_t *entity = (io_entity_t *)handle; io_dev_info_t *dev = entity->dev_handle; if (dev->funcs->write != NULL) { result = dev->funcs->write(entity, buffer, length, length_written); } else result = IO_NOT_SUPPORTED; return result; } /* Close an IO entity */ int io_close(uintptr_t handle) { int result = IO_FAIL; assert(is_valid_entity(handle)); io_entity_t *entity = (io_entity_t *)handle; io_dev_info_t *dev = entity->dev_handle; if (dev->funcs->close != NULL) result = dev->funcs->close(entity); else { /* Absence of registered function implies NOP here */ result = IO_SUCCESS; } /* Ignore improbable free_entity failure */ (void)free_entity(entity); return result; } arm-trusted-firmware-1.0-aw-6/fdts/000077500000000000000000000000001322600646200171445ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/fdts/fvp-base-gicv2-psci.dtb000066400000000000000000000235421322600646200233140ustar00rootroot00000000000000Ð þí'bH$(b#¸€ FVP Basearm,vfp-basearm,vexpress"1chosenaliases/=/smb/motherboard/iofpga@3,00000000/uart@090000/E/smb/motherboard/iofpga@3,00000000/uart@0a0000/M/smb/motherboard/iofpga@3,00000000/uart@0b0000/U/smb/motherboard/iofpga@3,00000000/uart@0c0000psci arm,psci]smcdÄp„xÄ„Œ„ cpus"1cpu-mapcluster0core0–core1–core2–core3–cluster1core0–core1–core2–core3– idle-states šarm,pscicpu-sleep-0arm,idle-state§º(ËdÛ–ì ò cluster-sleep-0arm,idle-state§ºôËèÛ Äì ò cpu@0úcpu arm,armv8 psci ìòcpu@1úcpu arm,armv8 psci ìòcpu@2úcpu arm,armv8 psci ìòcpu@3úcpu arm,armv8 psci ìòcpu@100úcpu arm,armv8 psci ìòcpu@101úcpu arm,armv8 psci ìòcpu@102úcpu arm,armv8 psci ìòcpu@103úcpu arm,armv8 psci ì ò memory@80000000úmemory €€€interrupt-controller@2f000000%arm,cortex-a15-gicarm,cortex-a9-gic("9@/, , ,ð  N ìòtimerarm,armv8-timer0N ÿÿ ÿ ÿYõátimer@2a810000arm,armv7-timer-mem*Yõá"1iframe@2a830000p N*ƒpmuarm,armv8-pmuv30N<=>?smb simple-bus"1xi ( }?´            !!""##$$%%&&''(())**motherboardžrs1arm,vexpress,v2m-p1simple-bus"1(iflash@0,00000000arm,vexpress-flashcfi-flash±vram@2,00000000arm,vexpress-vram €ethernet@2,02000000smsc,lan91c111 Nclk24mhz fixed-clock¼Yn6 Év2m:clk24mhzìòrefclk1mhz fixed-clock¼YB@Év2m:refclk1mhzì ò refclk32khz fixed-clock¼Y€Év2m:refclk32khzì ò iofpga@3,00000000arm,amba-bussimple-bus"1i sysreg@010000arm,vexpress-sysregÜììòsysctl@020000arm,sp810arm,primecell ø ÿrefclktimclkapb_pclk¼0Étimerclken0timerclken1timerclken2timerclken3ìòaaci@040000arm,pl041arm,primecellN ø ÿapb_pclkmmci@050000arm,pl180arm,primecellN    ·+øÿmclkapb_pclkkmi@060000arm,pl050arm,primecellN øÿKMIREFCLKapb_pclkkmi@070000arm,pl050arm,primecellN øÿKMIREFCLKapb_pclkuart@090000arm,pl011arm,primecell Nøÿuartclkapb_pclkuart@0a0000arm,pl011arm,primecell Nøÿuartclkapb_pclkuart@0b0000arm,pl011arm,primecell Nøÿuartclkapb_pclkuart@0c0000arm,pl011arm,primecell Nøÿuartclkapb_pclkwdt@0f0000arm,sp805arm,primecellNø ÿwdogclkapb_pclktimer@110000arm,sp804arm,primecellNøÿtimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellNøÿtimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellNø ÿapb_pclkclcd@1f0000arm,pl111arm,primecellNøÿclcdclkapb_pclk7XVGA<Dvirtio_block@0130000 virtio,mmioN*fixedregulator@0regulator-fixedP3V3_2Z w2Z ìòmcc#arm,vexpress,config-bussimple-bus£osc@1arm,vexpress-osc¾×jepÈî༠Év2m:oscclk1ìòmuxfpga@0arm,vexpress-muxfpga¾dvimode@0arm,vexpress-dvimode¾ panelspanel@0panel7XVGAâ<êïô=„ý˜ 0#0h:DIFB_VMODE_NONINTERLACEDOTIM2_BCDTIM2_IPC&TCNTL_LCDTFTCNTL_BGRCNTL_LCDVCOMP(1)(YCLCD_CAP_5551CLCD_CAP_565CLCD_CAP_888^ modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3methodcpu_suspendcpu_offcpu_onsys_poweroffsys_resetcpuentry-methodentry-method-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandledevice_typeregenable-methodcpu-idle-states#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyrangesframe-numberinterrupt-map-maskinterrupt-maparm,v2m-memory-mapbank-width#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namescd-gpioswp-gpiosmax-frequencyvmmc-supplymodeuse_dmaframebufferregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-rangerefreshxresyrespixclockleft_marginright_marginupper_marginlower_marginhsync_lenvsync_lensyncvmodetim2cntlcapsbpparm-trusted-firmware-1.0-aw-6/fdts/fvp-base-gicv2-psci.dts000066400000000000000000000166011322600646200233330ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /dts-v1/; /memreserve/ 0x80000000 0x00010000; / { }; / { model = "FVP Base"; compatible = "arm,vfp-base", "arm,vexpress"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; chosen { }; aliases { serial0 = &v2m_serial0; serial1 = &v2m_serial1; serial2 = &v2m_serial2; serial3 = &v2m_serial3; }; psci { compatible = "arm,psci"; method = "smc"; cpu_suspend = <0xc4000001>; cpu_off = <0x84000002>; cpu_on = <0xc4000003>; sys_poweroff = <0x84000008>; sys_reset = <0x84000009>; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; cluster1 { core0 { cpu = <&CPU4>; }; core1 { cpu = <&CPU5>; }; core2 { cpu = <&CPU6>; }; core3 { cpu = <&CPU7>; }; }; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x0010000>; entry-latency-us = <40>; exit-latency-us = <100>; min-residency-us = <150>; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x1010000>; entry-latency-us = <500>; exit-latency-us = <1000>; min-residency-us = <2500>; }; }; CPU0:cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1:cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2:cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3:cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU4:cpu@100 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU5:cpu@101 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU6:cpu@102 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU7:cpu@103 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; }; memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x7F000000>, <0x00000008 0x80000000 0 0x80000000>; }; gic: interrupt-controller@2f000000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0x2f000000 0 0x10000>, <0x0 0x2c000000 0 0x2000>, <0x0 0x2c010000 0 0x2000>, <0x0 0x2c02F000 0 0x2000>; interrupts = <1 9 0xf04>; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; clock-frequency = <100000000>; }; timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; clock-frequency = <100000000>; #address-cells = <2>; #size-cells = <2>; ranges; frame@2a830000 { frame-number = <1>; interrupts = <0 26 4>; reg = <0x0 0x2a830000 0x0 0x10000>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 60 4>, <0 61 4>, <0 62 4>, <0 63 4>; }; smb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0x08000000 0x04000000>, <1 0 0 0x14000000 0x04000000>, <2 0 0 0x18000000 0x04000000>, <3 0 0 0x1c000000 0x04000000>, <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic 0 0 4>, <0 0 1 &gic 0 1 4>, <0 0 2 &gic 0 2 4>, <0 0 3 &gic 0 3 4>, <0 0 4 &gic 0 4 4>, <0 0 5 &gic 0 5 4>, <0 0 6 &gic 0 6 4>, <0 0 7 &gic 0 7 4>, <0 0 8 &gic 0 8 4>, <0 0 9 &gic 0 9 4>, <0 0 10 &gic 0 10 4>, <0 0 11 &gic 0 11 4>, <0 0 12 &gic 0 12 4>, <0 0 13 &gic 0 13 4>, <0 0 14 &gic 0 14 4>, <0 0 15 &gic 0 15 4>, <0 0 16 &gic 0 16 4>, <0 0 17 &gic 0 17 4>, <0 0 18 &gic 0 18 4>, <0 0 19 &gic 0 19 4>, <0 0 20 &gic 0 20 4>, <0 0 21 &gic 0 21 4>, <0 0 22 &gic 0 22 4>, <0 0 23 &gic 0 23 4>, <0 0 24 &gic 0 24 4>, <0 0 25 &gic 0 25 4>, <0 0 26 &gic 0 26 4>, <0 0 27 &gic 0 27 4>, <0 0 28 &gic 0 28 4>, <0 0 29 &gic 0 29 4>, <0 0 30 &gic 0 30 4>, <0 0 31 &gic 0 31 4>, <0 0 32 &gic 0 32 4>, <0 0 33 &gic 0 33 4>, <0 0 34 &gic 0 34 4>, <0 0 35 &gic 0 35 4>, <0 0 36 &gic 0 36 4>, <0 0 37 &gic 0 37 4>, <0 0 38 &gic 0 38 4>, <0 0 39 &gic 0 39 4>, <0 0 40 &gic 0 40 4>, <0 0 41 &gic 0 41 4>, <0 0 42 &gic 0 42 4>; /include/ "rtsm_ve-motherboard.dtsi" }; panels { panel@0 { compatible = "panel"; mode = "XVGA"; refresh = <60>; xres = <1024>; yres = <768>; pixclock = <15748>; left_margin = <152>; right_margin = <48>; upper_margin = <23>; lower_margin = <3>; hsync_len = <104>; vsync_len = <4>; sync = <0>; vmode = "FB_VMODE_NONINTERLACED"; tim2 = "TIM2_BCD", "TIM2_IPC"; cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; bpp = <16>; }; }; }; arm-trusted-firmware-1.0-aw-6/fdts/fvp-base-gicv2legacy-psci.dtb000066400000000000000000000235421322600646200245010ustar00rootroot00000000000000Ð þí'bH$(b#¸€ FVP Basearm,vfp-basearm,vexpress"1chosenaliases/=/smb/motherboard/iofpga@3,00000000/uart@090000/E/smb/motherboard/iofpga@3,00000000/uart@0a0000/M/smb/motherboard/iofpga@3,00000000/uart@0b0000/U/smb/motherboard/iofpga@3,00000000/uart@0c0000psci arm,psci]smcdÄp„xÄ„Œ„ cpus"1cpu-mapcluster0core0–core1–core2–core3–cluster1core0–core1–core2–core3– idle-states šarm,pscicpu-sleep-0arm,idle-state§º(ËdÛ–ì ò cluster-sleep-0arm,idle-state§ºôËèÛ Äì ò cpu@0úcpu arm,armv8 psci ìòcpu@1úcpu arm,armv8 psci ìòcpu@2úcpu arm,armv8 psci ìòcpu@3úcpu arm,armv8 psci ìòcpu@100úcpu arm,armv8 psci ìòcpu@101úcpu arm,armv8 psci ìòcpu@102úcpu arm,armv8 psci ìòcpu@103úcpu arm,armv8 psci ì ò memory@80000000úmemory €€€interrupt-controller@2c001000%arm,cortex-a15-gicarm,cortex-a9-gic("9@,, ,@ ,`  N ìòtimerarm,armv8-timer0N ÿÿ ÿ ÿYõátimer@2a810000arm,armv7-timer-mem*Yõá"1iframe@2a830000p N*ƒpmuarm,armv8-pmuv30N<=>?smb simple-bus"1xi ( }?´            !!""##$$%%&&''(())**motherboardžrs1arm,vexpress,v2m-p1simple-bus"1(iflash@0,00000000arm,vexpress-flashcfi-flash±vram@2,00000000arm,vexpress-vram €ethernet@2,02000000smsc,lan91c111 Nclk24mhz fixed-clock¼Yn6 Év2m:clk24mhzìòrefclk1mhz fixed-clock¼YB@Év2m:refclk1mhzì ò refclk32khz fixed-clock¼Y€Év2m:refclk32khzì ò iofpga@3,00000000arm,amba-bussimple-bus"1i sysreg@010000arm,vexpress-sysregÜììòsysctl@020000arm,sp810arm,primecell ø ÿrefclktimclkapb_pclk¼0Étimerclken0timerclken1timerclken2timerclken3ìòaaci@040000arm,pl041arm,primecellN ø ÿapb_pclkmmci@050000arm,pl180arm,primecellN    ·+øÿmclkapb_pclkkmi@060000arm,pl050arm,primecellN øÿKMIREFCLKapb_pclkkmi@070000arm,pl050arm,primecellN øÿKMIREFCLKapb_pclkuart@090000arm,pl011arm,primecell Nøÿuartclkapb_pclkuart@0a0000arm,pl011arm,primecell Nøÿuartclkapb_pclkuart@0b0000arm,pl011arm,primecell Nøÿuartclkapb_pclkuart@0c0000arm,pl011arm,primecell Nøÿuartclkapb_pclkwdt@0f0000arm,sp805arm,primecellNø ÿwdogclkapb_pclktimer@110000arm,sp804arm,primecellNøÿtimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellNøÿtimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellNø ÿapb_pclkclcd@1f0000arm,pl111arm,primecellNøÿclcdclkapb_pclk7XVGA<Dvirtio_block@0130000 virtio,mmioN*fixedregulator@0regulator-fixedP3V3_2Z w2Z ìòmcc#arm,vexpress,config-bussimple-bus£osc@1arm,vexpress-osc¾×jepÈî༠Év2m:oscclk1ìòmuxfpga@0arm,vexpress-muxfpga¾dvimode@0arm,vexpress-dvimode¾ panelspanel@0panel7XVGAâ<êïô=„ý˜ 0#0h:DIFB_VMODE_NONINTERLACEDOTIM2_BCDTIM2_IPC&TCNTL_LCDTFTCNTL_BGRCNTL_LCDVCOMP(1)(YCLCD_CAP_5551CLCD_CAP_565CLCD_CAP_888^ modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3methodcpu_suspendcpu_offcpu_onsys_poweroffsys_resetcpuentry-methodentry-method-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandledevice_typeregenable-methodcpu-idle-states#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyrangesframe-numberinterrupt-map-maskinterrupt-maparm,v2m-memory-mapbank-width#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namescd-gpioswp-gpiosmax-frequencyvmmc-supplymodeuse_dmaframebufferregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-rangerefreshxresyrespixclockleft_marginright_marginupper_marginlower_marginhsync_lenvsync_lensyncvmodetim2cntlcapsbpparm-trusted-firmware-1.0-aw-6/fdts/fvp-base-gicv2legacy-psci.dts000066400000000000000000000166001322600646200245170ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /dts-v1/; /memreserve/ 0x80000000 0x00010000; / { }; / { model = "FVP Base"; compatible = "arm,vfp-base", "arm,vexpress"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; chosen { }; aliases { serial0 = &v2m_serial0; serial1 = &v2m_serial1; serial2 = &v2m_serial2; serial3 = &v2m_serial3; }; psci { compatible = "arm,psci"; method = "smc"; cpu_suspend = <0xc4000001>; cpu_off = <0x84000002>; cpu_on = <0xc4000003>; sys_poweroff = <0x84000008>; sys_reset = <0x84000009>; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; cluster1 { core0 { cpu = <&CPU4>; }; core1 { cpu = <&CPU5>; }; core2 { cpu = <&CPU6>; }; core3 { cpu = <&CPU7>; }; }; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x0010000>; entry-latency-us = <40>; exit-latency-us = <100>; min-residency-us = <150>; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x1010000>; entry-latency-us = <500>; exit-latency-us = <1000>; min-residency-us = <2500>; }; }; CPU0:cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1:cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2:cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3:cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU4:cpu@100 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU5:cpu@101 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU6:cpu@102 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU7:cpu@103 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; }; memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x7F000000>, <0x00000008 0x80000000 0 0x80000000>; }; gic: interrupt-controller@2c001000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0x2c001000 0 0x1000>, <0x0 0x2c002000 0 0x1000>, <0x0 0x2c004000 0 0x2000>, <0x0 0x2c006000 0 0x2000>; interrupts = <1 9 0xf04>; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; clock-frequency = <100000000>; }; timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; clock-frequency = <100000000>; #address-cells = <2>; #size-cells = <2>; ranges; frame@2a830000 { frame-number = <1>; interrupts = <0 26 4>; reg = <0x0 0x2a830000 0x0 0x10000>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 60 4>, <0 61 4>, <0 62 4>, <0 63 4>; }; smb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0x08000000 0x04000000>, <1 0 0 0x14000000 0x04000000>, <2 0 0 0x18000000 0x04000000>, <3 0 0 0x1c000000 0x04000000>, <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic 0 0 4>, <0 0 1 &gic 0 1 4>, <0 0 2 &gic 0 2 4>, <0 0 3 &gic 0 3 4>, <0 0 4 &gic 0 4 4>, <0 0 5 &gic 0 5 4>, <0 0 6 &gic 0 6 4>, <0 0 7 &gic 0 7 4>, <0 0 8 &gic 0 8 4>, <0 0 9 &gic 0 9 4>, <0 0 10 &gic 0 10 4>, <0 0 11 &gic 0 11 4>, <0 0 12 &gic 0 12 4>, <0 0 13 &gic 0 13 4>, <0 0 14 &gic 0 14 4>, <0 0 15 &gic 0 15 4>, <0 0 16 &gic 0 16 4>, <0 0 17 &gic 0 17 4>, <0 0 18 &gic 0 18 4>, <0 0 19 &gic 0 19 4>, <0 0 20 &gic 0 20 4>, <0 0 21 &gic 0 21 4>, <0 0 22 &gic 0 22 4>, <0 0 23 &gic 0 23 4>, <0 0 24 &gic 0 24 4>, <0 0 25 &gic 0 25 4>, <0 0 26 &gic 0 26 4>, <0 0 27 &gic 0 27 4>, <0 0 28 &gic 0 28 4>, <0 0 29 &gic 0 29 4>, <0 0 30 &gic 0 30 4>, <0 0 31 &gic 0 31 4>, <0 0 32 &gic 0 32 4>, <0 0 33 &gic 0 33 4>, <0 0 34 &gic 0 34 4>, <0 0 35 &gic 0 35 4>, <0 0 36 &gic 0 36 4>, <0 0 37 &gic 0 37 4>, <0 0 38 &gic 0 38 4>, <0 0 39 &gic 0 39 4>, <0 0 40 &gic 0 40 4>, <0 0 41 &gic 0 41 4>, <0 0 42 &gic 0 42 4>; /include/ "rtsm_ve-motherboard.dtsi" }; panels { panel@0 { compatible = "panel"; mode = "XVGA"; refresh = <60>; xres = <1024>; yres = <768>; pixclock = <15748>; left_margin = <152>; right_margin = <48>; upper_margin = <23>; lower_margin = <3>; hsync_len = <104>; vsync_len = <4>; sync = <0>; vmode = "FB_VMODE_NONINTERLACED"; tim2 = "TIM2_BCD", "TIM2_IPC"; cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; bpp = <16>; }; }; }; arm-trusted-firmware-1.0-aw-6/fdts/fvp-base-gicv3-psci.dtb000066400000000000000000000247261322600646200233220ustar00rootroot00000000000000Ð þí)ÖH&|(Z&4€ FVP Basearm,vfp-basearm,vexpress"1chosenaliases/=/smb/motherboard/iofpga@3,00000000/uart@090000/E/smb/motherboard/iofpga@3,00000000/uart@0a0000/M/smb/motherboard/iofpga@3,00000000/uart@0b0000/U/smb/motherboard/iofpga@3,00000000/uart@0c0000psci arm,psci]smcdÄp„xÄcpus"1cpu-mapcluster0core0core1core2core3cluster1core0core1core2core3 idle-states ƒarm,pscicpu-sleep-0arm,idle-state£(´dÄ–Õ Û cluster-sleep-0arm,idle-state£ô´èÄ ÄÕ Û cpu@0ãcpu arm,armv8ïópsci ÕÛcpu@1ãcpu arm,armv8ïópsci ÕÛcpu@2ãcpu arm,armv8ïópsci ÕÛcpu@3ãcpu arm,armv8ïópsci ÕÛcpu@100ãcpu arm,armv8ïópsci ÕÛcpu@101ãcpu arm,armv8ïópsci ÕÛcpu@102ãcpu arm,armv8ïópsci ÕÛcpu@103ãcpu arm,armv8ïópsci Õ Û memory@80000000ãmemory €interrupt-controller@2f000000 arm,gic-v3"1")Pï// , , ,ð  > ÕÛits@2f020000arm,gic-v3-itsIï/timerarm,armv8-timer0> ÿÿ ÿ ÿXõátimer@2a810000arm,armv7-timer-memï*Xõá"1"frame@2a830000h >ï*ƒpmuarm,armv8-pmuv30><=>?smb simple-bus"1x"  u? ˆ            !!""##$$%%&&''(())**motherboard–rs1arm,vexpress,v2m-p1simple-bus"1"flash@0,00000000arm,vexpress-flashcfi-flashï©vram@2,00000000arm,vexpress-vram ï€ethernet@2,02000000smsc,lan91c111 ï>clk24mhz fixed-clock´Xn6 Áv2m:clk24mhzÕÛrefclk1mhz fixed-clock´XB@Áv2m:refclk1mhzÕ Û refclk32khz fixed-clock´X€Áv2m:refclk32khzÕ Û iofpga@3,00000000arm,amba-bussimple-bus"1" sysreg@010000arm,vexpress-sysregïÔäÕÛsysctl@020000arm,sp810arm,primecellï ð ÷refclktimclkapb_pclk´0Átimerclken0timerclken1timerclken2timerclken3ÕÛaaci@040000arm,pl041arm,primecellï> ð ÷apb_pclkmmci@050000arm,pl180arm,primecellï>    ·#ð÷mclkapb_pclkkmi@060000arm,pl050arm,primecellï> ð÷KMIREFCLKapb_pclkkmi@070000arm,pl050arm,primecellï> ð÷KMIREFCLKapb_pclkuart@090000arm,pl011arm,primecellï >ð÷uartclkapb_pclkuart@0a0000arm,pl011arm,primecellï >ð÷uartclkapb_pclkuart@0b0000arm,pl011arm,primecellï >ð÷uartclkapb_pclkuart@0c0000arm,pl011arm,primecellï >ð÷uartclkapb_pclkwdt@0f0000arm,sp805arm,primecellï>ð ÷wdogclkapb_pclktimer@110000arm,sp804arm,primecellï>ð÷timclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellï>ð÷timclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellï>ð ÷apb_pclkclcd@1f0000arm,pl111arm,primecellï>ð÷clcdclkapb_pclk/XVGA4<virtio_block@0130000 virtio,mmioï>*fixedregulator@0regulator-fixedH3V3W2Z o2Z ‡ÕÛmcc#arm,vexpress,config-bussimple-bus›osc@1arm,vexpress-osc¶ÏjepÈîà´ Áv2m:oscclk1ÕÛreset@0arm,vexpress-reset¶muxfpga@0arm,vexpress-muxfpga¶shutdown@0arm,vexpress-shutdown¶reboot@0arm,vexpress-reboot¶ dvimode@0arm,vexpress-dvimode¶ panelspanel@0panel/XVGAÚ<âçì=„õ˜0(h2<AFB_VMODE_NONINTERLACEDGTIM2_BCDTIM2_IPC&LCNTL_LCDTFTCNTL_BGRCNTL_LCDVCOMP(1)(QCLCD_CAP_5551CLCD_CAP_565CLCD_CAP_888V modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3methodcpu_suspendcpu_offcpu_oncpuentry-methodentry-method-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandledevice_typeregenable-methodcpu-idle-states#interrupt-cellsrangesinterrupt-controllerinterruptsmsi-controllerclock-frequencyframe-numberinterrupt-map-maskinterrupt-maparm,v2m-memory-mapbank-width#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namescd-gpioswp-gpiosmax-frequencyvmmc-supplymodeuse_dmaframebufferregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcfreq-rangerefreshxresyrespixclockleft_marginright_marginupper_marginlower_marginhsync_lenvsync_lensyncvmodetim2cntlcapsbpparm-trusted-firmware-1.0-aw-6/fdts/fvp-base-gicv3-psci.dts000066400000000000000000000173051322600646200233360ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /dts-v1/; /memreserve/ 0x80000000 0x00010000; / { }; / { model = "FVP Base"; compatible = "arm,vfp-base", "arm,vexpress"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; chosen { }; aliases { serial0 = &v2m_serial0; serial1 = &v2m_serial1; serial2 = &v2m_serial2; serial3 = &v2m_serial3; }; psci { compatible = "arm,psci"; method = "smc"; cpu_suspend = <0xc4000001>; cpu_off = <0x84000002>; cpu_on = <0xc4000003>; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; cluster1 { core0 { cpu = <&CPU4>; }; core1 { cpu = <&CPU5>; }; core2 { cpu = <&CPU6>; }; core3 { cpu = <&CPU7>; }; }; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x0010000>; entry-latency-us = <40>; exit-latency-us = <100>; min-residency-us = <150>; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x1010000>; entry-latency-us = <500>; exit-latency-us = <1000>; min-residency-us = <2500>; }; }; CPU0:cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1:cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2:cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3:cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU4:cpu@100 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU5:cpu@101 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU6:cpu@102 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU7:cpu@103 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; }; memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x7F000000>, <0x00000008 0x80000000 0 0x80000000>; }; gic: interrupt-controller@2f000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-controller; reg = <0x0 0x2f000000 0 0x10000>, // GICD <0x0 0x2f100000 0 0x200000>, // GICR <0x0 0x2c000000 0 0x2000>, // GICC <0x0 0x2c010000 0 0x2000>, // GICH <0x0 0x2c02f000 0 0x2000>; // GICV interrupts = <1 9 4>; its: its@2f020000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0x2f020000 0x0 0x20000>; // GITS }; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; clock-frequency = <100000000>; }; timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; clock-frequency = <100000000>; #address-cells = <2>; #size-cells = <2>; ranges; frame@2a830000 { frame-number = <1>; interrupts = <0 26 4>; reg = <0x0 0x2a830000 0x0 0x10000>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 60 4>, <0 61 4>, <0 62 4>, <0 63 4>; }; smb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0x08000000 0x04000000>, <1 0 0 0x14000000 0x04000000>, <2 0 0 0x18000000 0x04000000>, <3 0 0 0x1c000000 0x04000000>, <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic 0 0 0 0 4>, <0 0 1 &gic 0 0 0 1 4>, <0 0 2 &gic 0 0 0 2 4>, <0 0 3 &gic 0 0 0 3 4>, <0 0 4 &gic 0 0 0 4 4>, <0 0 5 &gic 0 0 0 5 4>, <0 0 6 &gic 0 0 0 6 4>, <0 0 7 &gic 0 0 0 7 4>, <0 0 8 &gic 0 0 0 8 4>, <0 0 9 &gic 0 0 0 9 4>, <0 0 10 &gic 0 0 0 10 4>, <0 0 11 &gic 0 0 0 11 4>, <0 0 12 &gic 0 0 0 12 4>, <0 0 13 &gic 0 0 0 13 4>, <0 0 14 &gic 0 0 0 14 4>, <0 0 15 &gic 0 0 0 15 4>, <0 0 16 &gic 0 0 0 16 4>, <0 0 17 &gic 0 0 0 17 4>, <0 0 18 &gic 0 0 0 18 4>, <0 0 19 &gic 0 0 0 19 4>, <0 0 20 &gic 0 0 0 20 4>, <0 0 21 &gic 0 0 0 21 4>, <0 0 22 &gic 0 0 0 22 4>, <0 0 23 &gic 0 0 0 23 4>, <0 0 24 &gic 0 0 0 24 4>, <0 0 25 &gic 0 0 0 25 4>, <0 0 26 &gic 0 0 0 26 4>, <0 0 27 &gic 0 0 0 27 4>, <0 0 28 &gic 0 0 0 28 4>, <0 0 29 &gic 0 0 0 29 4>, <0 0 30 &gic 0 0 0 30 4>, <0 0 31 &gic 0 0 0 31 4>, <0 0 32 &gic 0 0 0 32 4>, <0 0 33 &gic 0 0 0 33 4>, <0 0 34 &gic 0 0 0 34 4>, <0 0 35 &gic 0 0 0 35 4>, <0 0 36 &gic 0 0 0 36 4>, <0 0 37 &gic 0 0 0 37 4>, <0 0 38 &gic 0 0 0 38 4>, <0 0 39 &gic 0 0 0 39 4>, <0 0 40 &gic 0 0 0 40 4>, <0 0 41 &gic 0 0 0 41 4>, <0 0 42 &gic 0 0 0 42 4>; /include/ "rtsm_ve-motherboard-no_psci.dtsi" }; panels { panel@0 { compatible = "panel"; mode = "XVGA"; refresh = <60>; xres = <1024>; yres = <768>; pixclock = <15748>; left_margin = <152>; right_margin = <48>; upper_margin = <23>; lower_margin = <3>; hsync_len = <104>; vsync_len = <4>; sync = <0>; vmode = "FB_VMODE_NONINTERLACED"; tim2 = "TIM2_BCD", "TIM2_IPC"; cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; bpp = <16>; }; }; }; arm-trusted-firmware-1.0-aw-6/fdts/fvp-foundation-gicv2-psci.dtb000066400000000000000000000164331322600646200245510ustar00rootroot00000000000000Ð þíH”(‡L€FVP Foundationarm,fvp-basearm,vexpress"1chosenaliases/=/smb/motherboard/iofpga@3,00000000/uart@090000/E/smb/motherboard/iofpga@3,00000000/uart@0a0000/M/smb/motherboard/iofpga@3,00000000/uart@0b0000/U/smb/motherboard/iofpga@3,00000000/uart@0c0000psci arm,psci]smcdÄp„xÄ„Œ„ cpus"1cpu-mapcluster0core0–core1–core2–core3–idle-states šarm,pscicpu-sleep-0arm,idle-state§º(ËdÛ–ìòcluster-sleep-0arm,idle-state§ºôËèÛ Äìòcpu@0úcpu arm,armv8 psciìòcpu@1úcpu arm,armv8 psciìòcpu@2úcpu arm,armv8 psciìòcpu@3úcpu arm,armv8 psciìòmemory@80000000úmemory €€€interrupt-controller@2f000000%arm,cortex-a15-gicarm,cortex-a9-gic("9@/, , ,ð  N ìòtimerarm,armv8-timer0N ÿÿ ÿ ÿYõátimer@2a810000arm,armv7-timer-mem*Yõá"1iframe@2a830000p N*ƒpmuarm,armv8-pmuv30N<=>?smb simple-bus"1xi ( }?´            !!""##$$%%&&''(())**motherboardžrs1arm,vexpress,v2m-p1simple-bus"1(iethernet@2,02000000smsc,lan91c111 Nclk24mhz fixed-clock±Yn6 ¾v2m:clk24mhzì ò refclk1mhz fixed-clock±YB@¾v2m:refclk1mhzì ò refclk32khz fixed-clock±Y€¾v2m:refclk32khzìòiofpga@3,00000000arm,amba-bussimple-bus"1i sysreg@010000arm,vexpress-sysregÑáì ò sysctl@020000arm,sp810arm,primecell í ôrefclktimclkapb_pclk±0¾timerclken0timerclken1timerclken2timerclken3ì ò uart@090000arm,pl011arm,primecell Ní ôuartclkapb_pclkuart@0a0000arm,pl011arm,primecell Ní ôuartclkapb_pclkuart@0b0000arm,pl011arm,primecell Ní ôuartclkapb_pclkuart@0c0000arm,pl011arm,primecell Ní ôuartclkapb_pclkwdt@0f0000arm,sp805arm,primecellNí ôwdogclkapb_pclktimer@110000arm,sp804arm,primecellNí  ôtimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellNí   ôtimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellNí  ôapb_pclkvirtio_block@0130000 virtio,mmioN*fixedregulator@0regulator-fixed3V32Z '2Z ?mcc#arm,vexpress,config-bussimple-busS muxfpga@0arm,vexpress-muxfpgandvimode@0arm,vexpress-dvimoden  modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3methodcpu_suspendcpu_offcpu_onsys_poweroffsys_resetcpuentry-methodentry-method-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandledevice_typeregenable-methodcpu-idle-states#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyrangesframe-numberinterrupt-map-maskinterrupt-maparm,v2m-memory-map#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcarm-trusted-firmware-1.0-aw-6/fdts/fvp-foundation-gicv2-psci.dts000066400000000000000000000140211322600646200245610ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of the ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /dts-v1/; /memreserve/ 0x80000000 0x00010000; / { }; / { model = "FVP Foundation"; compatible = "arm,fvp-base", "arm,vexpress"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; chosen { }; aliases { serial0 = &v2m_serial0; serial1 = &v2m_serial1; serial2 = &v2m_serial2; serial3 = &v2m_serial3; }; psci { compatible = "arm,psci"; method = "smc"; cpu_suspend = <0xc4000001>; cpu_off = <0x84000002>; cpu_on = <0xc4000003>; sys_poweroff = <0x84000008>; sys_reset = <0x84000009>; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x0010000>; entry-latency-us = <40>; exit-latency-us = <100>; min-residency-us = <150>; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x1010000>; entry-latency-us = <500>; exit-latency-us = <1000>; min-residency-us = <2500>; }; }; CPU0:cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1:cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2:cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3:cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; }; memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x7F000000>, <0x00000008 0x80000000 0 0x80000000>; }; gic: interrupt-controller@2f000000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0x2f000000 0 0x10000>, <0x0 0x2c000000 0 0x2000>, <0x0 0x2c010000 0 0x2000>, <0x0 0x2c02F000 0 0x2000>; interrupts = <1 9 0xf04>; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; clock-frequency = <100000000>; }; timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; clock-frequency = <100000000>; #address-cells = <2>; #size-cells = <2>; ranges; frame@2a830000 { frame-number = <1>; interrupts = <0 26 4>; reg = <0x0 0x2a830000 0x0 0x10000>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 60 4>, <0 61 4>, <0 62 4>, <0 63 4>; }; smb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0x08000000 0x04000000>, <1 0 0 0x14000000 0x04000000>, <2 0 0 0x18000000 0x04000000>, <3 0 0 0x1c000000 0x04000000>, <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic 0 0 4>, <0 0 1 &gic 0 1 4>, <0 0 2 &gic 0 2 4>, <0 0 3 &gic 0 3 4>, <0 0 4 &gic 0 4 4>, <0 0 5 &gic 0 5 4>, <0 0 6 &gic 0 6 4>, <0 0 7 &gic 0 7 4>, <0 0 8 &gic 0 8 4>, <0 0 9 &gic 0 9 4>, <0 0 10 &gic 0 10 4>, <0 0 11 &gic 0 11 4>, <0 0 12 &gic 0 12 4>, <0 0 13 &gic 0 13 4>, <0 0 14 &gic 0 14 4>, <0 0 15 &gic 0 15 4>, <0 0 16 &gic 0 16 4>, <0 0 17 &gic 0 17 4>, <0 0 18 &gic 0 18 4>, <0 0 19 &gic 0 19 4>, <0 0 20 &gic 0 20 4>, <0 0 21 &gic 0 21 4>, <0 0 22 &gic 0 22 4>, <0 0 23 &gic 0 23 4>, <0 0 24 &gic 0 24 4>, <0 0 25 &gic 0 25 4>, <0 0 26 &gic 0 26 4>, <0 0 27 &gic 0 27 4>, <0 0 28 &gic 0 28 4>, <0 0 29 &gic 0 29 4>, <0 0 30 &gic 0 30 4>, <0 0 31 &gic 0 31 4>, <0 0 32 &gic 0 32 4>, <0 0 33 &gic 0 33 4>, <0 0 34 &gic 0 34 4>, <0 0 35 &gic 0 35 4>, <0 0 36 &gic 0 36 4>, <0 0 37 &gic 0 37 4>, <0 0 38 &gic 0 38 4>, <0 0 39 &gic 0 39 4>, <0 0 40 &gic 0 40 4>, <0 0 41 &gic 0 41 4>, <0 0 42 &gic 0 42 4>; /include/ "fvp-foundation-motherboard.dtsi" }; }; arm-trusted-firmware-1.0-aw-6/fdts/fvp-foundation-gicv2legacy-psci.dtb000066400000000000000000000164331322600646200257360ustar00rootroot00000000000000Ð þíH”(‡L€FVP Foundationarm,fvp-basearm,vexpress"1chosenaliases/=/smb/motherboard/iofpga@3,00000000/uart@090000/E/smb/motherboard/iofpga@3,00000000/uart@0a0000/M/smb/motherboard/iofpga@3,00000000/uart@0b0000/U/smb/motherboard/iofpga@3,00000000/uart@0c0000psci arm,psci]smcdÄp„xÄ„Œ„ cpus"1cpu-mapcluster0core0–core1–core2–core3–idle-states šarm,pscicpu-sleep-0arm,idle-state§º(ËdÛ–ìòcluster-sleep-0arm,idle-state§ºôËèÛ Äìòcpu@0úcpu arm,armv8 psciìòcpu@1úcpu arm,armv8 psciìòcpu@2úcpu arm,armv8 psciìòcpu@3úcpu arm,armv8 psciìòmemory@80000000úmemory €€€interrupt-controller@2c001000%arm,cortex-a15-gicarm,cortex-a9-gic("9@,, ,@ ,`  N ìòtimerarm,armv8-timer0N ÿÿ ÿ ÿYõátimer@2a810000arm,armv7-timer-mem*Yõá"1iframe@2a830000p N*ƒpmuarm,armv8-pmuv30N<=>?smb simple-bus"1xi ( }?´            !!""##$$%%&&''(())**motherboardžrs1arm,vexpress,v2m-p1simple-bus"1(iethernet@2,02000000smsc,lan91c111 Nclk24mhz fixed-clock±Yn6 ¾v2m:clk24mhzì ò refclk1mhz fixed-clock±YB@¾v2m:refclk1mhzì ò refclk32khz fixed-clock±Y€¾v2m:refclk32khzìòiofpga@3,00000000arm,amba-bussimple-bus"1i sysreg@010000arm,vexpress-sysregÑáì ò sysctl@020000arm,sp810arm,primecell í ôrefclktimclkapb_pclk±0¾timerclken0timerclken1timerclken2timerclken3ì ò uart@090000arm,pl011arm,primecell Ní ôuartclkapb_pclkuart@0a0000arm,pl011arm,primecell Ní ôuartclkapb_pclkuart@0b0000arm,pl011arm,primecell Ní ôuartclkapb_pclkuart@0c0000arm,pl011arm,primecell Ní ôuartclkapb_pclkwdt@0f0000arm,sp805arm,primecellNí ôwdogclkapb_pclktimer@110000arm,sp804arm,primecellNí  ôtimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellNí   ôtimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellNí  ôapb_pclkvirtio_block@0130000 virtio,mmioN*fixedregulator@0regulator-fixed3V32Z '2Z ?mcc#arm,vexpress,config-bussimple-busS muxfpga@0arm,vexpress-muxfpgandvimode@0arm,vexpress-dvimoden  modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3methodcpu_suspendcpu_offcpu_onsys_poweroffsys_resetcpuentry-methodentry-method-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandledevice_typeregenable-methodcpu-idle-states#interrupt-cellsinterrupt-controllerinterruptsclock-frequencyrangesframe-numberinterrupt-map-maskinterrupt-maparm,v2m-memory-map#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcarm-trusted-firmware-1.0-aw-6/fdts/fvp-foundation-gicv2legacy-psci.dts000066400000000000000000000140201322600646200257450ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of the ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /dts-v1/; /memreserve/ 0x80000000 0x00010000; / { }; / { model = "FVP Foundation"; compatible = "arm,fvp-base", "arm,vexpress"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; chosen { }; aliases { serial0 = &v2m_serial0; serial1 = &v2m_serial1; serial2 = &v2m_serial2; serial3 = &v2m_serial3; }; psci { compatible = "arm,psci"; method = "smc"; cpu_suspend = <0xc4000001>; cpu_off = <0x84000002>; cpu_on = <0xc4000003>; sys_poweroff = <0x84000008>; sys_reset = <0x84000009>; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x0010000>; entry-latency-us = <40>; exit-latency-us = <100>; min-residency-us = <150>; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x1010000>; entry-latency-us = <500>; exit-latency-us = <1000>; min-residency-us = <2500>; }; }; CPU0:cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1:cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2:cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3:cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; }; memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x7F000000>, <0x00000008 0x80000000 0 0x80000000>; }; gic: interrupt-controller@2c001000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0x2c001000 0 0x1000>, <0x0 0x2c002000 0 0x1000>, <0x0 0x2c004000 0 0x2000>, <0x0 0x2c006000 0 0x2000>; interrupts = <1 9 0xf04>; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; clock-frequency = <100000000>; }; timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; clock-frequency = <100000000>; #address-cells = <2>; #size-cells = <2>; ranges; frame@2a830000 { frame-number = <1>; interrupts = <0 26 4>; reg = <0x0 0x2a830000 0x0 0x10000>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 60 4>, <0 61 4>, <0 62 4>, <0 63 4>; }; smb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0x08000000 0x04000000>, <1 0 0 0x14000000 0x04000000>, <2 0 0 0x18000000 0x04000000>, <3 0 0 0x1c000000 0x04000000>, <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic 0 0 4>, <0 0 1 &gic 0 1 4>, <0 0 2 &gic 0 2 4>, <0 0 3 &gic 0 3 4>, <0 0 4 &gic 0 4 4>, <0 0 5 &gic 0 5 4>, <0 0 6 &gic 0 6 4>, <0 0 7 &gic 0 7 4>, <0 0 8 &gic 0 8 4>, <0 0 9 &gic 0 9 4>, <0 0 10 &gic 0 10 4>, <0 0 11 &gic 0 11 4>, <0 0 12 &gic 0 12 4>, <0 0 13 &gic 0 13 4>, <0 0 14 &gic 0 14 4>, <0 0 15 &gic 0 15 4>, <0 0 16 &gic 0 16 4>, <0 0 17 &gic 0 17 4>, <0 0 18 &gic 0 18 4>, <0 0 19 &gic 0 19 4>, <0 0 20 &gic 0 20 4>, <0 0 21 &gic 0 21 4>, <0 0 22 &gic 0 22 4>, <0 0 23 &gic 0 23 4>, <0 0 24 &gic 0 24 4>, <0 0 25 &gic 0 25 4>, <0 0 26 &gic 0 26 4>, <0 0 27 &gic 0 27 4>, <0 0 28 &gic 0 28 4>, <0 0 29 &gic 0 29 4>, <0 0 30 &gic 0 30 4>, <0 0 31 &gic 0 31 4>, <0 0 32 &gic 0 32 4>, <0 0 33 &gic 0 33 4>, <0 0 34 &gic 0 34 4>, <0 0 35 &gic 0 35 4>, <0 0 36 &gic 0 36 4>, <0 0 37 &gic 0 37 4>, <0 0 38 &gic 0 38 4>, <0 0 39 &gic 0 39 4>, <0 0 40 &gic 0 40 4>, <0 0 41 &gic 0 41 4>, <0 0 42 &gic 0 42 4>; /include/ "fvp-foundation-motherboard.dtsi" }; }; arm-trusted-firmware-1.0-aw-6/fdts/fvp-foundation-gicv3-psci.dtb000066400000000000000000000176171322600646200245570ustar00rootroot00000000000000Ð þíH(È€FVP Foundationarm,fvp-basearm,vexpress"1chosenaliases/=/smb/motherboard/iofpga@3,00000000/uart@090000/E/smb/motherboard/iofpga@3,00000000/uart@0a0000/M/smb/motherboard/iofpga@3,00000000/uart@0b0000/U/smb/motherboard/iofpga@3,00000000/uart@0c0000psci arm,psci]smcdÄp„xÄcpus"1cpu-mapcluster0core0core1core2core3idle-states ƒarm,pscicpu-sleep-0arm,idle-state£(´dÄ–ÕÛcluster-sleep-0arm,idle-state£ô´èÄ ÄÕÛcpu@0ãcpu arm,armv8ïópsciÕÛcpu@1ãcpu arm,armv8ïópsciÕÛcpu@2ãcpu arm,armv8ïópsciÕÛcpu@3ãcpu arm,armv8ïópsciÕÛmemory@80000000ãmemory €interrupt-controller@2f000000 arm,gic-v3"1")Pï// , , ,ð  > ÕÛits@2f020000arm,gic-v3-itsIï/timerarm,armv8-timer0> ÿÿ ÿ ÿXõátimer@2a810000arm,armv7-timer-memï*Xõá"1"frame@2a830000h >ï*ƒpmuarm,armv8-pmuv30><=>?smb simple-bus"1x"  u? ˆ            !!""##$$%%&&''(())**motherboard–rs1arm,vexpress,v2m-p1simple-bus"1"ethernet@2,02000000smsc,lan91c111 ï>clk24mhz fixed-clock©Xn6 ¶v2m:clk24mhzÕ Û refclk1mhz fixed-clock©XB@¶v2m:refclk1mhzÕ Û refclk32khz fixed-clock©X€¶v2m:refclk32khzÕÛiofpga@3,00000000arm,amba-bussimple-bus"1" sysreg@010000arm,vexpress-sysregïÉÙÕ Û sysctl@020000arm,sp810arm,primecellï å ìrefclktimclkapb_pclk©0¶timerclken0timerclken1timerclken2timerclken3Õ Û uart@090000arm,pl011arm,primecellï >å ìuartclkapb_pclkuart@0a0000arm,pl011arm,primecellï >å ìuartclkapb_pclkuart@0b0000arm,pl011arm,primecellï >å ìuartclkapb_pclkuart@0c0000arm,pl011arm,primecellï >å ìuartclkapb_pclkwdt@0f0000arm,sp805arm,primecellï>å ìwdogclkapb_pclktimer@110000arm,sp804arm,primecellï>å  ìtimclken1timclken2apb_pclktimer@120000arm,sp804arm,primecellï>å   ìtimclken1timclken2apb_pclkrtc@170000arm,pl031arm,primecellï>å  ìapb_pclkvirtio_block@0130000 virtio,mmioï>*fixedregulator@0regulator-fixedø3V32Z 2Z 7mcc#arm,vexpress,config-bussimple-busK reset@0arm,vexpress-resetfmuxfpga@0arm,vexpress-muxfpgafshutdown@0arm,vexpress-shutdownfreboot@0arm,vexpress-rebootf dvimode@0arm,vexpress-dvimodef  modelcompatibleinterrupt-parent#address-cells#size-cellsserial0serial1serial2serial3methodcpu_suspendcpu_offcpu_oncpuentry-methodentry-method-paramentry-latency-usexit-latency-usmin-residency-uslinux,phandledevice_typeregenable-methodcpu-idle-states#interrupt-cellsrangesinterrupt-controllerinterruptsmsi-controllerclock-frequencyframe-numberinterrupt-map-maskinterrupt-maparm,v2m-memory-map#clock-cellsclock-output-namesgpio-controller#gpio-cellsclocksclock-namesregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onarm,vexpress,config-bridgearm,vexpress-sysreg,funcarm-trusted-firmware-1.0-aw-6/fdts/fvp-foundation-gicv3-psci.dts000066400000000000000000000145211322600646200245670ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /dts-v1/; /memreserve/ 0x80000000 0x00010000; / { }; / { model = "FVP Foundation"; compatible = "arm,fvp-base", "arm,vexpress"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; chosen { }; aliases { serial0 = &v2m_serial0; serial1 = &v2m_serial1; serial2 = &v2m_serial2; serial3 = &v2m_serial3; }; psci { compatible = "arm,psci"; method = "smc"; cpu_suspend = <0xc4000001>; cpu_off = <0x84000002>; cpu_on = <0xc4000003>; }; cpus { #address-cells = <2>; #size-cells = <0>; cpu-map { cluster0 { core0 { cpu = <&CPU0>; }; core1 { cpu = <&CPU1>; }; core2 { cpu = <&CPU2>; }; core3 { cpu = <&CPU3>; }; }; }; idle-states { entry-method = "arm,psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x0010000>; entry-latency-us = <40>; exit-latency-us = <100>; min-residency-us = <150>; }; CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "arm,idle-state"; entry-method-param = <0x1010000>; entry-latency-us = <500>; exit-latency-us = <1000>; min-residency-us = <2500>; }; }; CPU0:cpu@0 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU1:cpu@1 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU2:cpu@2 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; CPU3:cpu@3 { device_type = "cpu"; compatible = "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; }; memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x7F000000>, <0x00000008 0x80000000 0 0x80000000>; }; gic: interrupt-controller@2f000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; ranges; interrupt-controller; reg = <0x0 0x2f000000 0 0x10000>, // GICD <0x0 0x2f100000 0 0x200000>, // GICR <0x0 0x2c000000 0 0x2000>, // GICC <0x0 0x2c010000 0 0x2000>, // GICH <0x0 0x2c02f000 0 0x2000>; // GICV interrupts = <1 9 4>; its: its@2f020000 { compatible = "arm,gic-v3-its"; msi-controller; reg = <0x0 0x2f020000 0x0 0x20000>; // GITS }; }; timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; clock-frequency = <100000000>; }; timer@2a810000 { compatible = "arm,armv7-timer-mem"; reg = <0x0 0x2a810000 0x0 0x10000>; clock-frequency = <100000000>; #address-cells = <2>; #size-cells = <2>; ranges; frame@2a830000 { frame-number = <1>; interrupts = <0 26 4>; reg = <0x0 0x2a830000 0x0 0x10000>; }; }; pmu { compatible = "arm,armv8-pmuv3"; interrupts = <0 60 4>, <0 61 4>, <0 62 4>, <0 63 4>; }; smb { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0x08000000 0x04000000>, <1 0 0 0x14000000 0x04000000>, <2 0 0 0x18000000 0x04000000>, <3 0 0 0x1c000000 0x04000000>, <4 0 0 0x0c000000 0x04000000>, <5 0 0 0x10000000 0x04000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 63>; interrupt-map = <0 0 0 &gic 0 0 0 0 4>, <0 0 1 &gic 0 0 0 1 4>, <0 0 2 &gic 0 0 0 2 4>, <0 0 3 &gic 0 0 0 3 4>, <0 0 4 &gic 0 0 0 4 4>, <0 0 5 &gic 0 0 0 5 4>, <0 0 6 &gic 0 0 0 6 4>, <0 0 7 &gic 0 0 0 7 4>, <0 0 8 &gic 0 0 0 8 4>, <0 0 9 &gic 0 0 0 9 4>, <0 0 10 &gic 0 0 0 10 4>, <0 0 11 &gic 0 0 0 11 4>, <0 0 12 &gic 0 0 0 12 4>, <0 0 13 &gic 0 0 0 13 4>, <0 0 14 &gic 0 0 0 14 4>, <0 0 15 &gic 0 0 0 15 4>, <0 0 16 &gic 0 0 0 16 4>, <0 0 17 &gic 0 0 0 17 4>, <0 0 18 &gic 0 0 0 18 4>, <0 0 19 &gic 0 0 0 19 4>, <0 0 20 &gic 0 0 0 20 4>, <0 0 21 &gic 0 0 0 21 4>, <0 0 22 &gic 0 0 0 22 4>, <0 0 23 &gic 0 0 0 23 4>, <0 0 24 &gic 0 0 0 24 4>, <0 0 25 &gic 0 0 0 25 4>, <0 0 26 &gic 0 0 0 26 4>, <0 0 27 &gic 0 0 0 27 4>, <0 0 28 &gic 0 0 0 28 4>, <0 0 29 &gic 0 0 0 29 4>, <0 0 30 &gic 0 0 0 30 4>, <0 0 31 &gic 0 0 0 31 4>, <0 0 32 &gic 0 0 0 32 4>, <0 0 33 &gic 0 0 0 33 4>, <0 0 34 &gic 0 0 0 34 4>, <0 0 35 &gic 0 0 0 35 4>, <0 0 36 &gic 0 0 0 36 4>, <0 0 37 &gic 0 0 0 37 4>, <0 0 38 &gic 0 0 0 38 4>, <0 0 39 &gic 0 0 0 39 4>, <0 0 40 &gic 0 0 0 40 4>, <0 0 41 &gic 0 0 0 41 4>, <0 0 42 &gic 0 0 0 42 4>; /include/ "fvp-foundation-motherboard-no_psci.dtsi" }; }; arm-trusted-firmware-1.0-aw-6/fdts/fvp-foundation-motherboard-no_psci.dtsi000066400000000000000000000132331322600646200267260ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of the ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ motherboard { arm,v2m-memory-map = "rs1"; compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; #interrupt-cells = <1>; ranges; ethernet@2,02000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; interrupts = <15>; }; v2m_clk24mhz: clk24mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; v2m_refclk1mhz: refclk1mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; v2m_refclk32khz: refclk32khz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "v2m:refclk32khz"; }; iofpga@3,00000000 { compatible = "arm,amba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 3 0 0x200000>; v2m_sysreg: sysreg@010000 { compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; gpio-controller; #gpio-cells = <2>; }; v2m_sysctl: sysctl@020000 { compatible = "arm,sp810", "arm,primecell"; reg = <0x020000 0x1000>; clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; }; v2m_serial0: uart@090000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial1: uart@0a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial2: uart@0b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial3: uart@0c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; wdt@0f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; clock-names = "wdogclk", "apb_pclk"; }; v2m_timer01: timer@110000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x110000 0x1000>; interrupts = <2>; clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; v2m_timer23: timer@120000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x120000 0x1000>; interrupts = <3>; clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; rtc@170000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x170000 0x1000>; interrupts = <4>; clocks = <&v2m_clk24mhz>; clock-names = "apb_pclk"; }; virtio_block@0130000 { compatible = "virtio,mmio"; reg = <0x130000 0x1000>; interrupts = <0x2a>; }; }; v2m_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; mcc { compatible = "arm,vexpress,config-bus", "simple-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; reset@0 { compatible = "arm,vexpress-reset"; arm,vexpress-sysreg,func = <5 0>; }; muxfpga@0 { compatible = "arm,vexpress-muxfpga"; arm,vexpress-sysreg,func = <7 0>; }; shutdown@0 { compatible = "arm,vexpress-shutdown"; arm,vexpress-sysreg,func = <8 0>; }; reboot@0 { compatible = "arm,vexpress-reboot"; arm,vexpress-sysreg,func = <9 0>; }; dvimode@0 { compatible = "arm,vexpress-dvimode"; arm,vexpress-sysreg,func = <11 0>; }; }; }; arm-trusted-firmware-1.0-aw-6/fdts/fvp-foundation-motherboard.dtsi000066400000000000000000000135711322600646200253030ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of the ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ motherboard { arm,v2m-memory-map = "rs1"; compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; #interrupt-cells = <1>; ranges; ethernet@2,02000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; interrupts = <15>; }; v2m_clk24mhz: clk24mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; v2m_refclk1mhz: refclk1mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; v2m_refclk32khz: refclk32khz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "v2m:refclk32khz"; }; iofpga@3,00000000 { compatible = "arm,amba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 3 0 0x200000>; v2m_sysreg: sysreg@010000 { compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; gpio-controller; #gpio-cells = <2>; }; v2m_sysctl: sysctl@020000 { compatible = "arm,sp810", "arm,primecell"; reg = <0x020000 0x1000>; clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; }; v2m_serial0: uart@090000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial1: uart@0a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial2: uart@0b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial3: uart@0c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; wdt@0f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; clock-names = "wdogclk", "apb_pclk"; }; v2m_timer01: timer@110000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x110000 0x1000>; interrupts = <2>; clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; v2m_timer23: timer@120000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x120000 0x1000>; interrupts = <3>; clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; rtc@170000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x170000 0x1000>; interrupts = <4>; clocks = <&v2m_clk24mhz>; clock-names = "apb_pclk"; }; virtio_block@0130000 { compatible = "virtio,mmio"; reg = <0x130000 0x1000>; interrupts = <0x2a>; }; }; v2m_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; mcc { compatible = "arm,vexpress,config-bus", "simple-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; /* * Not supported in FVP models * * reset@0 { * compatible = "arm,vexpress-reset"; * arm,vexpress-sysreg,func = <5 0>; * }; */ muxfpga@0 { compatible = "arm,vexpress-muxfpga"; arm,vexpress-sysreg,func = <7 0>; }; /* * Not used - Superseded by PSCI sys_poweroff * * shutdown@0 { * compatible = "arm,vexpress-shutdown"; * arm,vexpress-sysreg,func = <8 0>; * }; */ /* * Not used - Superseded by PSCI sys_reset * * reboot@0 { * compatible = "arm,vexpress-reboot"; * arm,vexpress-sysreg,func = <9 0>; * }; */ dvimode@0 { compatible = "arm,vexpress-dvimode"; arm,vexpress-sysreg,func = <11 0>; }; }; }; arm-trusted-firmware-1.0-aw-6/fdts/rtsm_ve-motherboard-no_psci.dtsi000066400000000000000000000165451322600646200254570ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ motherboard { arm,v2m-memory-map = "rs1"; compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; #interrupt-cells = <1>; ranges; flash@0,00000000 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; bank-width = <4>; }; vram@2,00000000 { compatible = "arm,vexpress-vram"; reg = <2 0x00000000 0x00800000>; }; ethernet@2,02000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; interrupts = <15>; }; v2m_clk24mhz: clk24mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; v2m_refclk1mhz: refclk1mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; v2m_refclk32khz: refclk32khz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "v2m:refclk32khz"; }; iofpga@3,00000000 { compatible = "arm,amba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 3 0 0x200000>; v2m_sysreg: sysreg@010000 { compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; gpio-controller; #gpio-cells = <2>; }; v2m_sysctl: sysctl@020000 { compatible = "arm,sp810", "arm,primecell"; reg = <0x020000 0x1000>; clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; }; aaci@040000 { compatible = "arm,pl041", "arm,primecell"; reg = <0x040000 0x1000>; interrupts = <11>; clocks = <&v2m_clk24mhz>; clock-names = "apb_pclk"; }; mmci@050000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; interrupts = <9 10>; cd-gpios = <&v2m_sysreg 0 0>; wp-gpios = <&v2m_sysreg 1 0>; max-frequency = <12000000>; vmmc-supply = <&v2m_fixed_3v3>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "mclk", "apb_pclk"; }; kmi@060000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x060000 0x1000>; interrupts = <12>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "KMIREFCLK", "apb_pclk"; }; kmi@070000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x070000 0x1000>; interrupts = <13>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "KMIREFCLK", "apb_pclk"; }; v2m_serial0: uart@090000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial1: uart@0a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial2: uart@0b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial3: uart@0c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; wdt@0f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; clock-names = "wdogclk", "apb_pclk"; }; v2m_timer01: timer@110000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x110000 0x1000>; interrupts = <2>; clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; v2m_timer23: timer@120000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x120000 0x1000>; interrupts = <3>; clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; rtc@170000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x170000 0x1000>; interrupts = <4>; clocks = <&v2m_clk24mhz>; clock-names = "apb_pclk"; }; clcd@1f0000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x1f0000 0x1000>; interrupts = <14>; clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; clock-names = "clcdclk", "apb_pclk"; mode = "XVGA"; use_dma = <0>; framebuffer = <0x18000000 0x00180000>; }; virtio_block@0130000 { compatible = "virtio,mmio"; reg = <0x130000 0x1000>; interrupts = <0x2a>; }; }; v2m_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; mcc { compatible = "arm,vexpress,config-bus", "simple-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; v2m_oscclk1: osc@1 { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; freq-range = <23750000 63500000>; #clock-cells = <0>; clock-output-names = "v2m:oscclk1"; }; reset@0 { compatible = "arm,vexpress-reset"; arm,vexpress-sysreg,func = <5 0>; }; muxfpga@0 { compatible = "arm,vexpress-muxfpga"; arm,vexpress-sysreg,func = <7 0>; }; shutdown@0 { compatible = "arm,vexpress-shutdown"; arm,vexpress-sysreg,func = <8 0>; }; reboot@0 { compatible = "arm,vexpress-reboot"; arm,vexpress-sysreg,func = <9 0>; }; dvimode@0 { compatible = "arm,vexpress-dvimode"; arm,vexpress-sysreg,func = <11 0>; }; }; }; arm-trusted-firmware-1.0-aw-6/fdts/rtsm_ve-motherboard.dtsi000066400000000000000000000171031322600646200240160ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ motherboard { arm,v2m-memory-map = "rs1"; compatible = "arm,vexpress,v2m-p1", "simple-bus"; #address-cells = <2>; /* SMB chipselect number and offset */ #size-cells = <1>; #interrupt-cells = <1>; ranges; flash@0,00000000 { compatible = "arm,vexpress-flash", "cfi-flash"; reg = <0 0x00000000 0x04000000>, <4 0x00000000 0x04000000>; bank-width = <4>; }; vram@2,00000000 { compatible = "arm,vexpress-vram"; reg = <2 0x00000000 0x00800000>; }; ethernet@2,02000000 { compatible = "smsc,lan91c111"; reg = <2 0x02000000 0x10000>; interrupts = <15>; }; v2m_clk24mhz: clk24mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; v2m_refclk1mhz: refclk1mhz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; v2m_refclk32khz: refclk32khz { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "v2m:refclk32khz"; }; iofpga@3,00000000 { compatible = "arm,amba-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 3 0 0x200000>; v2m_sysreg: sysreg@010000 { compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; gpio-controller; #gpio-cells = <2>; }; v2m_sysctl: sysctl@020000 { compatible = "arm,sp810", "arm,primecell"; reg = <0x020000 0x1000>; clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; clock-names = "refclk", "timclk", "apb_pclk"; #clock-cells = <1>; clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; }; aaci@040000 { compatible = "arm,pl041", "arm,primecell"; reg = <0x040000 0x1000>; interrupts = <11>; clocks = <&v2m_clk24mhz>; clock-names = "apb_pclk"; }; mmci@050000 { compatible = "arm,pl180", "arm,primecell"; reg = <0x050000 0x1000>; interrupts = <9 10>; cd-gpios = <&v2m_sysreg 0 0>; wp-gpios = <&v2m_sysreg 1 0>; max-frequency = <12000000>; vmmc-supply = <&v2m_fixed_3v3>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "mclk", "apb_pclk"; }; kmi@060000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x060000 0x1000>; interrupts = <12>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "KMIREFCLK", "apb_pclk"; }; kmi@070000 { compatible = "arm,pl050", "arm,primecell"; reg = <0x070000 0x1000>; interrupts = <13>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "KMIREFCLK", "apb_pclk"; }; v2m_serial0: uart@090000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; interrupts = <5>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial1: uart@0a0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a0000 0x1000>; interrupts = <6>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial2: uart@0b0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b0000 0x1000>; interrupts = <7>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; v2m_serial3: uart@0c0000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c0000 0x1000>; interrupts = <8>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clock-names = "uartclk", "apb_pclk"; }; wdt@0f0000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; clock-names = "wdogclk", "apb_pclk"; }; v2m_timer01: timer@110000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x110000 0x1000>; interrupts = <2>; clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; v2m_timer23: timer@120000 { compatible = "arm,sp804", "arm,primecell"; reg = <0x120000 0x1000>; interrupts = <3>; clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; clock-names = "timclken1", "timclken2", "apb_pclk"; }; rtc@170000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x170000 0x1000>; interrupts = <4>; clocks = <&v2m_clk24mhz>; clock-names = "apb_pclk"; }; clcd@1f0000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x1f0000 0x1000>; interrupts = <14>; clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; clock-names = "clcdclk", "apb_pclk"; mode = "XVGA"; use_dma = <0>; framebuffer = <0x18000000 0x00180000>; }; virtio_block@0130000 { compatible = "virtio,mmio"; reg = <0x130000 0x1000>; interrupts = <0x2a>; }; }; v2m_fixed_3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; mcc { compatible = "arm,vexpress,config-bus", "simple-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; v2m_oscclk1: osc@1 { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; freq-range = <23750000 63500000>; #clock-cells = <0>; clock-output-names = "v2m:oscclk1"; }; /* * Not supported in FVP models * * reset@0 { * compatible = "arm,vexpress-reset"; * arm,vexpress-sysreg,func = <5 0>; * }; */ muxfpga@0 { compatible = "arm,vexpress-muxfpga"; arm,vexpress-sysreg,func = <7 0>; }; /* * Not used - Superseded by PSCI sys_poweroff * * shutdown@0 { * compatible = "arm,vexpress-shutdown"; * arm,vexpress-sysreg,func = <8 0>; * }; */ /* * Not used - Superseded by PSCI sys_reset * * reboot@0 { * compatible = "arm,vexpress-reboot"; * arm,vexpress-sysreg,func = <9 0>; * }; */ dvimode@0 { compatible = "arm,vexpress-dvimode"; arm,vexpress-sysreg,func = <11 0>; }; }; }; arm-trusted-firmware-1.0-aw-6/include/000077500000000000000000000000001322600646200176275ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/bl31/000077500000000000000000000000001322600646200203705ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/bl31/bl31.h000066400000000000000000000040561322600646200213070ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __BL31_H__ #define __BL31_H__ #include /******************************************************************************* * Function prototypes ******************************************************************************/ void bl31_arch_setup(void); void bl31_next_el_arch_setup(uint32_t security_state); void bl31_set_next_image_type(uint32_t type); uint32_t bl31_get_next_image_type(void); void bl31_prepare_next_image_entry(void); void bl31_register_bl32_init(int32_t (*)(void)); #endif /* __BL31_H__ */ arm-trusted-firmware-1.0-aw-6/include/bl31/context.h000066400000000000000000000274101322600646200222310ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CONTEXT_H__ #define __CONTEXT_H__ /******************************************************************************* * Constants that allow assembler code to access members of and the 'gp_regs' * structure at their correct offsets. ******************************************************************************/ #define CTX_GPREGS_OFFSET 0x0 #define CTX_GPREG_X0 0x0 #define CTX_GPREG_X1 0x8 #define CTX_GPREG_X2 0x10 #define CTX_GPREG_X3 0x18 #define CTX_GPREG_X4 0x20 #define CTX_GPREG_X5 0x28 #define CTX_GPREG_X6 0x30 #define CTX_GPREG_X7 0x38 #define CTX_GPREG_X8 0x40 #define CTX_GPREG_X9 0x48 #define CTX_GPREG_X10 0x50 #define CTX_GPREG_X11 0x58 #define CTX_GPREG_X12 0x60 #define CTX_GPREG_X13 0x68 #define CTX_GPREG_X14 0x70 #define CTX_GPREG_X15 0x78 #define CTX_GPREG_X16 0x80 #define CTX_GPREG_X17 0x88 #define CTX_GPREG_X18 0x90 #define CTX_GPREG_X19 0x98 #define CTX_GPREG_X20 0xa0 #define CTX_GPREG_X21 0xa8 #define CTX_GPREG_X22 0xb0 #define CTX_GPREG_X23 0xb8 #define CTX_GPREG_X24 0xc0 #define CTX_GPREG_X25 0xc8 #define CTX_GPREG_X26 0xd0 #define CTX_GPREG_X27 0xd8 #define CTX_GPREG_X28 0xe0 #define CTX_GPREG_X29 0xe8 #define CTX_GPREG_LR 0xf0 #define CTX_GPREG_SP_EL0 0xf8 #define CTX_GPREGS_END 0x100 /******************************************************************************* * Constants that allow assembler code to access members of and the 'el3_state' * structure at their correct offsets. Note that some of the registers are only * 32-bits wide but are stored as 64-bit values for convenience ******************************************************************************/ #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) #define CTX_SCR_EL3 0x0 #define CTX_RUNTIME_SP 0x8 #define CTX_SPSR_EL3 0x10 #define CTX_ELR_EL3 0x18 #define CTX_EL3STATE_END 0x20 /******************************************************************************* * Constants that allow assembler code to access members of and the * 'el1_sys_regs' structure at their correct offsets. Note that some of the * registers are only 32-bits wide but are stored as 64-bit values for * convenience ******************************************************************************/ #define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) #define CTX_SPSR_EL1 0x0 #define CTX_ELR_EL1 0x8 #define CTX_SPSR_ABT 0x10 #define CTX_SPSR_UND 0x18 #define CTX_SPSR_IRQ 0x20 #define CTX_SPSR_FIQ 0x28 #define CTX_SCTLR_EL1 0x30 #define CTX_ACTLR_EL1 0x38 #define CTX_CPACR_EL1 0x40 #define CTX_CSSELR_EL1 0x48 #define CTX_SP_EL1 0x50 #define CTX_ESR_EL1 0x58 #define CTX_TTBR0_EL1 0x60 #define CTX_TTBR1_EL1 0x68 #define CTX_MAIR_EL1 0x70 #define CTX_AMAIR_EL1 0x78 #define CTX_TCR_EL1 0x80 #define CTX_TPIDR_EL1 0x88 #define CTX_TPIDR_EL0 0x90 #define CTX_TPIDRRO_EL0 0x98 #define CTX_DACR32_EL2 0xa0 #define CTX_IFSR32_EL2 0xa8 #define CTX_PAR_EL1 0xb0 #define CTX_FAR_EL1 0xb8 #define CTX_AFSR0_EL1 0xc0 #define CTX_AFSR1_EL1 0xc8 #define CTX_CONTEXTIDR_EL1 0xd0 #define CTX_VBAR_EL1 0xd8 /* * If the timer registers aren't saved and restored, we don't have to reserve * space for them in the context */ #if NS_TIMER_SWITCH #define CTX_CNTP_CTL_EL0 0xe0 #define CTX_CNTP_CVAL_EL0 0xe8 #define CTX_CNTV_CTL_EL0 0xf0 #define CTX_CNTV_CVAL_EL0 0xf8 #define CTX_CNTKCTL_EL1 0x100 #define CTX_FP_FPEXC32_EL2 0x108 #define CTX_SYSREGS_END 0x110 #else #define CTX_FP_FPEXC32_EL2 0xe0 #define CTX_SYSREGS_END 0xf0 #endif /******************************************************************************* * Constants that allow assembler code to access members of and the 'fp_regs' * structure at their correct offsets. ******************************************************************************/ #if CTX_INCLUDE_FPREGS #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) #define CTX_FP_Q0 0x0 #define CTX_FP_Q1 0x10 #define CTX_FP_Q2 0x20 #define CTX_FP_Q3 0x30 #define CTX_FP_Q4 0x40 #define CTX_FP_Q5 0x50 #define CTX_FP_Q6 0x60 #define CTX_FP_Q7 0x70 #define CTX_FP_Q8 0x80 #define CTX_FP_Q9 0x90 #define CTX_FP_Q10 0xa0 #define CTX_FP_Q11 0xb0 #define CTX_FP_Q12 0xc0 #define CTX_FP_Q13 0xd0 #define CTX_FP_Q14 0xe0 #define CTX_FP_Q15 0xf0 #define CTX_FP_Q16 0x100 #define CTX_FP_Q17 0x110 #define CTX_FP_Q18 0x120 #define CTX_FP_Q19 0x130 #define CTX_FP_Q20 0x140 #define CTX_FP_Q21 0x150 #define CTX_FP_Q22 0x160 #define CTX_FP_Q23 0x170 #define CTX_FP_Q24 0x180 #define CTX_FP_Q25 0x190 #define CTX_FP_Q26 0x1a0 #define CTX_FP_Q27 0x1b0 #define CTX_FP_Q28 0x1c0 #define CTX_FP_Q29 0x1d0 #define CTX_FP_Q30 0x1e0 #define CTX_FP_Q31 0x1f0 #define CTX_FP_FPSR 0x200 #define CTX_FP_FPCR 0x208 #define CTX_FPREGS_END 0x210 #endif #ifndef __ASSEMBLY__ #include #include /* for CACHE_WRITEBACK_GRANULE */ #include /* * Common constants to help define the 'cpu_context' structure and its * members below. */ #define DWORD_SHIFT 3 #define DEFINE_REG_STRUCT(name, num_regs) \ typedef struct name { \ uint64_t _regs[num_regs]; \ } __aligned(16) name##_t /* Constants to determine the size of individual context structures */ #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) #define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) #if CTX_INCLUDE_FPREGS #define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) #endif #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) /* * AArch64 general purpose register context structure. Usually x0-x18, * lr are saved as the compiler is expected to preserve the remaining * callee saved registers if used by the C runtime and the assembler * does not touch the remaining. But in case of world switch during * exception handling, we need to save the callee registers too. */ DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); /* * AArch64 EL1 system register context structure for preserving the * architectural state during switches from one security state to * another in EL1. */ DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); /* * AArch64 floating point register context structure for preserving * the floating point state during switches from one security state to * another. */ #if CTX_INCLUDE_FPREGS DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); #endif /* * Miscellaneous registers used by EL3 firmware to maintain its state * across exception entries and exits */ DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); /* * Macros to access members of any of the above structures using their * offsets */ #define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) #define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \ = val) /* * Top-level context structure which is used by EL3 firmware to * preserve the state of a core at EL1 in one of the two security * states and save enough EL3 meta data to be able to return to that * EL and security state. The context management library will be used * to ensure that SP_EL3 always points to an instance of this * structure at exception entry and exit. Each instance will * correspond to either the secure or the non-secure state. */ typedef struct cpu_context { gp_regs_t gpregs_ctx; el3_state_t el3state_ctx; el1_sys_regs_t sysregs_ctx; #if CTX_INCLUDE_FPREGS fp_regs_t fpregs_ctx; #endif } cpu_context_t; /* Macros to access members of the 'cpu_context_t' structure */ #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) #if CTX_INCLUDE_FPREGS #define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) #endif #define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) /* * Compile time assertions related to the 'cpu_context' structure to * ensure that the assembler and the compiler view of the offsets of * the structure members is the same. */ CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ assert_core_context_gp_offset_mismatch); CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ assert_core_context_sys_offset_mismatch); #if CTX_INCLUDE_FPREGS CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ assert_core_context_fp_offset_mismatch); #endif CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ assert_core_context_el3state_offset_mismatch); /* * Helper macro to set the general purpose registers that correspond to * parameters in an aapcs_64 call i.e. x0-x7 */ #define set_aapcs_args0(ctx, x0) do { \ write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ } while (0); #define set_aapcs_args1(ctx, x0, x1) do { \ write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ set_aapcs_args0(ctx, x0); \ } while (0); #define set_aapcs_args2(ctx, x0, x1, x2) do { \ write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ set_aapcs_args1(ctx, x0, x1); \ } while (0); #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ set_aapcs_args2(ctx, x0, x1, x2); \ } while (0); #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ set_aapcs_args3(ctx, x0, x1, x2, x3); \ } while (0); #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ } while (0); #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ } while (0); #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ } while (0); /******************************************************************************* * Function prototypes ******************************************************************************/ void el1_sysregs_context_save(el1_sys_regs_t *regs); void el1_sysregs_context_restore(el1_sys_regs_t *regs); #if CTX_INCLUDE_FPREGS void fpregs_context_save(fp_regs_t *regs); void fpregs_context_restore(fp_regs_t *regs); #endif #undef CTX_SYSREG_ALL #if CTX_INCLUDE_FPREGS #undef CTX_FPREG_ALL #endif #undef CTX_GPREG_ALL #undef CTX_EL3STATE_ALL #endif /* __ASSEMBLY__ */ #endif /* __CONTEXT_H__ */ arm-trusted-firmware-1.0-aw-6/include/bl31/context_mgmt.h000066400000000000000000000076531322600646200232640ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CM_H__ #define __CM_H__ #include #include /******************************************************************************* * Forward declarations ******************************************************************************/ struct entry_point_info; /******************************************************************************* * Function & variable prototypes ******************************************************************************/ void cm_init(void); void *cm_get_context_by_mpidr(uint64_t mpidr, uint32_t security_state); static inline void *cm_get_context(uint32_t security_state); void cm_set_context_by_mpidr(uint64_t mpidr, void *context, uint32_t security_state); static inline void cm_set_context(void *context, uint32_t security_state); void cm_init_context(uint64_t mpidr, const struct entry_point_info *ep); void cm_prepare_el3_exit(uint32_t security_state); void cm_el1_sysregs_context_save(uint32_t security_state); void cm_el1_sysregs_context_restore(uint32_t security_state); void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint); void cm_set_elr_spsr_el3(uint32_t security_state, uint64_t entrypoint, uint32_t spsr); void cm_write_scr_el3_bit(uint32_t security_state, uint32_t bit_pos, uint32_t value); void cm_set_next_eret_context(uint32_t security_state); uint32_t cm_get_scr_el3(uint32_t security_state); /* Inline definitions */ /******************************************************************************* * This function returns a pointer to the most recent 'cpu_context' structure * for the calling CPU that was set as the context for the specified security * state. NULL is returned if no such structure has been specified. ******************************************************************************/ void *cm_get_context(uint32_t security_state) { assert(security_state <= NON_SECURE); return get_cpu_data(cpu_context[security_state]); } /******************************************************************************* * This function sets the pointer to the current 'cpu_context' structure for the * specified security state for the calling CPU ******************************************************************************/ void cm_set_context(void *context, uint32_t security_state) { assert(security_state <= NON_SECURE); set_cpu_data(cpu_context[security_state], context); } #endif /* __CM_H__ */ arm-trusted-firmware-1.0-aw-6/include/bl31/cpu_data.h000066400000000000000000000113151322600646200223220ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CPU_DATA_H__ #define __CPU_DATA_H__ /* Offsets for the cpu_data structure */ #define CPU_DATA_CRASH_BUF_OFFSET 0x20 #if CRASH_REPORTING #define CPU_DATA_LOG2SIZE 7 #else #define CPU_DATA_LOG2SIZE 6 #endif /* need enough space in crash buffer to save 8 registers */ #define CPU_DATA_CRASH_BUF_SIZE 64 #define CPU_DATA_CPU_OPS_PTR 0x10 #ifndef __ASSEMBLY__ #include #include #include #include /******************************************************************************* * Function & variable prototypes ******************************************************************************/ /******************************************************************************* * Cache of frequently used per-cpu data: * Pointers to non-secure and secure security state contexts * Address of the crash stack * It is aligned to the cache line boundary to allow efficient concurrent * manipulation of these pointers on different cpus * * TODO: Add other commonly used variables to this (tf_issues#90) * * The data structure and the _cpu_data accessors should not be used directly * by components that have per-cpu members. The member access macros should be * used for this. ******************************************************************************/ typedef struct cpu_data { void *cpu_context[2]; uint64_t cpu_ops_ptr; struct psci_cpu_data psci_svc_cpu_data; #if CRASH_REPORTING uint64_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3]; #endif } __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t; #if CRASH_REPORTING /* verify assembler offsets match data structures */ CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof (cpu_data_t, crash_buf), assert_cpu_data_crash_stack_offset_mismatch); #endif CASSERT((1 << CPU_DATA_LOG2SIZE) == sizeof(cpu_data_t), assert_cpu_data_log2size_mismatch); CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof (cpu_data_t, cpu_ops_ptr), assert_cpu_data_cpu_ops_ptr_offset_mismatch); struct cpu_data *_cpu_data_by_index(uint32_t cpu_index); struct cpu_data *_cpu_data_by_mpidr(uint64_t mpidr); /* Return the cpu_data structure for the current CPU. */ static inline struct cpu_data *_cpu_data(void) { return (cpu_data_t *)read_tpidr_el3(); } /************************************************************************** * APIs for initialising and accessing per-cpu data *************************************************************************/ void init_cpu_data_ptr(void); #define get_cpu_data(_m) _cpu_data()->_m #define set_cpu_data(_m, _v) _cpu_data()->_m = _v #define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m #define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v #define get_cpu_data_by_mpidr(_id, _m) _cpu_data_by_mpidr(_id)->_m #define set_cpu_data_by_mpidr(_id, _m, _v) _cpu_data_by_mpidr(_id)->_m = _v #define flush_cpu_data(_m) flush_dcache_range((uint64_t) \ &(_cpu_data()->_m), \ sizeof(_cpu_data()->_m)) #define flush_cpu_data_by_index(_ix, _m) \ flush_dcache_range((uint64_t) \ &(_cpu_data_by_index(_ix)->_m), \ sizeof(_cpu_data_by_index(_ix)->_m)) #endif /* __ASSEMBLY__ */ #endif /* __CPU_DATA_H__ */ arm-trusted-firmware-1.0-aw-6/include/bl31/head_data.h000066400000000000000000000016341322600646200224370ustar00rootroot00000000000000/* * * Header for system * */ #ifndef __HEAD_H__ #define __HEAD_H__ /******************************************************************************/ /* the control information stored in file head */ /******************************************************************************/ struct spare_boot_ctrl_head { unsigned int jump_instruction; // one intruction jumping to real code unsigned char magic[8]; // ="u-boot" unsigned int check_sum; // generated by PC unsigned int align_size; // align size in byte unsigned int length; // the size of all file unsigned int uboot_length; // the size of uboot unsigned char version[8]; // uboot version unsigned char platform[8]; // platform information int reserved[1]; //stamp space, 16bytes align } ; #endif /* __HEAD_H__ */ arm-trusted-firmware-1.0-aw-6/include/bl31/interrupt_mgmt.h000066400000000000000000000131561322600646200236270ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __INTERRUPT_MGMT_H__ #define __INTERRUPT_MGMT_H__ #include /******************************************************************************* * Constants for the types of interrupts recognised by the IM framework ******************************************************************************/ #define INTR_TYPE_S_EL1 0 #define INTR_TYPE_EL3 1 #define INTR_TYPE_NS 2 #define MAX_INTR_TYPES 3 #define INTR_TYPE_INVAL MAX_INTR_TYPES /* * Constant passed to the interrupt handler in the 'id' field when the * framework does not read the gic registers to determine the interrupt id. */ #define INTR_ID_UNAVAILABLE 0xFFFFFFFF /******************************************************************************* * Mask for _both_ the routing model bits in the 'flags' parameter and * constants to define the valid routing models for each supported interrupt * type ******************************************************************************/ #define INTR_RM_FLAGS_SHIFT 0x0 #define INTR_RM_FLAGS_MASK 0x3 /* Routed to EL3 from NS. Taken to S-EL1 from Secure */ #define INTR_SEL1_VALID_RM0 0x2 /* Routed to EL3 from NS and Secure */ #define INTR_SEL1_VALID_RM1 0x3 /* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ #define INTR_NS_VALID_RM0 0x0 /* Routed to EL1/EL2 from NS and to EL3 from Secure */ #define INTR_NS_VALID_RM1 0x1 /******************************************************************************* * Constants for the _individual_ routing model bits in the 'flags' field for * each interrupt type and mask to validate the 'flags' parameter while * registering an interrupt handler ******************************************************************************/ #define INTR_TYPE_FLAGS_MASK 0xFFFFFFFC #define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ #define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ #define INTR_RM_FROM_FLAG_MASK 1 #define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \ & INTR_RM_FROM_FLAG_MASK) #define set_interrupt_rm_flag(flag, ss) (flag |= 1 << ss) #define clr_interrupt_rm_flag(flag, ss) (flag &= ~(1 << ss)) /******************************************************************************* * Macros to validate the routing model bits in the 'flags' for a type * of interrupt. If the model does not match one of the valid masks * -EINVAL is returned. ******************************************************************************/ #define validate_sel1_interrupt_rm(x) (x == INTR_SEL1_VALID_RM0 ? 0 : \ (x == INTR_SEL1_VALID_RM1 ? 0 :\ -EINVAL)) #define validate_ns_interrupt_rm(x) (x == INTR_NS_VALID_RM0 ? 0 : \ (x == INTR_NS_VALID_RM1 ? 0 :\ -EINVAL)) /******************************************************************************* * Macros to set the 'flags' parameter passed to an interrupt type handler. Only * the flag to indicate the security state when the exception was generated is * supported. ******************************************************************************/ #define INTR_SRC_SS_FLAG_SHIFT 0 /* BIT[0] */ #define INTR_SRC_SS_FLAG_MASK 1 #define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT) #define clr_interrupt_src_ss(flag) (flag &= ~(1 << INTR_SRC_SS_FLAG_SHIFT)) #define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \ INTR_SRC_SS_FLAG_MASK) #ifndef __ASSEMBLY__ /* Prototype for defining a handler for an interrupt type */ typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, uint32_t flags, void *handle, void *cookie); /******************************************************************************* * Function & variable prototypes ******************************************************************************/ uint32_t get_scr_el3_from_routing_model(uint32_t security_state); int32_t set_routing_model(uint32_t type, uint32_t flags); int32_t register_interrupt_type_handler(uint32_t type, interrupt_type_handler_t handler, uint32_t flags); interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type); #endif /*__ASSEMBLY__*/ #endif /* __INTERRUPT_MGMT_H__ */ arm-trusted-firmware-1.0-aw-6/include/bl31/runtime_svc.h000066400000000000000000000225511322600646200231040ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __RUNTIME_SVC_H__ #define __RUNTIME_SVC_H__ /******************************************************************************* * Bit definitions inside the function id as per the SMC calling convention ******************************************************************************/ #define FUNCID_TYPE_SHIFT 31 #define FUNCID_CC_SHIFT 30 #define FUNCID_OEN_SHIFT 24 #define FUNCID_NUM_SHIFT 0 #define FUNCID_TYPE_MASK 0x1 #define FUNCID_CC_MASK 0x1 #define FUNCID_OEN_MASK 0x3f #define FUNCID_NUM_MASK 0xffff #define FUNCID_TYPE_WIDTH 1 #define FUNCID_CC_WIDTH 1 #define FUNCID_OEN_WIDTH 6 #define FUNCID_NUM_WIDTH 16 #define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ FUNCID_CC_MASK) #define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \ FUNCID_TYPE_MASK) #define SMC_64 1 #define SMC_32 0 #define SMC_UNK 0xffffffff #define SMC_TYPE_FAST 1 #define SMC_TYPE_STD 0 #define SMC_PREEMPTED 0xfffffffe /******************************************************************************* * Owning entity number definitions inside the function id as per the SMC * calling convention ******************************************************************************/ #define OEN_ARM_START 0 #define OEN_ARM_END 0 #define OEN_CPU_START 1 #define OEN_CPU_END 1 #define OEN_SIP_START 2 #define OEN_SIP_END 2 #define OEN_OEM_START 3 #define OEN_OEM_END 3 #define OEN_STD_START 4 /* Standard Calls */ #define OEN_STD_END 4 #define OEN_TAP_START 48 /* Trusted Applications */ #define OEN_TAP_END 49 #define OEN_TOS_START 50 /* Trusted OS */ #define OEN_TOS_END 63 #define OEN_LIMIT 64 /******************************************************************************* * Constants to indicate type of exception to the common exception handler. ******************************************************************************/ #define SYNC_EXCEPTION_SP_EL0 0x0 #define IRQ_SP_EL0 0x1 #define FIQ_SP_EL0 0x2 #define SERROR_SP_EL0 0x3 #define SYNC_EXCEPTION_SP_ELX 0x4 #define IRQ_SP_ELX 0x5 #define FIQ_SP_ELX 0x6 #define SERROR_SP_ELX 0x7 #define SYNC_EXCEPTION_AARCH64 0x8 #define IRQ_AARCH64 0x9 #define FIQ_AARCH64 0xa #define SERROR_AARCH64 0xb #define SYNC_EXCEPTION_AARCH32 0xc #define IRQ_AARCH32 0xd #define FIQ_AARCH32 0xe #define SERROR_AARCH32 0xf /******************************************************************************* * Structure definition, typedefs & constants for the runtime service framework ******************************************************************************/ /* * Constants to allow the assembler access a runtime service * descriptor */ #define RT_SVC_SIZE_LOG2 5 #define SIZEOF_RT_SVC_DESC (1 << RT_SVC_SIZE_LOG2) #define RT_SVC_DESC_INIT 16 #define RT_SVC_DESC_HANDLE 24 /* * The function identifier has 6 bits for the owning entity number and * single bit for the type of smc call. When taken together these * values limit the maximum number of runtime services to 128. */ #define MAX_RT_SVCS 128 #ifndef __ASSEMBLY__ #include #include #include /* Various flags passed to SMC handlers */ #define SMC_FROM_SECURE (0 << 0) #define SMC_FROM_NON_SECURE (1 << 0) #define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) #define is_caller_secure(_f) (!(is_caller_non_secure(_f))) /* Prototype for runtime service initializing function */ typedef int32_t (*rt_svc_init_t)(void); /* Convenience macros to return from SMC handler */ #define SMC_RET0(_h) { \ return (uint64_t) (_h); \ } #define SMC_RET1(_h, _x0) { \ write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X0, (_x0)); \ SMC_RET0(_h); \ } #define SMC_RET2(_h, _x0, _x1) { \ write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X1, (_x1)); \ SMC_RET1(_h, (_x0)); \ } #define SMC_RET3(_h, _x0, _x1, _x2) { \ write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X2, (_x2)); \ SMC_RET2(_h, (_x0), (_x1)); \ } #define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X3, (_x3)); \ SMC_RET3(_h, (_x0), (_x1), (_x2)); \ } /* * Convenience macros to access general purpose registers using handle provided * to SMC handler. These takes the offset values defined in context.h */ #define SMC_GET_GP(_h, _g) \ read_ctx_reg(get_gpregs_ctx(_h), (_g)); #define SMC_SET_GP(_h, _g, _v) \ write_ctx_reg(get_gpregs_ctx(_h), (_g), (_v)); /* * Convenience macros to access EL3 context registers using handle provided to * SMC handler. These takes the offset values defined in context.h */ #define SMC_GET_EL3(_h, _e) \ read_ctx_reg(get_el3state_ctx(_h), (_e)); #define SMC_SET_EL3(_h, _e, _v) \ write_ctx_reg(get_el3state_ctx(_h), (_e), (_v)); /* * Prototype for runtime service SMC handler function. x0 (SMC Function ID) to * x4 are as passed by the caller. Rest of the arguments to SMC and the context * can be accessed using the handle pointer. The cookie parameter is reserved * for future use */ typedef uint64_t (*rt_svc_handle_t)(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags); typedef struct rt_svc_desc { uint8_t start_oen; uint8_t end_oen; uint8_t call_type; const char *name; rt_svc_init_t init; rt_svc_handle_t handle; } rt_svc_desc_t; /* * Convenience macro to declare a service descriptor */ #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ static const rt_svc_desc_t __svc_desc_ ## _name \ __attribute__ ((section("rt_svc_descs"), used)) = { \ _start, \ _end, \ _type, \ #_name, \ _setup, \ _smch } /* * Compile time assertions related to the 'rt_svc_desc' structure to: * 1. ensure that the assembler and the compiler view of the size * of the structure are the same. * 2. ensure that the assembler and the compiler see the initialisation * routine at the same offset. * 3. ensure that the assembler and the compiler see the handler * routine at the same offset. */ CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC), \ assert_sizeof_rt_svc_desc_mismatch); CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init), \ assert_rt_svc_desc_init_offset_mismatch); CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \ assert_rt_svc_desc_handle_offset_mismatch); /* * This macro combines the call type and the owning entity number corresponding * to a runtime service to generate a unique owning entity number. This unique * oen is used to access an entry in the 'rt_svc_descs_indices' array. The entry * contains the index of the service descriptor in the 'rt_svc_descs' array. */ #define get_unique_oen(oen, call_type) ((oen & FUNCID_OEN_MASK) | \ ((call_type & FUNCID_TYPE_MASK) \ << FUNCID_OEN_WIDTH)) /* * Macro to define UUID for services. Apart from defining and initializing a * uuid_t structure, this macro verifies that the first word of the defined UUID * does not equal SMC_UNK. This is to ensure that the caller won't mistake the * returned UUID in x0 for an invalid SMC error return */ #define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \ _n0, _n1, _n2, _n3, _n4, _n5) \ CASSERT(_tl != SMC_UNK, invalid_svc_uuid);\ static const uuid_t _name = { \ _tl, _tm, _th, _cl, _ch, \ { _n0, _n1, _n2, _n3, _n4, _n5 } \ } /* Return a UUID in the SMC return registers */ #define SMC_UUID_RET(_h, _uuid) \ SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ ((const uint32_t *) &(_uuid))[1], \ ((const uint32_t *) &(_uuid))[2], \ ((const uint32_t *) &(_uuid))[3]) /******************************************************************************* * Function & variable prototypes ******************************************************************************/ void runtime_svc_init(void); extern uint64_t __RT_SVC_DESCS_START__; extern uint64_t __RT_SVC_DESCS_END__; void init_crash_reporting(void); #endif /*__ASSEMBLY__*/ #endif /* __RUNTIME_SVC_H__ */ arm-trusted-firmware-1.0-aw-6/include/bl31/services/000077500000000000000000000000001322600646200222135ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/bl31/services/psci.h000066400000000000000000000206171322600646200233300ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PSCI_H__ #define __PSCI_H__ /******************************************************************************* * Defines for runtime services func ids ******************************************************************************/ #define PSCI_VERSION 0x84000000 #define PSCI_CPU_SUSPEND_AARCH32 0x84000001 #define PSCI_CPU_SUSPEND_AARCH64 0xc4000001 #define PSCI_CPU_OFF 0x84000002 #define PSCI_CPU_ON_AARCH32 0x84000003 #define PSCI_CPU_ON_AARCH64 0xc4000003 #define PSCI_AFFINITY_INFO_AARCH32 0x84000004 #define PSCI_AFFINITY_INFO_AARCH64 0xc4000004 #define PSCI_MIG_AARCH32 0x84000005 #define PSCI_MIG_AARCH64 0xc4000005 #define PSCI_MIG_INFO_TYPE 0x84000006 #define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 #define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 #define PSCI_SYSTEM_OFF 0x84000008 #define PSCI_SYSTEM_RESET 0x84000009 /* * Number of PSCI calls (above) implemented */ #define PSCI_NUM_CALLS 15 /******************************************************************************* * PSCI Migrate and friends ******************************************************************************/ #define PSCI_TOS_UP_MIG_CAP 0 #define PSCI_TOS_NOT_UP_MIG_CAP 1 #define PSCI_TOS_NOT_PRESENT_MP 2 /******************************************************************************* * PSCI CPU_SUSPEND 'power_state' parameter specific defines ******************************************************************************/ #define PSTATE_ID_SHIFT 0 #define PSTATE_TYPE_SHIFT 16 #define PSTATE_AFF_LVL_SHIFT 24 #define PSTATE_ID_MASK 0xffff #define PSTATE_TYPE_MASK 0x1 #define PSTATE_AFF_LVL_MASK 0x3 #define PSTATE_VALID_MASK 0xFCFE0000 #define PSTATE_TYPE_STANDBY 0x0 #define PSTATE_TYPE_POWERDOWN 0x1 #define psci_get_pstate_id(pstate) (pstate >> PSTATE_ID_SHIFT) & \ PSTATE_ID_MASK #define psci_get_pstate_type(pstate) (pstate >> PSTATE_TYPE_SHIFT) & \ PSTATE_TYPE_MASK #define psci_get_pstate_afflvl(pstate) (pstate >> PSTATE_AFF_LVL_SHIFT) & \ PSTATE_AFF_LVL_MASK /******************************************************************************* * PSCI version ******************************************************************************/ #define PSCI_MAJOR_VER (0 << 16) #define PSCI_MINOR_VER 0x2 /******************************************************************************* * PSCI error codes ******************************************************************************/ #define PSCI_E_SUCCESS 0 #define PSCI_E_NOT_SUPPORTED -1 #define PSCI_E_INVALID_PARAMS -2 #define PSCI_E_DENIED -3 #define PSCI_E_ALREADY_ON -4 #define PSCI_E_ON_PENDING -5 #define PSCI_E_INTERN_FAIL -6 #define PSCI_E_NOT_PRESENT -7 #define PSCI_E_DISABLED -8 /******************************************************************************* * PSCI affinity state related constants. An affinity instance could be present * or absent physically to cater for asymmetric topologies. If present then it * could in one of the 4 further defined states. ******************************************************************************/ #define PSCI_STATE_SHIFT 1 #define PSCI_STATE_MASK 0xff #define PSCI_AFF_ABSENT 0x0 #define PSCI_AFF_PRESENT 0x1 #define PSCI_STATE_ON 0x0 #define PSCI_STATE_OFF 0x1 #define PSCI_STATE_ON_PENDING 0x2 #define PSCI_STATE_SUSPEND 0x3 #define PSCI_INVALID_DATA -1 #define get_phys_state(x) (x != PSCI_STATE_ON ? \ PSCI_STATE_OFF : PSCI_STATE_ON) #define psci_validate_power_state(pstate) (pstate & PSTATE_VALID_MASK) #ifndef __ASSEMBLY__ #include /******************************************************************************* * Structure used to store per-cpu information relevant to the PSCI service. * It is populated in the per-cpu data array. In return we get a guarantee that * this information will not reside on a cache line shared with another cpu. ******************************************************************************/ typedef struct psci_cpu_data { uint32_t power_state; uint32_t max_phys_off_afflvl; /* Highest affinity level in physically powered off state */ } psci_cpu_data_t; /******************************************************************************* * Structure populated by platform specific code to export routines which * perform common low level pm functions ******************************************************************************/ typedef struct plat_pm_ops { int (*affinst_standby)(unsigned int); int (*affinst_on)(unsigned long, unsigned long, unsigned long, unsigned int, unsigned int); int (*affinst_off)(unsigned long, unsigned int, unsigned int); int (*affinst_suspend)(unsigned long, unsigned long, unsigned long, unsigned int, unsigned int); int (*affinst_on_finish)(unsigned long, unsigned int, unsigned int); int (*affinst_suspend_finish)(unsigned long, unsigned int, unsigned int); void (*core_power_down_wfi)(unsigned long); void (*system_off)(void) __dead2; void (*system_reset)(void) __dead2; } plat_pm_ops_t; /******************************************************************************* * Optional structure populated by the Secure Payload Dispatcher to be given a * chance to perform any bookkeeping before PSCI executes a power mgmt. * operation. It also allows PSCI to determine certain properties of the SP e.g. * migrate capability etc. ******************************************************************************/ typedef struct spd_pm_ops { void (*svc_on)(uint64_t target_cpu); int32_t (*svc_off)(uint64_t __unused); void (*svc_suspend)(uint64_t power_state); void (*svc_on_finish)(uint64_t __unused); void (*svc_suspend_finish)(uint64_t suspend_level); void (*svc_migrate)(uint64_t __unused1, uint64_t __unused2); int32_t (*svc_migrate_info)(uint64_t *__unused); void (*svc_system_off)(void); void (*svc_system_reset)(void); } spd_pm_ops_t; /******************************************************************************* * Function & Data prototypes ******************************************************************************/ unsigned int psci_version(void); int psci_affinity_info(unsigned long, unsigned int); int psci_migrate(unsigned int); unsigned int psci_migrate_info_type(void); unsigned long psci_migrate_info_up_cpu(void); int psci_cpu_on(unsigned long, unsigned long, unsigned long); void __dead2 psci_power_down_wfi(void); void psci_aff_on_finish_entry(void); void psci_aff_suspend_finish_entry(void); void psci_register_spd_pm_hook(const spd_pm_ops_t *); int psci_get_suspend_stateid_by_mpidr(unsigned long); int psci_get_suspend_stateid(void); int psci_get_suspend_afflvl(void); uint32_t psci_get_max_phys_off_afflvl(void); uint64_t psci_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags); /* PSCI setup function */ int32_t psci_setup(void); #endif /*__ASSEMBLY__*/ #endif /* __PSCI_H__ */ arm-trusted-firmware-1.0-aw-6/include/bl31/services/std_svc.h000066400000000000000000000041751322600646200240400ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __STD_SVC_H__ #define __STD_SVC_H__ /* SMC function IDs for Standard Service queries */ #define ARM_STD_SVC_CALL_COUNT 0x8400ff00 #define ARM_STD_SVC_UID 0x8400ff01 /* 0x8400ff02 is reserved */ #define ARM_STD_SVC_VERSION 0x8400ff03 /* ARM Standard Service Calls version numbers */ #define STD_SVC_VERSION_MAJOR 0x0 #define STD_SVC_VERSION_MINOR 0x1 /* The macros below are used to identify PSCI calls from the SMC function ID */ #define PSCI_FID_MASK 0xffe0u #define PSCI_FID_VALUE 0u #define is_psci_fid(_fid) \ (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) #endif /* __STD_SVC_H__ */ arm-trusted-firmware-1.0-aw-6/include/bl32/000077500000000000000000000000001322600646200203715ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/bl32/tsp/000077500000000000000000000000001322600646200211775ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/bl32/tsp/platform_tsp.h000066400000000000000000000036271322600646200240720ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PLATFORM_TSP_H__ /******************************************************************************* * Mandatory TSP functions (only if platform contains a TSP) ******************************************************************************/ void tsp_early_platform_setup(void); void tsp_plat_arch_setup(void); void tsp_platform_setup(void); #define __PLATFORM_H__ #endif arm-trusted-firmware-1.0-aw-6/include/bl32/tsp/tsp.h000066400000000000000000000104131322600646200221550ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TSP_H__ #define __TSP_H__ /* * SMC function IDs that TSP uses to signal various forms of completions * to the secure payload dispatcher. */ #define TSP_ENTRY_DONE 0xf2000000 #define TSP_ON_DONE 0xf2000001 #define TSP_OFF_DONE 0xf2000002 #define TSP_SUSPEND_DONE 0xf2000003 #define TSP_RESUME_DONE 0xf2000004 #define TSP_PREEMPTED 0xf2000005 #define TSP_SYSTEM_OFF_DONE 0xf2000008 #define TSP_SYSTEM_RESET_DONE 0xf2000009 /* * Function identifiers to handle FIQs through the synchronous handling model. * If the TSP was previously interrupted then control has to be returned to * the TSPD after handling the interrupt else execution can remain in the TSP. */ #define TSP_HANDLED_S_EL1_FIQ 0xf2000006 #define TSP_EL3_FIQ 0xf2000007 /* SMC function ID that TSP uses to request service from secure monitor */ #define TSP_GET_ARGS 0xf2001000 /* * Identifiers for various TSP services. Corresponding function IDs (whether * fast or standard) are generated by macros defined below */ #define TSP_ADD 0x2000 #define TSP_SUB 0x2001 #define TSP_MUL 0x2002 #define TSP_DIV 0x2003 #define TSP_HANDLE_FIQ_AND_RETURN 0x2004 /* * Generate function IDs for TSP services to be used in SMC calls, by * appropriately setting bit 31 to differentiate standard and fast SMC calls */ #define TSP_STD_FID(fid) ((fid) | 0x72000000 | (0 << 31)) #define TSP_FAST_FID(fid) ((fid) | 0x72000000 | (1 << 31)) /* SMC function ID to request a previously preempted std smc */ #define TSP_FID_RESUME TSP_STD_FID(0x3000) /* * Identify a TSP service from function ID filtering the last 16 bits from the * SMC function ID */ #define TSP_BARE_FID(fid) ((fid) & 0xffff) /* * Total number of function IDs implemented for services offered to NS clients. * The function IDs are defined above */ #define TSP_NUM_FID 0x4 /* TSP implementation version numbers */ #define TSP_VERSION_MAJOR 0x0 /* Major version */ #define TSP_VERSION_MINOR 0x1 /* Minor version */ /* * Standard Trusted OS Function IDs that fall under Trusted OS call range * according to SMC calling convention */ #define TOS_CALL_COUNT 0xbf00ff00 /* Number of calls implemented */ #define TOS_UID 0xbf00ff01 /* Implementation UID */ /* 0xbf00ff02 is reserved */ #define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */ #ifndef __ASSEMBLY__ #include typedef uint32_t tsp_vector_isn_t; typedef struct tsp_vectors { tsp_vector_isn_t std_smc_entry; tsp_vector_isn_t fast_smc_entry; tsp_vector_isn_t cpu_on_entry; tsp_vector_isn_t cpu_off_entry; tsp_vector_isn_t cpu_resume_entry; tsp_vector_isn_t cpu_suspend_entry; tsp_vector_isn_t fiq_entry; tsp_vector_isn_t system_off_entry; tsp_vector_isn_t system_reset_entry; } tsp_vectors_t; #endif /* __ASSEMBLY__ */ #endif /* __TSP_H__ */ arm-trusted-firmware-1.0-aw-6/include/common/000077500000000000000000000000001322600646200211175ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/common/asm_macros.S000066400000000000000000000130541322600646200233720ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include .macro func_prologue stp x29, x30, [sp, #-0x10]! mov x29,sp .endm .macro func_epilogue ldp x29, x30, [sp], #0x10 .endm .macro dcache_line_size reg, tmp mrs \tmp, ctr_el0 ubfx \tmp, \tmp, #16, #4 mov \reg, #4 lsl \reg, \reg, \tmp .endm .macro icache_line_size reg, tmp mrs \tmp, ctr_el0 and \tmp, \tmp, #0xf mov \reg, #4 lsl \reg, \reg, \tmp .endm .macro smc_check label mrs x0, esr_el3 ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH cmp x0, #EC_AARCH64_SMC b.ne $label .endm /* * This macro verifies that the a given vector doesn't exceed the * architectural limit of 32 instructions. This is meant to be placed * immedately after the last instruction in the vector. It takes the * vector entry as the parameter */ .macro check_vector_size since .if (. - \since) > (32 * 4) .error "Vector exceeds 32 instructions" .endif .endm /* * This macro is used to create a function label and place the * code into a separate text section based on the function name * to enable elimination of unused code during linking */ .macro func _name .section .text.\_name, "ax" .type \_name, %function \_name: .endm /* --------------------------------------------- * Find the type of reset and jump to handler * if present. If the handler is null then it is * a cold boot. The primary cpu will set up the * platform while the secondaries wait for * their turn to be woken up * --------------------------------------------- */ .macro wait_for_entrypoint wait_for_entrypoint: mrs x0, mpidr_el1 bl platform_get_entrypoint cbnz x0, do_warm_boot mrs x0, mpidr_el1 bl platform_is_primary_cpu cbnz x0, do_cold_boot /* --------------------------------------------- * Perform any platform specific secondary cpu * actions * --------------------------------------------- */ bl plat_secondary_cold_boot_setup b wait_for_entrypoint do_warm_boot: /* --------------------------------------------- * Jump to BL31 for all warm boot init. * --------------------------------------------- */ blr x0 do_cold_boot: .endm /* * This macro declares an array of 1 or more stacks, properly * aligned and in the requested section */ #define STACK_ALIGN 6 .macro declare_stack _name, _section, _size, _count .if ((\_size & ((1 << STACK_ALIGN) - 1)) <> 0) .error "Stack size not correctly aligned" .endif .section \_section, "aw", %nobits .align STACK_ALIGN \_name: .space ((\_count) * (\_size)), 0 .endm /* * This macro calculates the base address of an MP stack using the * platform_get_core_pos() index, the name of the stack storage and * the size of each stack * In: X0 = MPIDR of CPU whose stack is wanted * Out: X0 = physical address of stack base * Clobber: X30, X1, X2 */ .macro get_mp_stack _name, _size bl platform_get_core_pos ldr x2, =(\_name + \_size) mov x1, #\_size madd x0, x0, x1, x2 .endm /* * This macro calculates the base address of a UP stack using the * name of the stack storage and the size of the stack * Out: X0 = physical address of stack base */ .macro get_up_stack _name, _size ldr x0, =(\_name + \_size) .endm /* * Helper macro to generate the best mov/movk combinations according * the value to be moved. The 16 bits from '_shift' are tested and * if not zero, they are moved into '_reg' without affecting * other bits. */ .macro _mov_imm16 _reg, _val, _shift .if (\_val >> \_shift) & 0xffff .if (\_val & (1 << \_shift - 1)) movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift .else mov \_reg, \_val & (0xffff << \_shift) .endif .endif .endm /* * Helper macro to load arbitrary values into 32 or 64-bit registers * which generates the best mov/movk combinations. Many base addresses * are 64KB aligned the macro will eliminate updating bits 15:0 in * that case */ .macro mov_imm _reg, _val .if (\_val) == 0 mov \_reg, #0 .else _mov_imm16 \_reg, (\_val), 0 _mov_imm16 \_reg, (\_val), 16 _mov_imm16 \_reg, (\_val), 32 _mov_imm16 \_reg, (\_val), 48 .endif .endm arm-trusted-firmware-1.0-aw-6/include/common/assert_macros.S000066400000000000000000000040751322600646200241160ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * Assembler macro to enable asm_assert. Use this macro wherever * assert is required in assembly. Please note that the macro makes * use of label '300' to provide the logic and the caller * should make sure that this label is not used to branch prior * to calling this macro. */ #define ASM_ASSERT(_cc) \ .ifndef .L_assert_filename ;\ .pushsection .rodata.str1.1, "aS" ;\ .L_assert_filename: ;\ .string __FILE__ ;\ .popsection ;\ .endif ;\ b._cc 300f ;\ adr x0, .L_assert_filename ;\ mov x1, __LINE__ ;\ b asm_assert ;\ 300: arm-trusted-firmware-1.0-aw-6/include/common/bl_common.h000066400000000000000000000210731322600646200232400ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __BL_COMMON_H__ #define __BL_COMMON_H__ #define SECURE 0x0 #define NON_SECURE 0x1 #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE)) #define UP 1 #define DOWN 0 /******************************************************************************* * Constants to identify the location of a memory region in a given memory * layout. ******************************************************************************/ #define TOP 0x1 #define BOTTOM !TOP /****************************************************************************** * Opcode passed in x0 to tell next EL that we want to run an image. * Corresponds to the function ID of the only SMC that the BL1 exception * handlers service. That's why the chosen value is the first function ID of * the ARM SMC64 range. *****************************************************************************/ #define RUN_IMAGE 0xC0000000 /******************************************************************************* * Constants that allow assembler code to access members of and the * 'entry_point_info' structure at their correct offsets. ******************************************************************************/ #define ENTRY_POINT_INFO_PC_OFFSET 0x08 #define ENTRY_POINT_INFO_ARGS_OFFSET 0x18 #define PARAM_EP_SECURITY_MASK 0x1 #define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) #define SET_SECURITY_STATE(x, security) \ ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) #define EP_EE_MASK 0x2 #define EP_EE_LITTLE 0x0 #define EP_EE_BIG 0x2 #define EP_GET_EE(x) (x & EP_EE_MASK) #define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) #define EP_ST_MASK 0x4 #define EP_ST_DISABLE 0x0 #define EP_ST_ENABLE 0x4 #define EP_GET_ST(x) (x & EP_ST_MASK) #define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) #define PARAM_EP 0x01 #define PARAM_IMAGE_BINARY 0x02 #define PARAM_BL31 0x03 #define VERSION_1 0x01 #define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \ (_p)->h.type = (uint8_t)(_type); \ (_p)->h.version = (uint8_t)(_ver); \ (_p)->h.size = (uint16_t)sizeof(*_p); \ (_p)->h.attr = (uint32_t)(_attr) ; \ } while (0) #ifndef __ASSEMBLY__ #include /* For __dead2 */ #include #include #include /******************************************************************************* * Structure used for telling the next BL how much of a particular type of * memory is available for its use and how much is already used. ******************************************************************************/ typedef struct meminfo { uint64_t total_base; size_t total_size; uint64_t free_base; size_t free_size; } meminfo_t; typedef struct aapcs64_params { unsigned long arg0; unsigned long arg1; unsigned long arg2; unsigned long arg3; unsigned long arg4; unsigned long arg5; unsigned long arg6; unsigned long arg7; } aapcs64_params_t; /*************************************************************************** * This structure provides version information and the size of the * structure, attributes for the structure it represents ***************************************************************************/ typedef struct param_header { uint8_t type; /* type of the structure */ uint8_t version; /* version of this structure */ uint16_t size; /* size of this structure in bytes */ uint32_t attr; /* attributes: unused bits SBZ */ } param_header_t; /***************************************************************************** * This structure represents the superset of information needed while * switching exception levels. The only two mechanisms to do so are * ERET & SMC. Security state is indicated using bit zero of header * attribute * NOTE: BL1 expects entrypoint followed by spsr while processing * SMC to jump to BL31 from the start of entry_point_info *****************************************************************************/ typedef struct entry_point_info { param_header_t h; uintptr_t pc; uint32_t spsr; aapcs64_params_t args; } entry_point_info_t; /***************************************************************************** * Image info binary provides information from the image loader that * can be used by the firmware to manage available trusted RAM. * More advanced firmware image formats can provide additional * information that enables optimization or greater flexibility in the * common firmware code *****************************************************************************/ typedef struct image_info { param_header_t h; uintptr_t image_base; /* physical address of base of image */ uint32_t image_size; /* bytes read from image file */ } image_info_t; /******************************************************************************* * This structure represents the superset of information that can be passed to * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be * populated only if BL2 detects its presence. A pointer to a structure of this * type should be passed in X3 to BL31's cold boot entrypoint * * Use of this structure and the X3 parameter is not mandatory: the BL3-1 * platform code can use other mechanisms to provide the necessary information * about BL3-2 and BL3-3 to the common and SPD code. * * BL3-1 image information is mandatory if this structure is used. If either of * the optional BL3-2 and BL3-3 image information is not provided, this is * indicated by the respective image_info pointers being zero. ******************************************************************************/ typedef struct bl31_params { param_header_t h; image_info_t *bl31_image_info; entry_point_info_t *bl32_ep_info; image_info_t *bl32_image_info; entry_point_info_t *bl33_ep_info; image_info_t *bl33_image_info; } bl31_params_t; /* * Compile time assertions related to the 'entry_point_info' structure to * ensure that the assembler and the compiler view of the offsets of * the structure members is the same. */ CASSERT(ENTRY_POINT_INFO_PC_OFFSET == __builtin_offsetof(entry_point_info_t, pc), \ assert_BL31_pc_offset_mismatch); CASSERT(ENTRY_POINT_INFO_ARGS_OFFSET == \ __builtin_offsetof(entry_point_info_t, args), \ assert_BL31_args_offset_mismatch); CASSERT(sizeof(unsigned long) == __builtin_offsetof(entry_point_info_t, spsr) - \ __builtin_offsetof(entry_point_info_t, pc), \ assert_entrypoint_and_spsr_should_be_adjacent); /******************************************************************************* * Function & variable prototypes ******************************************************************************/ unsigned long page_align(unsigned long, unsigned); void change_security_state(unsigned int); unsigned long image_size(const char *); int load_image(meminfo_t *mem_layout, const char *image_name, uint64_t image_base, image_info_t *image_data, entry_point_info_t *entry_point_info); extern const char build_message[]; extern const char version_string[]; void reserve_mem(uint64_t *free_base, size_t *free_size, uint64_t addr, size_t size); #endif /*__ASSEMBLY__*/ #endif /* __BL_COMMON_H__ */ arm-trusted-firmware-1.0-aw-6/include/common/debug.h000066400000000000000000000056501322600646200223640ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __DEBUG_H__ #define __DEBUG_H__ #include /* The log output macros print output to the console. These macros produce * compiled log output only if the LOG_LEVEL defined in the makefile (or the * make command line) is greater or equal than the level required for that * type of log output. * The format expected is the same as for printf(). For example: * INFO("Info %s.\n", "message") -> INFO: Info message. * WARN("Warning %s.\n", "message") -> WARNING: Warning message. */ #define LOG_LEVEL_NONE 0 #define LOG_LEVEL_ERROR 10 #define LOG_LEVEL_NOTICE 20 #define LOG_LEVEL_WARNING 30 #define LOG_LEVEL_INFO 40 #define LOG_LEVEL_VERBOSE 50 #if LOG_LEVEL >= LOG_LEVEL_NOTICE # define NOTICE(...) tf_printf("NOTICE: " __VA_ARGS__) #else # define NOTICE(...) #endif #if LOG_LEVEL >= LOG_LEVEL_ERROR # define ERROR(...) tf_printf("ERROR: " __VA_ARGS__) #else # define ERROR(...) #endif #if LOG_LEVEL >= LOG_LEVEL_WARNING # define WARN(...) tf_printf("WARNING: " __VA_ARGS__) #else # define WARN(...) #endif #if LOG_LEVEL >= LOG_LEVEL_INFO # define INFO(...) tf_printf("INFO: " __VA_ARGS__) #else # define INFO(...) #endif #if LOG_LEVEL >= LOG_LEVEL_VERBOSE # define VERBOSE(...) tf_printf("VERBOSE: " __VA_ARGS__) #else # define VERBOSE(...) #endif void __dead2 do_panic(void); #define panic() do_panic() void tf_printf(const char *fmt, ...); #endif /* __DEBUG_H__ */ arm-trusted-firmware-1.0-aw-6/include/common/firmware_image_package.h000066400000000000000000000051541322600646200257260ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __FIRMWARE_IMAGE_PACKAGE_H__ #define __FIRMWARE_IMAGE_PACKAGE_H__ #include #include /* This is used as a signature to validate the blob header */ #define TOC_HEADER_NAME 0xAA640001 /* ToC Entry UUIDs */ #define UUID_TRUSTED_BOOT_FIRMWARE_BL2 \ {0x0becf95f, 0x224d, 0x4d3e, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} } #define UUID_SCP_FIRMWARE_BL30 \ {0x3dfd6697, 0xbe89, 0x49e8, 0xae, 0x5d, {0x78, 0xa1, 0x40, 0x60, 0x82, 0x13} } #define UUID_EL3_RUNTIME_FIRMWARE_BL31 \ {0x6d08d447, 0xfe4c, 0x4698, 0x9b, 0x95, {0x29, 0x50, 0xcb, 0xbd, 0x5a, 0x00} } #define UUID_SECURE_PAYLOAD_BL32 \ {0x89e1d005, 0xdc53, 0x4713, 0x8d, 0x2b, {0x50, 0x0a, 0x4b, 0x7a, 0x3e, 0x38} } #define UUID_NON_TRUSTED_FIRMWARE_BL33 \ {0xa7eed0d6, 0xeafc, 0x4bd5, 0x97, 0x82, {0x99, 0x34, 0xf2, 0x34, 0xb6, 0xe4} } typedef struct fip_toc_header { uint32_t name; uint32_t serial_number; uint64_t flags; } fip_toc_header_t; typedef struct fip_toc_entry { uuid_t uuid; uint64_t offset_address; uint64_t size; uint64_t flags; } fip_toc_entry_t; #endif /* __FIRMWARE_IMAGE_PACKAGE_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/000077500000000000000000000000001322600646200213055ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/drivers/arm/000077500000000000000000000000001322600646200220645ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/drivers/arm/arm_gic.h000066400000000000000000000046221322600646200236420ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ARM_GIC_H__ #define __ARM_GIC_H__ #include /******************************************************************************* * Function declarations ******************************************************************************/ void arm_gic_init(unsigned int gicc_base, unsigned int gicd_base, unsigned long gicr_base, const unsigned int *irq_sec_ptr, unsigned int num_irqs); void arm_gic_setup(void); void arm_gic_cpuif_deactivate(void); void arm_gic_cpuif_setup(void); void arm_gic_pcpu_distif_setup(void); uint32_t arm_gic_interrupt_type_to_line(uint32_t type, uint32_t security_state); uint32_t arm_gic_get_pending_interrupt_type(void); uint32_t arm_gic_get_pending_interrupt_id(void); uint32_t arm_gic_acknowledge_interrupt(void); void arm_gic_end_of_interrupt(uint32_t id); uint32_t arm_gic_get_interrupt_type(uint32_t id); #endif /* __GIC_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/arm/cci400.h000066400000000000000000000066331322600646200232270ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CCI_400_H__ #define __CCI_400_H__ /* Slave interface offsets from PERIPHBASE */ #define SLAVE_IFACE4_OFFSET 0x5000 #define SLAVE_IFACE3_OFFSET 0x4000 #define SLAVE_IFACE2_OFFSET 0x3000 #define SLAVE_IFACE1_OFFSET 0x2000 #define SLAVE_IFACE0_OFFSET 0x1000 #define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + \ (0x1000 * (index)) /* Control and ID register offsets */ #define CTRL_OVERRIDE_REG 0x0 #define SPEC_CTRL_REG 0x4 #define SECURE_ACCESS_REG 0x8 #define STATUS_REG 0xc #define IMPRECISE_ERR_REG 0x10 #define PERFMON_CTRL_REG 0x100 /* Slave interface register offsets */ #define SNOOP_CTRL_REG 0x0 #define SH_OVERRIDE_REG 0x4 #define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 #define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 #define QOS_CTRL_REG 0x10c #define MAX_OT_REG 0x110 #define TARGET_LATENCY_REG 0x130 #define LATENCY_REGULATION_REG 0x134 #define QOS_RANGE_REG 0x138 /* Snoop Control register bit definitions */ #define DVM_EN_BIT (1 << 1) #define SNOOP_EN_BIT (1 << 0) /* Status register bit definitions */ #define CHANGE_PENDING_BIT (1 << 0) #ifndef __ASSEMBLY__ /* Function declarations */ /* * The CCI-400 driver must be initialized with the base address of the * CCI-400 device in the platform memory map, and the cluster indices for * the CCI-400 slave interfaces 3 and 4 respectively. These are the fully * coherent ACE slave interfaces of CCI-400. * The cluster indices must either be 0 or 1, corresponding to the level 1 * affinity instance of the mpidr representing the cluster. A negative cluster * index indicates that no cluster is present on that slave interface. */ void cci_init(unsigned long cci_base, int slave_iface3_cluster_ix, int slave_iface4_cluster_ix); void cci_enable_cluster_coherency(unsigned long mpidr); void cci_disable_cluster_coherency(unsigned long mpidr); #endif /* __ASSEMBLY__ */ #endif /* __CCI_400_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/arm/gic_v2.h000066400000000000000000000241661322600646200234170ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GIC_V2_H__ #define __GIC_V2_H__ #define GIC400_NUM_SPIS 480 #define MAX_PPIS 14 #define MAX_SGIS 16 #define MIN_SGI_ID 0 #define MIN_PPI_ID 16 #define MIN_SPI_ID 32 #define GRP0 0 #define GRP1 1 #define GIC_PRI_MASK 0xff #define GIC_HIGHEST_SEC_PRIORITY 0 #define GIC_LOWEST_SEC_PRIORITY 127 #define GIC_HIGHEST_NS_PRIORITY 128 #define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ #define GIC_SPURIOUS_INTERRUPT 1023 #define ENABLE_GRP0 (1 << 0) #define ENABLE_GRP1 (1 << 1) /* Distributor interface definitions */ #define GICD_CTLR 0x0 #define GICD_TYPER 0x4 #define GICD_IGROUPR 0x80 #define GICD_ISENABLER 0x100 #define GICD_ICENABLER 0x180 #define GICD_ISPENDR 0x200 #define GICD_ICPENDR 0x280 #define GICD_ISACTIVER 0x300 #define GICD_ICACTIVER 0x380 #define GICD_IPRIORITYR 0x400 #define GICD_ITARGETSR 0x800 #define GICD_ICFGR 0xC00 #define GICD_SGIR 0xF00 #define GICD_CPENDSGIR 0xF10 #define GICD_SPENDSGIR 0xF20 #define IGROUPR_SHIFT 5 #define ISENABLER_SHIFT 5 #define ICENABLER_SHIFT ISENABLER_SHIFT #define ISPENDR_SHIFT 5 #define ICPENDR_SHIFT ISPENDR_SHIFT #define ISACTIVER_SHIFT 5 #define ICACTIVER_SHIFT ISACTIVER_SHIFT #define IPRIORITYR_SHIFT 2 #define ITARGETSR_SHIFT 2 #define ICFGR_SHIFT 4 #define CPENDSGIR_SHIFT 2 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT /* GICD_TYPER bit definitions */ #define IT_LINES_NO_MASK 0x1f /* Physical CPU Interface registers */ #define GICC_CTLR 0x0 #define GICC_PMR 0x4 #define GICC_BPR 0x8 #define GICC_IAR 0xC #define GICC_EOIR 0x10 #define GICC_RPR 0x14 #define GICC_HPPIR 0x18 #define GICC_AHPPIR 0x28 #define GICC_IIDR 0xFC #define GICC_DIR 0x1000 #define GICC_PRIODROP GICC_EOIR /* GICC_CTLR bit definitions */ #define EOI_MODE_NS (1 << 10) #define EOI_MODE_S (1 << 9) #define IRQ_BYP_DIS_GRP1 (1 << 8) #define FIQ_BYP_DIS_GRP1 (1 << 7) #define IRQ_BYP_DIS_GRP0 (1 << 6) #define FIQ_BYP_DIS_GRP0 (1 << 5) #define CBPR (1 << 4) #define FIQ_EN (1 << 3) #define ACK_CTL (1 << 2) /* GICC_IIDR bit masks and shifts */ #define GICC_IIDR_PID_SHIFT 20 #define GICC_IIDR_ARCH_SHIFT 16 #define GICC_IIDR_REV_SHIFT 12 #define GICC_IIDR_IMP_SHIFT 0 #define GICC_IIDR_PID_MASK 0xfff #define GICC_IIDR_ARCH_MASK 0xf #define GICC_IIDR_REV_MASK 0xf #define GICC_IIDR_IMP_MASK 0xfff /* HYP view virtual CPU Interface registers */ #define GICH_CTL 0x0 #define GICH_VTR 0x4 #define GICH_ELRSR0 0x30 #define GICH_ELRSR1 0x34 #define GICH_APR0 0xF0 #define GICH_LR_BASE 0x100 /* Virtual CPU Interface registers */ #define GICV_CTL 0x0 #define GICV_PRIMASK 0x4 #define GICV_BP 0x8 #define GICV_INTACK 0xC #define GICV_EOI 0x10 #define GICV_RUNNINGPRI 0x14 #define GICV_HIGHESTPEND 0x18 #define GICV_DEACTIVATE 0x1000 #ifndef __ASSEMBLY__ #include /******************************************************************************* * GIC Distributor function prototypes ******************************************************************************/ unsigned int gicd_read_igroupr(unsigned int, unsigned int); unsigned int gicd_read_isenabler(unsigned int, unsigned int); unsigned int gicd_read_icenabler(unsigned int, unsigned int); unsigned int gicd_read_ispendr(unsigned int, unsigned int); unsigned int gicd_read_icpendr(unsigned int, unsigned int); unsigned int gicd_read_isactiver(unsigned int, unsigned int); unsigned int gicd_read_icactiver(unsigned int, unsigned int); unsigned int gicd_read_ipriorityr(unsigned int, unsigned int); unsigned int gicd_read_itargetsr(unsigned int, unsigned int); unsigned int gicd_read_icfgr(unsigned int, unsigned int); unsigned int gicd_read_cpendsgir(unsigned int, unsigned int); unsigned int gicd_read_spendsgir(unsigned int, unsigned int); void gicd_write_igroupr(unsigned int, unsigned int, unsigned int); void gicd_write_isenabler(unsigned int, unsigned int, unsigned int); void gicd_write_icenabler(unsigned int, unsigned int, unsigned int); void gicd_write_ispendr(unsigned int, unsigned int, unsigned int); void gicd_write_icpendr(unsigned int, unsigned int, unsigned int); void gicd_write_isactiver(unsigned int, unsigned int, unsigned int); void gicd_write_icactiver(unsigned int, unsigned int, unsigned int); void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int); void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int); void gicd_write_icfgr(unsigned int, unsigned int, unsigned int); void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int); void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int); unsigned int gicd_get_igroupr(unsigned int, unsigned int); void gicd_set_igroupr(unsigned int, unsigned int); void gicd_clr_igroupr(unsigned int, unsigned int); void gicd_set_isenabler(unsigned int, unsigned int); void gicd_set_icenabler(unsigned int, unsigned int); void gicd_set_ispendr(unsigned int, unsigned int); void gicd_set_icpendr(unsigned int, unsigned int); void gicd_set_isactiver(unsigned int, unsigned int); void gicd_set_icactiver(unsigned int, unsigned int); void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int); void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int); /******************************************************************************* * GIC Distributor interface accessors for reading entire registers ******************************************************************************/ static inline unsigned int gicd_read_ctlr(unsigned int base) { return mmio_read_32(base + GICD_CTLR); } static inline unsigned int gicd_read_typer(unsigned int base) { return mmio_read_32(base + GICD_TYPER); } static inline unsigned int gicd_read_sgir(unsigned int base) { return mmio_read_32(base + GICD_SGIR); } /******************************************************************************* * GIC Distributor interface accessors for writing entire registers ******************************************************************************/ static inline void gicd_write_ctlr(unsigned int base, unsigned int val) { mmio_write_32(base + GICD_CTLR, val); } static inline void gicd_write_sgir(unsigned int base, unsigned int val) { mmio_write_32(base + GICD_SGIR, val); } /******************************************************************************* * GIC CPU interface accessors for reading entire registers ******************************************************************************/ static inline unsigned int gicc_read_ctlr(unsigned int base) { return mmio_read_32(base + GICC_CTLR); } static inline unsigned int gicc_read_pmr(unsigned int base) { return mmio_read_32(base + GICC_PMR); } static inline unsigned int gicc_read_BPR(unsigned int base) { return mmio_read_32(base + GICC_BPR); } static inline unsigned int gicc_read_IAR(unsigned int base) { return mmio_read_32(base + GICC_IAR); } static inline unsigned int gicc_read_EOIR(unsigned int base) { return mmio_read_32(base + GICC_EOIR); } static inline unsigned int gicc_read_hppir(unsigned int base) { return mmio_read_32(base + GICC_HPPIR); } static inline unsigned int gicc_read_ahppir(unsigned int base) { return mmio_read_32(base + GICC_AHPPIR); } static inline unsigned int gicc_read_dir(unsigned int base) { return mmio_read_32(base + GICC_DIR); } static inline unsigned int gicc_read_iidr(unsigned int base) { return mmio_read_32(base + GICC_IIDR); } /******************************************************************************* * GIC CPU interface accessors for writing entire registers ******************************************************************************/ static inline void gicc_write_ctlr(unsigned int base, unsigned int val) { mmio_write_32(base + GICC_CTLR, val); } static inline void gicc_write_pmr(unsigned int base, unsigned int val) { mmio_write_32(base + GICC_PMR, val); } static inline void gicc_write_BPR(unsigned int base, unsigned int val) { mmio_write_32(base + GICC_BPR, val); } static inline void gicc_write_IAR(unsigned int base, unsigned int val) { mmio_write_32(base + GICC_IAR, val); } static inline void gicc_write_EOIR(unsigned int base, unsigned int val) { mmio_write_32(base + GICC_EOIR, val); } static inline void gicc_write_hppir(unsigned int base, unsigned int val) { mmio_write_32(base + GICC_HPPIR, val); } static inline void gicc_write_dir(unsigned int base, unsigned int val) { mmio_write_32(base + GICC_DIR, val); } /******************************************************************************* * Prototype of function to map an interrupt type to the interrupt line used to * signal it. ******************************************************************************/ uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type); #endif /*__ASSEMBLY__*/ #endif /* __GIC_V2_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/arm/gic_v3.h000066400000000000000000000063231322600646200234130ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __GIC_V3_H__ #define __GIC_V3_H__ #include #include /* GICv3 Re-distributor interface registers & shifts */ #define GICR_PCPUBASE_SHIFT 0x11 #define GICR_TYPER 0x08 #define GICR_WAKER 0x14 /* GICR_WAKER bit definitions */ #define WAKER_CA (1UL << 2) #define WAKER_PS (1UL << 1) /* GICR_TYPER bit definitions */ #define GICR_TYPER_AFF_SHIFT 32 #define GICR_TYPER_AFF_MASK 0xffffffff #define GICR_TYPER_LAST (1UL << 4) /* GICv3 ICC_SRE register bit definitions*/ #define ICC_SRE_EN (1UL << 3) #define ICC_SRE_SRE (1UL << 0) /******************************************************************************* * GICv3 defintions ******************************************************************************/ #define GICV3_AFFLVL_MASK 0xff #define GICV3_AFF0_SHIFT 0 #define GICV3_AFF1_SHIFT 8 #define GICV3_AFF2_SHIFT 16 #define GICV3_AFF3_SHIFT 24 #define GICV3_AFFINITY_MASK 0xffffffff /******************************************************************************* * Function prototypes ******************************************************************************/ uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr); /******************************************************************************* * GIC Redistributor interface accessors ******************************************************************************/ static inline uint32_t gicr_read_waker(uintptr_t base) { return mmio_read_32(base + GICR_WAKER); } static inline void gicr_write_waker(uintptr_t base, uint32_t val) { mmio_write_32(base + GICR_WAKER, val); } static inline uint64_t gicr_read_typer(uintptr_t base) { return mmio_read_64(base + GICR_TYPER); } #endif /* __GIC_V3_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/arm/pl011.h000066400000000000000000000106351322600646200230770ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PL011_H__ #define __PL011_H__ /* PL011 Registers */ #define UARTDR 0x000 #define UARTRSR 0x004 #define UARTECR 0x004 #define UARTFR 0x018 #define UARTILPR 0x020 #define UARTIBRD 0x024 #define UARTFBRD 0x028 #define UARTLCR_H 0x02C #define UARTCR 0x030 #define UARTIFLS 0x034 #define UARTIMSC 0x038 #define UARTRIS 0x03C #define UARTMIS 0x040 #define UARTICR 0x044 #define UARTDMACR 0x048 /* Data status bits */ #define UART_DATA_ERROR_MASK 0x0F00 /* Status reg bits */ #define UART_STATUS_ERROR_MASK 0x0F /* Flag reg bits */ #define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ #define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ #define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ #define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ #define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ #define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ #define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ #define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ #define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ #define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */ #define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */ /* Control reg bits */ #define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ #define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ #define PL011_UARTCR_RTS (1 << 11) /* Request to send */ #define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ #define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ #define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ #define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ #define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ #if !defined(PL011_LINE_CONTROL) /* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ #define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) #endif /* Line Control Register Bits */ #define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ #define PL011_UARTLCR_H_WLEN_8 (3 << 5) #define PL011_UARTLCR_H_WLEN_7 (2 << 5) #define PL011_UARTLCR_H_WLEN_6 (1 << 5) #define PL011_UARTLCR_H_WLEN_5 (0 << 5) #define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ #define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ #define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ #define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ #define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ #endif /* __PL011_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/arm/tzc400.h000066400000000000000000000147421322600646200232710ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TZC400_H__ #define __TZC400_H__ #include #define BUILD_CONFIG_OFF 0x000 #define ACTION_OFF 0x004 #define GATE_KEEPER_OFF 0x008 #define SPECULATION_CTRL_OFF 0x00c #define INT_STATUS 0x010 #define INT_CLEAR 0x014 #define FAIL_ADDRESS_LOW_OFF 0x020 #define FAIL_ADDRESS_HIGH_OFF 0x024 #define FAIL_CONTROL_OFF 0x028 #define FAIL_ID 0x02c #define REGION_BASE_LOW_OFF 0x100 #define REGION_BASE_HIGH_OFF 0x104 #define REGION_TOP_LOW_OFF 0x108 #define REGION_TOP_HIGH_OFF 0x10c #define REGION_ATTRIBUTES_OFF 0x110 #define REGION_ID_ACCESS_OFF 0x114 #define REGION_NUM_OFF(region) (0x20 * region) /* ID Registers */ #define PID0_OFF 0xfe0 #define PID1_OFF 0xfe4 #define PID2_OFF 0xfe8 #define PID3_OFF 0xfec #define PID4_OFF 0xfd0 #define PID5_OFF 0xfd4 #define PID6_OFF 0xfd8 #define PID7_OFF 0xfdc #define CID0_OFF 0xff0 #define CID1_OFF 0xff4 #define CID2_OFF 0xff8 #define CID3_OFF 0xffc #define BUILD_CONFIG_NF_SHIFT 24 #define BUILD_CONFIG_NF_MASK 0x3 #define BUILD_CONFIG_AW_SHIFT 8 #define BUILD_CONFIG_AW_MASK 0x3f #define BUILD_CONFIG_NR_SHIFT 0 #define BUILD_CONFIG_NR_MASK 0x1f /* Not describing the case where regions 1 to 8 overlap */ #define ACTION_RV_SHIFT 0 #define ACTION_RV_MASK 0x3 #define ACTION_RV_LOWOK 0x0 #define ACTION_RV_LOWERR 0x1 #define ACTION_RV_HIGHOK 0x2 #define ACTION_RV_HIGHERR 0x3 /* * Number of gate keepers is implementation defined. But we know the max for * this device is 4. Get implementation details from BUILD_CONFIG. */ #define GATE_KEEPER_OS_SHIFT 16 #define GATE_KEEPER_OS_MASK 0xf #define GATE_KEEPER_OR_SHIFT 0 #define GATE_KEEPER_OR_MASK 0xf #define GATE_KEEPER_FILTER_MASK 0x1 /* Speculation is enabled by default. */ #define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) #define SPECULATION_CTRL_READ_DISABLE (1 << 0) /* Max number of filters allowed is 4. */ #define INT_STATUS_OVERLAP_SHIFT 16 #define INT_STATUS_OVERLAP_MASK 0xf #define INT_STATUS_OVERRUN_SHIFT 8 #define INT_STATUS_OVERRUN_MASK 0xf #define INT_STATUS_STATUS_SHIFT 0 #define INT_STATUS_STATUS_MASK 0xf #define INT_CLEAR_CLEAR_SHIFT 0 #define INT_CLEAR_CLEAR_MASK 0xf #define FAIL_CONTROL_DIR_SHIFT (1 << 24) #define FAIL_CONTROL_DIR_READ 0x0 #define FAIL_CONTROL_DIR_WRITE 0x1 #define FAIL_CONTROL_NS_SHIFT (1 << 21) #define FAIL_CONTROL_NS_SECURE 0x0 #define FAIL_CONTROL_NS_NONSECURE 0x1 #define FAIL_CONTROL_PRIV_SHIFT (1 << 20) #define FAIL_CONTROL_PRIV_PRIV 0x0 #define FAIL_CONTROL_PRIV_UNPRIV 0x1 /* * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. * Platform should provide the value on initialisation. */ #define FAIL_ID_VNET_SHIFT 24 #define FAIL_ID_VNET_MASK 0xf #define FAIL_ID_ID_SHIFT 0 /* Used along with 'tzc_region_attributes_t' below */ #define REGION_ATTRIBUTES_SEC_SHIFT 30 #define REGION_ATTRIBUTES_F_EN_SHIFT 0 #define REGION_ATTRIBUTES_F_EN_MASK 0xf #define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 #define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 #define REGION_ID_ACCESS_NSAID_ID_MASK 0xf /* Macros for setting Region ID access permissions based on NSAID */ #define TZC_REGION_ACCESS_RD(id) \ ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) #define TZC_REGION_ACCESS_WR(id) \ ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) #define TZC_REGION_ACCESS_RDWR(id) \ (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) /* Filters are bit mapped 0 to 3. */ #define TZC400_COMPONENT_ID 0xb105f00d /******************************************************************************* * Function & variable prototypes ******************************************************************************/ /* * What type of action is expected when an access violation occurs. * The memory requested is zeroed. But we can also raise and event to * let the system know it happened. * We can raise an interrupt(INT) and/or cause an exception(ERR). * TZC_ACTION_NONE - No interrupt, no Exception * TZC_ACTION_ERR - No interrupt, raise exception -> sync external * data abort * TZC_ACTION_INT - Raise interrupt, no exception * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync * external data abort */ typedef enum { TZC_ACTION_NONE = 0, TZC_ACTION_ERR = 1, TZC_ACTION_INT = 2, TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) } tzc_action_t; /* * Controls secure access to a region. If not enabled secure access is not * allowed to region. */ typedef enum { TZC_REGION_S_NONE = 0, TZC_REGION_S_RD = 1, TZC_REGION_S_WR = 2, TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) } tzc_region_attributes_t; void tzc_init(uint64_t base); void tzc_configure_region(uint32_t filters, uint8_t region, uint64_t region_base, uint64_t region_top, tzc_region_attributes_t sec_attr, uint32_t ns_device_access); void tzc_enable_filters(void); void tzc_disable_filters(void); void tzc_set_action(tzc_action_t action); #endif /* __TZC400__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/console.h000066400000000000000000000034121322600646200231200ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CONSOLE_H__ #define __CONSOLE_H__ int console_init(unsigned long base_addr, unsigned int uart_clk, unsigned int baud_rate); int console_exit(void); int console_putc(int c); int console_getc(void); #endif /* __CONSOLE_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/io/000077500000000000000000000000001322600646200217145ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/drivers/io/io_driver.h000066400000000000000000000061621322600646200240540ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __IO_DRIVER_H__ #define __IO_DRIVER_H__ #include #include /* Generic IO entity structure,representing an accessible IO construct on the * device, such as a file */ typedef struct io_entity { struct io_dev_info *dev_handle; uintptr_t info; } io_entity_t; /* Device info structure, providing device-specific functions and a means of * adding driver-specific state */ typedef struct io_dev_info { const struct io_dev_funcs *funcs; uintptr_t info; } io_dev_info_t; /* Structure used to create a connection to a type of device */ typedef struct io_dev_connector { /* dev_open opens a connection to a particular device driver */ int (*dev_open)(const uintptr_t dev_spec, io_dev_info_t **dev_info); } io_dev_connector_t; /* Structure to hold device driver function pointers */ typedef struct io_dev_funcs { io_type_t (*type)(void); int (*open)(io_dev_info_t *dev_info, const uintptr_t spec, io_entity_t *entity); int (*seek)(io_entity_t *entity, int mode, ssize_t offset); int (*size)(io_entity_t *entity, size_t *length); int (*read)(io_entity_t *entity, uintptr_t buffer, size_t length, size_t *length_read); int (*write)(io_entity_t *entity, const uintptr_t buffer, size_t length, size_t *length_written); int (*close)(io_entity_t *entity); int (*dev_init)(io_dev_info_t *dev_info, const uintptr_t init_params); int (*dev_close)(io_dev_info_t *dev_info); } io_dev_funcs_t; /* Operations intended to be performed during platform initialisation */ /* Register an IO device */ int io_register_device(const io_dev_info_t *dev_info); #endif /* __IO_DRIVER_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/io/io_fip.h000066400000000000000000000032671322600646200233420ustar00rootroot00000000000000/* * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __IO_FIP_H__ #define __IO_FIP_H__ struct io_dev_connector; int register_io_dev_fip(const struct io_dev_connector **dev_con); #endif /* __IO_FIP_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/io/io_memmap.h000066400000000000000000000033041322600646200240300ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __IO_MEMMAP_H__ #define __IO_MEMMAP_H__ struct io_dev_connector; int register_io_dev_memmap(const struct io_dev_connector **dev_con); #endif /* __IO_MEMMAP_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/io/io_semihosting.h000066400000000000000000000032641322600646200251120ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __IO_SH_H__ #define __IO_SH_H__ struct io_dev_connector; int register_io_dev_sh(const struct io_dev_connector **dev_con); #endif /* __IO_SH_H__ */ arm-trusted-firmware-1.0-aw-6/include/drivers/io/io_storage.h000066400000000000000000000072311322600646200242230ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __IO_H__ #define __IO_H__ #include #include /* For ssize_t */ /* Device type which can be used to enable policy decisions about which device * to access */ typedef enum { IO_TYPE_INVALID, IO_TYPE_SEMIHOSTING, IO_TYPE_MEMMAP, IO_TYPE_FIRMWARE_IMAGE_PACKAGE, IO_TYPE_MAX } io_type_t; /* Modes used when seeking data on a supported device */ typedef enum { IO_SEEK_INVALID, IO_SEEK_SET, IO_SEEK_END, IO_SEEK_CUR, IO_SEEK_MAX } io_seek_mode_t; /* Connector type, providing a means of identifying a device to open */ struct io_dev_connector; /* File specification - used to refer to data on a device supporting file-like * entities */ typedef struct io_file_spec { const char *path; unsigned int mode; } io_file_spec_t; /* Block specification - used to refer to data on a device supporting * block-like entities */ typedef struct io_block_spec { size_t offset; size_t length; } io_block_spec_t; /* Access modes used when accessing data on a device */ #define IO_MODE_INVALID (0) #define IO_MODE_RO (1 << 0) #define IO_MODE_RW (1 << 1) /* Return codes reported by 'io_*' APIs */ #define IO_SUCCESS (0) #define IO_FAIL (-1) #define IO_NOT_SUPPORTED (-2) #define IO_RESOURCES_EXHAUSTED (-3) /* Open a connection to a device */ int io_dev_open(const struct io_dev_connector *dev_con, const uintptr_t dev_spec, uintptr_t *dev_handle); /* Initialise a device explicitly - to permit lazy initialisation or * re-initialisation */ int io_dev_init(uintptr_t dev_handle, const uintptr_t init_params); /* TODO: Consider whether an explicit "shutdown" API should be included */ /* Close a connection to a device */ int io_dev_close(uintptr_t dev_handle); /* Synchronous operations */ int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle); int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset); int io_size(uintptr_t handle, size_t *length); int io_read(uintptr_t handle, uintptr_t buffer, size_t length, size_t *length_read); int io_write(uintptr_t handle, const uintptr_t buffer, size_t length, size_t *length_written); int io_close(uintptr_t handle); #endif /* __IO_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/000077500000000000000000000000001322600646200203755ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/lib/aarch64/000077500000000000000000000000001322600646200216255ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/lib/aarch64/arch.h000066400000000000000000000330021322600646200227110ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ARCH_H__ #define __ARCH_H__ /******************************************************************************* * MIDR bit definitions ******************************************************************************/ #define MIDR_IMPL_MASK 0xff #define MIDR_IMPL_SHIFT 0x18 #define MIDR_VAR_SHIFT 20 #define MIDR_REV_SHIFT 0 #define MIDR_PN_MASK 0xfff #define MIDR_PN_SHIFT 0x4 /******************************************************************************* * MPIDR macros ******************************************************************************/ #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK #define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS #define MPIDR_AFFINITY_BITS 8 #define MPIDR_AFFLVL_MASK 0xff #define MPIDR_AFF0_SHIFT 0 #define MPIDR_AFF1_SHIFT 8 #define MPIDR_AFF2_SHIFT 16 #define MPIDR_AFF3_SHIFT 32 #define MPIDR_AFFINITY_MASK 0xff00ffffff #define MPIDR_AFFLVL_SHIFT 3 #define MPIDR_AFFLVL0 0 #define MPIDR_AFFLVL1 1 #define MPIDR_AFFLVL2 2 #define MPIDR_AFFLVL3 3 /* TODO: Support only the first 3 affinity levels for now */ #define MPIDR_MAX_AFFLVL 2 /* Constant to highlight the assumption that MPIDR allocation starts from 0 */ #define FIRST_MPIDR 0 /******************************************************************************* * Definitions for CPU system register interface to GICv3 ******************************************************************************/ #define ICC_SRE_EL1 S3_0_C12_C12_5 #define ICC_SRE_EL2 S3_4_C12_C9_5 #define ICC_SRE_EL3 S3_6_C12_C12_5 #define ICC_CTLR_EL1 S3_0_C12_C12_4 #define ICC_CTLR_EL3 S3_6_C12_C12_4 #define ICC_PMR_EL1 S3_0_C4_C6_0 /******************************************************************************* * Generic timer memory mapped registers & offsets ******************************************************************************/ #define CNTCR_OFF 0x000 #define CNTFID_OFF 0x020 #define CNTCR_EN (1 << 0) #define CNTCR_HDBG (1 << 1) #define CNTCR_FCREQ(x) ((x) << 8) /******************************************************************************* * System register bit definitions ******************************************************************************/ /* CLIDR definitions */ #define LOUIS_SHIFT 21 #define LOC_SHIFT 24 #define CLIDR_FIELD_WIDTH 3 /* CSSELR definitions */ #define LEVEL_SHIFT 1 /* D$ set/way op type defines */ #define DCISW 0x0 #define DCCISW 0x1 #define DCCSW 0x2 /* ID_AA64PFR0_EL1 definitions */ #define ID_AA64PFR0_EL0_SHIFT 0 #define ID_AA64PFR0_EL1_SHIFT 4 #define ID_AA64PFR0_EL2_SHIFT 8 #define ID_AA64PFR0_EL3_SHIFT 12 #define ID_AA64PFR0_ELX_MASK 0xf /* ID_PFR1_EL1 definitions */ #define ID_PFR1_VIRTEXT_SHIFT 12 #define ID_PFR1_VIRTEXT_MASK 0xf #define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ & ID_PFR1_VIRTEXT_MASK) /* SCTLR definitions */ #define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ (1 << 4)) #define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ (1 << 11)) #define SCTLR_M_BIT (1 << 0) #define SCTLR_A_BIT (1 << 1) #define SCTLR_C_BIT (1 << 2) #define SCTLR_SA_BIT (1 << 3) #define SCTLR_I_BIT (1 << 12) #define SCTLR_WXN_BIT (1 << 19) #define SCTLR_EE_BIT (1 << 25) /* CPACR_El1 definitions */ #define CPACR_EL1_FPEN(x) (x << 20) #define CPACR_EL1_FP_TRAP_EL0 0x1 #define CPACR_EL1_FP_TRAP_ALL 0x2 #define CPACR_EL1_FP_TRAP_NONE 0x3 /* SCR definitions */ #define SCR_RES1_BITS ((1 << 4) | (1 << 5)) #define SCR_TWE_BIT (1 << 13) #define SCR_TWI_BIT (1 << 12) #define SCR_ST_BIT (1 << 11) #define SCR_RW_BIT (1 << 10) #define SCR_SIF_BIT (1 << 9) #define SCR_HCE_BIT (1 << 8) #define SCR_SMD_BIT (1 << 7) #define SCR_EA_BIT (1 << 3) #define SCR_FIQ_BIT (1 << 2) #define SCR_IRQ_BIT (1 << 1) #define SCR_NS_BIT (1 << 0) #define SCR_VALID_BIT_MASK 0x2f8f /* HCR definitions */ #define HCR_RW_BIT (1ull << 31) #define HCR_AMO_BIT (1 << 5) #define HCR_IMO_BIT (1 << 4) #define HCR_FMO_BIT (1 << 3) /* CNTHCTL_EL2 definitions */ #define EVNTEN_BIT (1 << 2) #define EL1PCEN_BIT (1 << 1) #define EL1PCTEN_BIT (1 << 0) /* CNTKCTL_EL1 definitions */ #define EL0PTEN_BIT (1 << 9) #define EL0VTEN_BIT (1 << 8) #define EL0PCTEN_BIT (1 << 0) #define EL0VCTEN_BIT (1 << 1) #define EVNTEN_BIT (1 << 2) #define EVNTDIR_BIT (1 << 3) #define EVNTI_SHIFT 4 #define EVNTI_MASK 0xf /* CPTR_EL3 definitions */ #define TCPAC_BIT (1 << 31) #define TTA_BIT (1 << 20) #define TFP_BIT (1 << 10) /* CPSR/SPSR definitions */ #define DAIF_FIQ_BIT (1 << 0) #define DAIF_IRQ_BIT (1 << 1) #define DAIF_ABT_BIT (1 << 2) #define DAIF_DBG_BIT (1 << 3) #define SPSR_DAIF_SHIFT 6 #define SPSR_DAIF_MASK 0xf #define SPSR_AIF_SHIFT 6 #define SPSR_AIF_MASK 0x7 #define SPSR_E_SHIFT 9 #define SPSR_E_MASK 0x1 #define SPSR_E_LITTLE 0x0 #define SPSR_E_BIG 0x1 #define SPSR_T_SHIFT 5 #define SPSR_T_MASK 0x1 #define SPSR_T_ARM 0x0 #define SPSR_T_THUMB 0x1 #define DISABLE_ALL_EXCEPTIONS \ (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) /* * TCR defintions */ #define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) #define TCR_EL1_IPS_SHIFT 32 #define TCR_EL3_PS_SHIFT 16 /* (internal) physical address size bits in EL3/EL1 */ #define TCR_PS_BITS_4GB (0x0) #define TCR_PS_BITS_64GB (0x1) #define TCR_PS_BITS_1TB (0x2) #define TCR_PS_BITS_4TB (0x3) #define TCR_PS_BITS_16TB (0x4) #define TCR_PS_BITS_256TB (0x5) #define ADDR_MASK_48_TO_63 0xFFFF000000000000UL #define ADDR_MASK_44_TO_47 0x0000F00000000000UL #define ADDR_MASK_42_TO_43 0x00000C0000000000UL #define ADDR_MASK_40_TO_41 0x0000030000000000UL #define ADDR_MASK_36_TO_39 0x000000F000000000UL #define ADDR_MASK_32_TO_35 0x0000000F00000000UL #define TCR_RGN_INNER_NC (0x0 << 8) #define TCR_RGN_INNER_WBA (0x1 << 8) #define TCR_RGN_INNER_WT (0x2 << 8) #define TCR_RGN_INNER_WBNA (0x3 << 8) #define TCR_RGN_OUTER_NC (0x0 << 10) #define TCR_RGN_OUTER_WBA (0x1 << 10) #define TCR_RGN_OUTER_WT (0x2 << 10) #define TCR_RGN_OUTER_WBNA (0x3 << 10) #define TCR_SH_NON_SHAREABLE (0x0 << 12) #define TCR_SH_OUTER_SHAREABLE (0x2 << 12) #define TCR_SH_INNER_SHAREABLE (0x3 << 12) #define MODE_SP_SHIFT 0x0 #define MODE_SP_MASK 0x1 #define MODE_SP_EL0 0x0 #define MODE_SP_ELX 0x1 #define MODE_RW_SHIFT 0x4 #define MODE_RW_MASK 0x1 #define MODE_RW_64 0x0 #define MODE_RW_32 0x1 #define MODE_EL_SHIFT 0x2 #define MODE_EL_MASK 0x3 #define MODE_EL3 0x3 #define MODE_EL2 0x2 #define MODE_EL1 0x1 #define MODE_EL0 0x0 #define MODE32_SHIFT 0 #define MODE32_MASK 0xf #define MODE32_usr 0x0 #define MODE32_fiq 0x1 #define MODE32_irq 0x2 #define MODE32_svc 0x3 #define MODE32_mon 0x6 #define MODE32_abt 0x7 #define MODE32_hyp 0xa #define MODE32_und 0xb #define MODE32_sys 0xf #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) #define SPSR_64(el, sp, daif) \ (MODE_RW_64 << MODE_RW_SHIFT | \ ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) #define SPSR_MODE32(mode, isa, endian, aif) \ (MODE_RW_32 << MODE_RW_SHIFT | \ ((mode) & MODE32_MASK) << MODE32_SHIFT | \ ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) /* Physical timer control register bit fields shifts and masks */ #define CNTP_CTL_ENABLE_SHIFT 0 #define CNTP_CTL_IMASK_SHIFT 1 #define CNTP_CTL_ISTATUS_SHIFT 2 #define CNTP_CTL_ENABLE_MASK 1 #define CNTP_CTL_IMASK_MASK 1 #define CNTP_CTL_ISTATUS_MASK 1 #define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \ CNTP_CTL_ENABLE_MASK) #define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \ CNTP_CTL_IMASK_MASK) #define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \ CNTP_CTL_ISTATUS_MASK) #define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT) #define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT) #define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT)) #define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT)) /* Miscellaneous MMU related constants */ #define NUM_2MB_IN_GB (1 << 9) #define NUM_4K_IN_2MB (1 << 9) #define NUM_GB_IN_4GB (1 << 2) #define TWO_MB_SHIFT 21 #define ONE_GB_SHIFT 30 #define FOUR_KB_SHIFT 12 #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) #define INVALID_DESC 0x0 #define BLOCK_DESC 0x1 #define TABLE_DESC 0x3 #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT #define LEVEL1 1 #define LEVEL2 2 #define LEVEL3 3 #define XN (1ull << 2) #define PXN (1ull << 1) #define CONT_HINT (1ull << 0) #define UPPER_ATTRS(x) (x & 0x7) << 52 #define NON_GLOBAL (1 << 9) #define ACCESS_FLAG (1 << 8) #define NSH (0x0 << 6) #define OSH (0x2 << 6) #define ISH (0x3 << 6) #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT #define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) #define PAGE_SIZE_MASK (PAGE_SIZE - 1) #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) #define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ #define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT #define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) /* Values for number of entries in each MMU translation table */ #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) #define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) /* Values to convert a memory address to an index into a translation table */ #define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) /* * AP[1] bit is ignored by hardware and is * treated as if it is One in EL2/EL3 */ #define AP_RO (0x1 << 5) #define AP_RW (0x0 << 5) #define NS (0x1 << 3) #define ATTR_SO_INDEX 0x2 #define ATTR_DEVICE_INDEX 0x1 #define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 #define LOWER_ATTRS(x) (((x) & 0xfff) << 2) #define ATTR_SO (0x0) #define ATTR_DEVICE (0x4) #define ATTR_IWBWA_OWBWA_NTR (0xff) #define MAIR_ATTR_SET(attr, index) (attr << (index << 3)) /* Exception Syndrome register bits and bobs */ #define ESR_EC_SHIFT 26 #define ESR_EC_MASK 0x3f #define ESR_EC_LENGTH 6 #define EC_UNKNOWN 0x0 #define EC_WFE_WFI 0x1 #define EC_AARCH32_CP15_MRC_MCR 0x3 #define EC_AARCH32_CP15_MRRC_MCRR 0x4 #define EC_AARCH32_CP14_MRC_MCR 0x5 #define EC_AARCH32_CP14_LDC_STC 0x6 #define EC_FP_SIMD 0x7 #define EC_AARCH32_CP10_MRC 0x8 #define EC_AARCH32_CP14_MRRC_MCRR 0xc #define EC_ILLEGAL 0xe #define EC_AARCH32_SVC 0x11 #define EC_AARCH32_HVC 0x12 #define EC_AARCH32_SMC 0x13 #define EC_AARCH64_SVC 0x15 #define EC_AARCH64_HVC 0x16 #define EC_AARCH64_SMC 0x17 #define EC_AARCH64_SYS 0x18 #define EC_IABORT_LOWER_EL 0x20 #define EC_IABORT_CUR_EL 0x21 #define EC_PC_ALIGN 0x22 #define EC_DABORT_LOWER_EL 0x24 #define EC_DABORT_CUR_EL 0x25 #define EC_SP_ALIGN 0x26 #define EC_AARCH32_FP 0x28 #define EC_AARCH64_FP 0x2c #define EC_SERROR 0x2f #define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK /******************************************************************************* * Definitions of register offsets and fields in the CNTCTLBase Frame of the * system level implementation of the Generic Timer. ******************************************************************************/ #define CNTNSAR 0x4 #define CNTNSAR_NS_SHIFT(x) x #define CNTACR_BASE(x) (0x40 + (x << 2)) #define CNTACR_RPCT_SHIFT 0x0 #define CNTACR_RVCT_SHIFT 0x1 #define CNTACR_RFRQ_SHIFT 0x2 #define CNTACR_RVOFF_SHIFT 0x3 #define CNTACR_RWVT_SHIFT 0x4 #define CNTACR_RWPT_SHIFT 0x5 #endif /* __ARCH_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/aarch64/arch_helpers.h000066400000000000000000000241151322600646200244400ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __ARCH_HELPERS_H__ #define __ARCH_HELPERS_H__ #include /* for additional register definitions */ #include /* For __dead2 */ #include /********************************************************************** * Macros which create inline functions to read or write CPU system * registers *********************************************************************/ #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ static inline uint64_t read_ ## _name(void) \ { \ uint64_t v; \ __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ return v; \ } #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ static inline void write_ ## _name(uint64_t v) \ { \ __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ } #define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \ static inline void write_ ## _name(const uint64_t v) \ { \ __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \ } /* Define read function for system register */ #define DEFINE_SYSREG_READ_FUNC(_name) \ _DEFINE_SYSREG_READ_FUNC(_name, _name) /* Define read & write function for system register */ #define DEFINE_SYSREG_RW_FUNCS(_name) \ _DEFINE_SYSREG_READ_FUNC(_name, _name) \ _DEFINE_SYSREG_WRITE_FUNC(_name, _name) /* Define read & write function for renamed system register */ #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) /* Define write function for special system registers */ #define DEFINE_SYSREG_WRITE_CONST_FUNC(_name) \ _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _name) /********************************************************************** * Macros to create inline functions for system instructions *********************************************************************/ /* Define function for simple system instruction */ #define DEFINE_SYSOP_FUNC(_op) \ static inline void _op(void) \ { \ __asm__ (#_op); \ } /* Define function for system instruction with type specifier */ #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ static inline void _op ## _type(void) \ { \ __asm__ (#_op " " #_type); \ } /* Define function for system instruction with register parameter */ #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ static inline void _op ## _type(uint64_t v) \ { \ __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ } /******************************************************************************* * Aarch64 translation tables manipulation helper prototypes ******************************************************************************/ uint64_t create_table_desc(uint64_t *next_table_ptr); uint64_t create_block_desc(uint64_t desc, uint64_t addr, uint32_t level); uint64_t create_device_block(uint64_t output_addr, uint32_t level, uint32_t ns); uint64_t create_romem_block(uint64_t output_addr, uint32_t level, uint32_t ns); uint64_t create_rwmem_block(uint64_t output_addr, uint32_t level, uint32_t ns); /******************************************************************************* * TLB maintenance accessor prototypes ******************************************************************************/ DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) /******************************************************************************* * Cache maintenance accessor prototypes ******************************************************************************/ DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) void flush_dcache_range(uint64_t, uint64_t); void inv_dcache_range(uint64_t, uint64_t); void dcsw_op_louis(uint32_t); void dcsw_op_all(uint32_t); void disable_mmu_el3(void); void disable_mmu_icache_el3(void); /******************************************************************************* * Misc. accessor prototypes ******************************************************************************/ DEFINE_SYSREG_WRITE_CONST_FUNC(daifset) DEFINE_SYSREG_WRITE_CONST_FUNC(daifclr) #define enable_irq() write_daifclr(DAIF_IRQ_BIT) #define enable_fiq() write_daifclr(DAIF_FIQ_BIT) #define enable_serror() write_daifclr(DAIF_ABT_BIT) #define enable_debug_exceptions() write_daifclr(DAIF_DBG_BIT) #define disable_irq() write_daifset(DAIF_IRQ_BIT) #define disable_fiq() write_daifset(DAIF_FIQ_BIT) #define disable_serror() write_daifset(DAIF_ABT_BIT) #define disable_debug_exceptions() write_daifset(DAIF_DBG_BIT) DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) DEFINE_SYSREG_READ_FUNC(CurrentEl) DEFINE_SYSREG_RW_FUNCS(daif) DEFINE_SYSREG_RW_FUNCS(spsr_el1) DEFINE_SYSREG_RW_FUNCS(spsr_el2) DEFINE_SYSREG_RW_FUNCS(spsr_el3) DEFINE_SYSREG_RW_FUNCS(elr_el1) DEFINE_SYSREG_RW_FUNCS(elr_el2) DEFINE_SYSREG_RW_FUNCS(elr_el3) DEFINE_SYSOP_FUNC(wfi) DEFINE_SYSOP_FUNC(wfe) DEFINE_SYSOP_FUNC(sev) DEFINE_SYSOP_TYPE_FUNC(dsb, sy) DEFINE_SYSOP_FUNC(isb) uint32_t get_afflvl_shift(uint32_t); uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t); void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); /******************************************************************************* * System register accessor prototypes ******************************************************************************/ DEFINE_SYSREG_READ_FUNC(midr_el1) DEFINE_SYSREG_READ_FUNC(mpidr_el1) DEFINE_SYSREG_RW_FUNCS(scr_el3) DEFINE_SYSREG_RW_FUNCS(hcr_el2) DEFINE_SYSREG_RW_FUNCS(vbar_el1) DEFINE_SYSREG_RW_FUNCS(vbar_el2) DEFINE_SYSREG_RW_FUNCS(vbar_el3) DEFINE_SYSREG_RW_FUNCS(sctlr_el1) DEFINE_SYSREG_RW_FUNCS(sctlr_el2) DEFINE_SYSREG_RW_FUNCS(sctlr_el3) DEFINE_SYSREG_RW_FUNCS(actlr_el1) DEFINE_SYSREG_RW_FUNCS(actlr_el2) DEFINE_SYSREG_RW_FUNCS(actlr_el3) DEFINE_SYSREG_RW_FUNCS(esr_el1) DEFINE_SYSREG_RW_FUNCS(esr_el2) DEFINE_SYSREG_RW_FUNCS(esr_el3) DEFINE_SYSREG_RW_FUNCS(afsr0_el1) DEFINE_SYSREG_RW_FUNCS(afsr0_el2) DEFINE_SYSREG_RW_FUNCS(afsr0_el3) DEFINE_SYSREG_RW_FUNCS(afsr1_el1) DEFINE_SYSREG_RW_FUNCS(afsr1_el2) DEFINE_SYSREG_RW_FUNCS(afsr1_el3) DEFINE_SYSREG_RW_FUNCS(far_el1) DEFINE_SYSREG_RW_FUNCS(far_el2) DEFINE_SYSREG_RW_FUNCS(far_el3) DEFINE_SYSREG_RW_FUNCS(mair_el1) DEFINE_SYSREG_RW_FUNCS(mair_el2) DEFINE_SYSREG_RW_FUNCS(mair_el3) DEFINE_SYSREG_RW_FUNCS(amair_el1) DEFINE_SYSREG_RW_FUNCS(amair_el2) DEFINE_SYSREG_RW_FUNCS(amair_el3) DEFINE_SYSREG_READ_FUNC(rvbar_el1) DEFINE_SYSREG_READ_FUNC(rvbar_el2) DEFINE_SYSREG_READ_FUNC(rvbar_el3) DEFINE_SYSREG_RW_FUNCS(rmr_el1) DEFINE_SYSREG_RW_FUNCS(rmr_el2) DEFINE_SYSREG_RW_FUNCS(rmr_el3) DEFINE_SYSREG_RW_FUNCS(tcr_el1) DEFINE_SYSREG_RW_FUNCS(tcr_el2) DEFINE_SYSREG_RW_FUNCS(tcr_el3) DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) DEFINE_SYSREG_RW_FUNCS(cptr_el2) DEFINE_SYSREG_RW_FUNCS(cptr_el3) DEFINE_SYSREG_RW_FUNCS(cpacr_el1) DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) DEFINE_SYSREG_READ_FUNC(cntpct_el0) DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) DEFINE_SYSREG_RW_FUNCS(tpidr_el3) DEFINE_SYSREG_RW_FUNCS(vpidr_el2) DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) /* GICv3 System Registers */ DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) #define IS_IN_EL(x) \ (GET_EL(read_CurrentEl()) == MODE_EL##x) #define IS_IN_EL1() IS_IN_EL(1) #define IS_IN_EL3() IS_IN_EL(3) /* Previously defined accesor functions with incomplete register names */ #define read_current_el() read_CurrentEl() #define dsb() dsbsy() #define read_midr() read_midr_el1() #define read_mpidr() read_mpidr_el1() #define read_scr() read_scr_el3() #define write_scr(_v) write_scr_el3(_v) #define read_hcr() read_hcr_el2() #define write_hcr(_v) write_hcr_el2(_v) #define read_cpacr() read_cpacr_el1() #define write_cpacr(_v) write_cpacr_el1(_v) #endif /* __ARCH_HELPERS_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/aarch64/xlat_tables.h000066400000000000000000000052771322600646200243130ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __XLAT_TABLES_H__ #define __XLAT_TABLES_H__ /* * Flags to override default values used to program system registers while * enabling the MMU. */ #define DISABLE_DCACHE (1 << 0) #ifndef __ASSEMBLY__ #include /* * Flags for building up memory mapping attributes. * These are organised so that a clear bit gives a more restrictive mapping * that a set bit, that way a bitwise-and two sets of attributes will never give * an attribute which has greater access rights that any of the original * attributes. */ typedef enum { MT_DEVICE = 0 << 0, MT_MEMORY = 1 << 0, MT_RO = 0 << 1, MT_RW = 1 << 1, MT_SECURE = 0 << 2, MT_NS = 1 << 2 } mmap_attr_t; /* * Structure for specifying a single region of memory. */ typedef struct mmap_region { unsigned long base_pa; unsigned long base_va; unsigned long size; mmap_attr_t attr; } mmap_region_t; void mmap_add_region(unsigned long base_pa, unsigned long base_va, unsigned long size, unsigned attr); void mmap_add(const mmap_region_t *mm); void init_xlat_tables(void); void enable_mmu_el1(uint32_t flags); void enable_mmu_el3(uint32_t flags); #endif /*__ASSEMBLY__*/ #endif /* __XLAT_TABLES_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/bakery_lock.h000066400000000000000000000040501322600646200230320ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __BAKERY_LOCK_H__ #define __BAKERY_LOCK_H__ #include #define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT typedef struct bakery_lock { int owner; volatile char entering[BAKERY_LOCK_MAX_CPUS]; volatile unsigned number[BAKERY_LOCK_MAX_CPUS]; } bakery_lock_t; #define NO_OWNER (-1) void bakery_lock_init(bakery_lock_t *bakery); void bakery_lock_get(bakery_lock_t *bakery); void bakery_lock_release(bakery_lock_t *bakery); int bakery_lock_try(bakery_lock_t *bakery); #endif /* __BAKERY_LOCK_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/cassert.h000066400000000000000000000040731322600646200222160ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CASSERT_H__ #define __CASSERT_H__ /******************************************************************************* * Macro to flag a compile time assertion. It uses the preprocessor to generate * an invalid C construct if 'cond' evaluates to false. * The following compilation error is triggered if the assertion fails: * "error: size of array 'msg' is negative" ******************************************************************************/ #define CASSERT(cond, msg) typedef char msg[(cond) ? 1 : -1] #endif /* __CASSERT_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/cpus/000077500000000000000000000000001322600646200213475ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/lib/cpus/aarch64/000077500000000000000000000000001322600646200225775ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/lib/cpus/aarch64/aem_generic.h000066400000000000000000000034021322600646200252050ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __AEM_GENERIC_H__ #define __AEM_GENERIC_H__ /* BASE AEM midr for revision 0 */ #define BASE_AEM_MIDR 0x410FD0F0 /* Foundation AEM midr for revision 0 */ #define FOUNDATION_AEM_MIDR 0x410FD000 #endif /* __AEM_GENERIC_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/cpus/aarch64/cortex_a53.h000066400000000000000000000037521322600646200247330ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CORTEX_A53_H__ #define __CORTEX_A53_H__ /* Cortex-A53 midr for revision 0 */ #define CORTEX_A53_MIDR 0x410FD030 /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ #define CPUECTLR_SMP_BIT (1 << 6) #endif /* __CORTEX_A53_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/cpus/aarch64/cortex_a57.h000066400000000000000000000056431322600646200247400ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __CORTEX_A57_H__ #define __CORTEX_A57_H__ /* Cortex-A57 midr for revision 0 */ #define CORTEX_A57_MIDR 0x410FD070 /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ #define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ #define CPUECTLR_SMP_BIT (1 << 6) #define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) #define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) #define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ #define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) /******************************************************************************* * L2 Control register specific definitions. ******************************************************************************/ #define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ #define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 #define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 #define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 #define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 #endif /* __CORTEX_A57_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/cpus/aarch64/cpu_macros.S000066400000000000000000000054551322600646200250670ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ (MIDR_PN_MASK << MIDR_PN_SHIFT) /* * Define the offsets to the fields in cpu_ops structure. */ .struct 0 CPU_MIDR: /* cpu_ops midr */ .space 8 /* Reset fn is needed in BL at reset vector */ #if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) CPU_RESET_FUNC: /* cpu_ops reset_func */ .space 8 #endif #if IMAGE_BL31 /* The power down core and cluster is needed only in BL3-1 */ CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */ .space 8 CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */ .space 8 #endif #if (IMAGE_BL31 && CRASH_REPORTING) CPU_REG_DUMP: /* cpu specific register dump for crash reporting */ .space 8 #endif CPU_OPS_SIZE = . /* * Convenience macro to declare cpu_ops structure. * Make sure the structure fields are as per the offsets * defined above. */ .macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0 .section cpu_ops, "a"; .align 3 .type cpu_ops_\_name, %object .quad \_midr #if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) .if \_noresetfunc .quad 0 .else .quad \_name\()_reset_func .endif #endif #if IMAGE_BL31 .quad \_name\()_core_pwr_dwn .quad \_name\()_cluster_pwr_dwn #endif #if (IMAGE_BL31 && CRASH_REPORTING) .quad \_name\()_cpu_reg_dump #endif .endm arm-trusted-firmware-1.0-aw-6/include/lib/mmio.h000066400000000000000000000042731322600646200215150ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __MMIO_H__ #define __MMIO_H__ #include static inline void mmio_write_8(uintptr_t addr, uint8_t value) { *(volatile uint8_t*)addr = value; } static inline uint8_t mmio_read_8(uintptr_t addr) { return *(volatile uint8_t*)addr; } static inline void mmio_write_32(uintptr_t addr, uint32_t value) { *(volatile uint32_t*)addr = value; } static inline uint32_t mmio_read_32(uintptr_t addr) { return *(volatile uint32_t*)addr; } static inline void mmio_write_64(uintptr_t addr, uint64_t value) { *(volatile uint64_t*)addr = value; } static inline uint64_t mmio_read_64(uintptr_t addr) { return *(volatile uint64_t*)addr; } #endif /* __MMIO_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/semihosting.h000066400000000000000000000064521322600646200231060ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SEMIHOSTING_H__ #define __SEMIHOSTING_H__ #include #include /* For ssize_t */ #define SEMIHOSTING_SYS_OPEN 0x01 #define SEMIHOSTING_SYS_CLOSE 0x02 #define SEMIHOSTING_SYS_WRITE0 0x04 #define SEMIHOSTING_SYS_WRITEC 0x03 #define SEMIHOSTING_SYS_WRITE 0x05 #define SEMIHOSTING_SYS_READ 0x06 #define SEMIHOSTING_SYS_READC 0x07 #define SEMIHOSTING_SYS_SEEK 0x0A #define SEMIHOSTING_SYS_FLEN 0x0C #define SEMIHOSTING_SYS_REMOVE 0x0E #define SEMIHOSTING_SYS_SYSTEM 0x12 #define SEMIHOSTING_SYS_ERRNO 0x13 #define FOPEN_MODE_R 0x0 #define FOPEN_MODE_RB 0x1 #define FOPEN_MODE_RPLUS 0x2 #define FOPEN_MODE_RPLUSB 0x3 #define FOPEN_MODE_W 0x4 #define FOPEN_MODE_WB 0x5 #define FOPEN_MODE_WPLUS 0x6 #define FOPEN_MODE_WPLUSB 0x7 #define FOPEN_MODE_A 0x8 #define FOPEN_MODE_AB 0x9 #define FOPEN_MODE_APLUS 0xa #define FOPEN_MODE_APLUSB 0xb long semihosting_connection_supported(void); long semihosting_file_open(const char *file_name, size_t mode); long semihosting_file_seek(long file_handle, ssize_t offset); long semihosting_file_read(long file_handle, size_t *length, uintptr_t buffer); long semihosting_file_write(long file_handle, size_t *length, const uintptr_t buffer); long semihosting_file_close(long file_handle); long semihosting_file_length(long file_handle); long semihosting_system(char *command_line); long semihosting_get_flen(const char *file_name); long semihosting_download_file(const char *file_name, size_t buf_size, uintptr_t buf); void semihosting_write_char(char character); void semihosting_write_string(char *string); char semihosting_read_char(void); #endif /* __SEMIHOSTING_H__ */ arm-trusted-firmware-1.0-aw-6/include/lib/spinlock.h000066400000000000000000000033631322600646200223750ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SPINLOCK_H__ #define __SPINLOCK_H__ typedef struct spinlock { volatile unsigned int lock; } spinlock_t; void spin_lock(spinlock_t *lock); void spin_unlock(spinlock_t *lock); #endif /* __SPINLOCK_H__ */ arm-trusted-firmware-1.0-aw-6/include/plat/000077500000000000000000000000001322600646200205675ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/plat/common/000077500000000000000000000000001322600646200220575ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/plat/common/plat_config.h000066400000000000000000000047661322600646200245320ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PLAT_CONFIG_H__ #define __PLAT_CONFIG_H__ #define CONFIG_GICC_BASE_OFFSET 0x4 #ifndef __ASSEMBLY__ #include enum plat_config_flags { /* Whether Base FVP memory map is in use */ CONFIG_BASE_MMAP = 0x1, /* Whether CCI should be enabled */ CONFIG_HAS_CCI = 0x2, /* Whether TZC should be configured */ CONFIG_HAS_TZC = 0x4 }; typedef struct plat_config { unsigned int gicd_base; unsigned int gicc_base; unsigned int gich_base; unsigned int gicv_base; unsigned int max_aff0; unsigned int max_aff1; unsigned long flags; } plat_config_t; inline const plat_config_t *get_plat_config(); CASSERT(CONFIG_GICC_BASE_OFFSET == __builtin_offsetof( plat_config_t, gicc_base), assert_gicc_base_offset_mismatch); /* If used, plat_config must be defined and populated in the platform port*/ extern plat_config_t plat_config; inline const plat_config_t *get_plat_config() { return &plat_config; } #endif /* __ASSEMBLY__ */ #endif /* __PLAT_CONFIG_H__ */ arm-trusted-firmware-1.0-aw-6/include/plat/common/platform.h000066400000000000000000000203751322600646200240630ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PLATFORM_H__ #define __PLATFORM_H__ #include /******************************************************************************* * Forward declarations ******************************************************************************/ struct plat_pm_ops; struct meminfo; struct image_info; struct entry_point_info; struct bl31_params; /******************************************************************************* * Function declarations ******************************************************************************/ /******************************************************************************* * Mandatory common functions ******************************************************************************/ uint64_t plat_get_syscnt_freq(void); int plat_get_image_source(const char *image_name, uintptr_t *dev_handle, uintptr_t *image_spec); unsigned long plat_get_ns_image_entrypoint(void); /******************************************************************************* * Mandatory interrupt management functions ******************************************************************************/ uint32_t plat_ic_get_pending_interrupt_id(void); uint32_t plat_ic_get_pending_interrupt_type(void); uint32_t plat_ic_acknowledge_interrupt(void); uint32_t plat_ic_get_interrupt_type(uint32_t id); void plat_ic_end_of_interrupt(uint32_t id); uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state); /******************************************************************************* * Optional common functions (may be overridden) ******************************************************************************/ unsigned int platform_get_core_pos(unsigned long mpidr); unsigned long platform_get_stack(unsigned long mpidr); void plat_report_exception(unsigned long); int plat_crash_console_init(void); int plat_crash_console_putc(int c); /******************************************************************************* * Mandatory BL1 functions ******************************************************************************/ void bl1_early_platform_setup(void); void bl1_plat_arch_setup(void); void bl1_platform_setup(void); struct meminfo *bl1_plat_sec_mem_layout(void); /* * This function allows the platform to change the entrypoint information for * BL2, after BL1 has loaded BL2 into memory but before BL2 is executed. */ void bl1_plat_set_bl2_ep_info(struct image_info *image, struct entry_point_info *ep); /******************************************************************************* * Optional BL1 functions (may be overridden) ******************************************************************************/ void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout, struct meminfo *bl2_mem_layout); /******************************************************************************* * Mandatory BL2 functions ******************************************************************************/ void bl2_early_platform_setup(struct meminfo *mem_layout); void bl2_plat_arch_setup(void); void bl2_platform_setup(void); struct meminfo *bl2_plat_sec_mem_layout(void); /* * This function returns a pointer to the shared memory that the platform has * kept aside to pass trusted firmware related information that BL3-1 * could need */ struct bl31_params *bl2_plat_get_bl31_params(void); /* * This function returns a pointer to the shared memory that the platform * has kept to point to entry point information of BL31 to BL2 */ struct entry_point_info *bl2_plat_get_bl31_ep_info(void); /* * This function flushes to main memory all the params that are * passed to BL3-1 */ void bl2_plat_flush_bl31_params(void); /* * The next 2 functions allow the platform to change the entrypoint information * for the mandatory 3rd level BL images, BL3-1 and BL3-3. This is done after * BL2 has loaded those images into memory but before BL3-1 is executed. */ void bl2_plat_set_bl31_ep_info(struct image_info *image, struct entry_point_info *ep); void bl2_plat_set_bl33_ep_info(struct image_info *image, struct entry_point_info *ep); /* Gets the memory layout for BL3-3 */ void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); /******************************************************************************* * Conditionally mandatory BL2 functions: must be implemented if BL3-0 image * is supported ******************************************************************************/ /* Gets the memory layout for BL3-0 */ void bl2_plat_get_bl30_meminfo(struct meminfo *mem_info); /* * This function is called after loading BL3-0 image and it is used to perform * any platform-specific actions required to handle the SCP firmware. */ int bl2_plat_handle_bl30(struct image_info *bl30_image_info); /******************************************************************************* * Conditionally mandatory BL2 functions: must be implemented if BL3-2 image * is supported ******************************************************************************/ void bl2_plat_set_bl32_ep_info(struct image_info *image, struct entry_point_info *ep); /* Gets the memory layout for BL3-2 */ void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); /******************************************************************************* * Optional BL2 functions (may be overridden) ******************************************************************************/ /******************************************************************************* * Mandatory BL3-1 functions ******************************************************************************/ void bl31_early_platform_setup(struct bl31_params *from_bl2, void *plat_params_from_bl2); void bl31_plat_arch_setup(void); void bl31_platform_setup(void); struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type); /******************************************************************************* * Mandatory PSCI functions (BL3-1) ******************************************************************************/ int platform_setup_pm(const struct plat_pm_ops **); int plat_get_max_afflvl(void); unsigned int plat_get_aff_count(unsigned int, unsigned long); unsigned int plat_get_aff_state(unsigned int, unsigned long); /******************************************************************************* * Optional BL3-1 functions (may be overridden) ******************************************************************************/ void bl31_plat_enable_mmu(uint32_t flags); /******************************************************************************* * Optional BL3-2 functions (may be overridden) ******************************************************************************/ void bl32_plat_enable_mmu(uint32_t flags); void platform_smp_init(void); #endif /* __PLATFORM_H__ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/000077500000000000000000000000001322600646200211105ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/stdlib/assert.h000066400000000000000000000047241322600646200225710ustar00rootroot00000000000000/*- * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. * (c) UNIX System Laboratories, Inc. * All or some portions of this file are derived from material licensed * to the University of California by American Telephone and Telegraph * Co. or Unix System Laboratories, Inc. and are reproduced herein with * the permission of UNIX System Laboratories, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)assert.h 8.2 (Berkeley) 1/21/94 * $FreeBSD$ */ #include /* * Unlike other ANSI header files, may usefully be included * multiple times, with and without NDEBUG defined. */ #undef assert #undef _assert #ifdef NDEBUG #define assert(e) ((void)0) #define _assert(e) ((void)0) #else #define _assert(e) assert(e) #define assert(e) ((e) ? (void)0 : __assert(__func__, __FILE__, \ __LINE__, #e)) #endif /* NDEBUG */ #ifndef _ASSERT_H_ #define _ASSERT_H_ __BEGIN_DECLS void __assert(const char *, const char *, int, const char *) __dead2; __END_DECLS #endif /* !_ASSERT_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/machine/000077500000000000000000000000001322600646200225145ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/stdlib/machine/_limits.h000066400000000000000000000071741322600646200243360ustar00rootroot00000000000000/*- * Copyright (c) 1988, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)limits.h 8.3 (Berkeley) 1/4/94 * $FreeBSD$ */ #ifndef _MACHINE__LIMITS_H_ #define _MACHINE__LIMITS_H_ /* * According to ANSI (section 2.2.4.2), the values below must be usable by * #if preprocessing directives. Additionally, the expression must have the * same type as would an expression that is an object of the corresponding * type converted according to the integral promotions. The subtraction for * INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2). */ #define __CHAR_BIT 8 /* number of bits in a char */ #define __SCHAR_MAX 0x7f /* max value for a signed char */ #define __SCHAR_MIN (-0x7f-1) /* min value for a signed char */ #define __UCHAR_MAX 0xff /* max value for an unsigned char */ #define __USHRT_MAX 0xffff /* max value for an unsigned short */ #define __SHRT_MAX 0x7fff /* max value for a short */ #define __SHRT_MIN (-0x7fff-1) /* min value for a short */ #define __UINT_MAX 0xffffffff /* max value for an unsigned int */ #define __INT_MAX 0x7fffffff /* max value for an int */ #define __INT_MIN (-0x7fffffff-1) /* min value for an int */ #define __ULONG_MAX 0xffffffffffffffff /* max for an unsigned long */ #define __LONG_MAX 0x7fffffffffffffff /* max for a long */ #define __LONG_MIN (-0x7fffffffffffffff-1) /* min for a long */ /* Long longs have the same size but not the same type as longs. */ /* max for an unsigned long long */ #define __ULLONG_MAX 0xffffffffffffffffULL #define __LLONG_MAX 0x7fffffffffffffffLL /* max for a long long */ #define __LLONG_MIN (-0x7fffffffffffffffLL-1) /* min for a long long */ #define __SSIZE_MAX __LONG_MAX /* max value for a ssize_t */ #define __SIZE_T_MAX __ULONG_MAX /* max value for a size_t */ #define __OFF_MAX __LONG_MAX /* max value for an off_t */ #define __OFF_MIN __LONG_MIN /* min value for an off_t */ /* Quads and longs are the same size. Ensure they stay in sync. */ #define __UQUAD_MAX (__ULONG_MAX) /* max value for a uquad_t */ #define __QUAD_MAX (__LONG_MAX) /* max value for a quad_t */ #define __QUAD_MIN (__LONG_MIN) /* min value for a quad_t */ #define __LONG_BIT 64 #define __WORD_BIT 32 /* Minimum signal stack size. */ #define __MINSIGSTKSZ (1024 * 4) #endif /* !_MACHINE__LIMITS_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/machine/_stdint.h000066400000000000000000000117341322600646200243370ustar00rootroot00000000000000/*- * Copyright (c) 2001, 2002 Mike Barcroft * Copyright (c) 2001 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Klaus Klein. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE__STDINT_H_ #define _MACHINE__STDINT_H_ #if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) #define INT8_C(c) (c) #define INT16_C(c) (c) #define INT32_C(c) (c) #define INT64_C(c) (c ## L) #define UINT8_C(c) (c) #define UINT16_C(c) (c) #define UINT32_C(c) (c ## U) #define UINT64_C(c) (c ## UL) #define INTMAX_C(c) INT64_C(c) #define UINTMAX_C(c) UINT64_C(c) #endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ #if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) /* * ISO/IEC 9899:1999 * 7.18.2.1 Limits of exact-width integer types */ /* Minimum values of exact-width signed integer types. */ #define INT8_MIN (-0x7f-1) #define INT16_MIN (-0x7fff-1) #define INT32_MIN (-0x7fffffff-1) #define INT64_MIN (-0x7fffffffffffffffL-1) /* Maximum values of exact-width signed integer types. */ #define INT8_MAX 0x7f #define INT16_MAX 0x7fff #define INT32_MAX 0x7fffffff #define INT64_MAX 0x7fffffffffffffffL /* Maximum values of exact-width unsigned integer types. */ #define UINT8_MAX 0xff #define UINT16_MAX 0xffff #define UINT32_MAX 0xffffffffU #define UINT64_MAX 0xffffffffffffffffUL /* * ISO/IEC 9899:1999 * 7.18.2.2 Limits of minimum-width integer types */ /* Minimum values of minimum-width signed integer types. */ #define INT_LEAST8_MIN INT8_MIN #define INT_LEAST16_MIN INT16_MIN #define INT_LEAST32_MIN INT32_MIN #define INT_LEAST64_MIN INT64_MIN /* Maximum values of minimum-width signed integer types. */ #define INT_LEAST8_MAX INT8_MAX #define INT_LEAST16_MAX INT16_MAX #define INT_LEAST32_MAX INT32_MAX #define INT_LEAST64_MAX INT64_MAX /* Maximum values of minimum-width unsigned integer types. */ #define UINT_LEAST8_MAX UINT8_MAX #define UINT_LEAST16_MAX UINT16_MAX #define UINT_LEAST32_MAX UINT32_MAX #define UINT_LEAST64_MAX UINT64_MAX /* * ISO/IEC 9899:1999 * 7.18.2.3 Limits of fastest minimum-width integer types */ /* Minimum values of fastest minimum-width signed integer types. */ #define INT_FAST8_MIN INT32_MIN #define INT_FAST16_MIN INT32_MIN #define INT_FAST32_MIN INT32_MIN #define INT_FAST64_MIN INT64_MIN /* Maximum values of fastest minimum-width signed integer types. */ #define INT_FAST8_MAX INT32_MAX #define INT_FAST16_MAX INT32_MAX #define INT_FAST32_MAX INT32_MAX #define INT_FAST64_MAX INT64_MAX /* Maximum values of fastest minimum-width unsigned integer types. */ #define UINT_FAST8_MAX UINT32_MAX #define UINT_FAST16_MAX UINT32_MAX #define UINT_FAST32_MAX UINT32_MAX #define UINT_FAST64_MAX UINT64_MAX /* * ISO/IEC 9899:1999 * 7.18.2.4 Limits of integer types capable of holding object pointers */ #define INTPTR_MIN INT64_MIN #define INTPTR_MAX INT64_MAX #define UINTPTR_MAX UINT64_MAX /* * ISO/IEC 9899:1999 * 7.18.2.5 Limits of greatest-width integer types */ #define INTMAX_MIN INT64_MIN #define INTMAX_MAX INT64_MAX #define UINTMAX_MAX UINT64_MAX /* * ISO/IEC 9899:1999 * 7.18.3 Limits of other integer types */ /* Limits of ptrdiff_t. */ #define PTRDIFF_MIN INT64_MIN #define PTRDIFF_MAX INT64_MAX /* Limits of sig_atomic_t. */ #define SIG_ATOMIC_MIN INT32_MIN #define SIG_ATOMIC_MAX INT32_MAX /* Limit of size_t. */ #define SIZE_MAX UINT64_MAX #ifndef WCHAR_MIN /* Also possibly defined in */ /* Limits of wchar_t. */ #define WCHAR_MIN INT32_MIN #define WCHAR_MAX INT32_MAX #endif /* Limits of wint_t. */ #define WINT_MIN INT32_MIN #define WINT_MAX INT32_MAX #endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ #endif /* !_MACHINE__STDINT_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/machine/_types.h000066400000000000000000000077351322600646200242040ustar00rootroot00000000000000/*- * Copyright (c) 2002 Mike Barcroft * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 * From: @(#)types.h 8.3 (Berkeley) 1/5/94 * $FreeBSD$ */ #ifndef _MACHINE__TYPES_H_ #define _MACHINE__TYPES_H_ #ifndef _SYS_CDEFS_H_ #error this file needs sys/cdefs.h as a prerequisite #endif /* * Basic types upon which most other types are built. */ typedef __signed char __int8_t; typedef unsigned char __uint8_t; typedef short __int16_t; typedef unsigned short __uint16_t; typedef int __int32_t; typedef unsigned int __uint32_t; typedef long __int64_t; typedef unsigned long __uint64_t; /* * Standard type definitions. */ typedef __int32_t __clock_t; /* clock()... */ typedef __int64_t __critical_t; typedef double __double_t; typedef float __float_t; typedef __int64_t __intfptr_t; typedef __int64_t __intmax_t; typedef __int64_t __intptr_t; typedef __int32_t __int_fast8_t; typedef __int32_t __int_fast16_t; typedef __int32_t __int_fast32_t; typedef __int64_t __int_fast64_t; typedef __int8_t __int_least8_t; typedef __int16_t __int_least16_t; typedef __int32_t __int_least32_t; typedef __int64_t __int_least64_t; typedef __int64_t __ptrdiff_t; /* ptr1 - ptr2 */ typedef __int64_t __register_t; typedef __int64_t __segsz_t; /* segment size (in pages) */ typedef __uint64_t __size_t; /* sizeof() */ typedef __int64_t __ssize_t; /* byte count or error */ typedef __int64_t __time_t; /* time()... */ typedef __uint64_t __uintfptr_t; typedef __uint64_t __uintmax_t; typedef __uint64_t __uintptr_t; typedef __uint32_t __uint_fast8_t; typedef __uint32_t __uint_fast16_t; typedef __uint32_t __uint_fast32_t; typedef __uint64_t __uint_fast64_t; typedef __uint8_t __uint_least8_t; typedef __uint16_t __uint_least16_t; typedef __uint32_t __uint_least32_t; typedef __uint64_t __uint_least64_t; typedef __uint64_t __u_register_t; typedef __uint64_t __vm_offset_t; typedef __int64_t __vm_ooffset_t; typedef __uint64_t __vm_paddr_t; typedef __uint64_t __vm_pindex_t; typedef __uint64_t __vm_size_t; /* * Unusual type definitions. */ #ifdef __GNUCLIKE_BUILTIN_VARARGS typedef __builtin_va_list __va_list; /* internally known to gcc */ #else typedef char * __va_list; #endif /* __GNUCLIKE_BUILTIN_VARARGS */ #if defined(__GNUCLIKE_BUILTIN_VAALIST) && !defined(__GNUC_VA_LIST) \ && !defined(__NO_GNUC_VA_LIST) #define __GNUC_VA_LIST typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/ #endif #endif /* !_MACHINE__TYPES_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/stddef.h000066400000000000000000000042051322600646200225330ustar00rootroot00000000000000/*- * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)stddef.h 8.1 (Berkeley) 6/2/93 * * $FreeBSD$ */ #ifndef _STDDEF_H_ #define _STDDEF_H_ #include #include #include typedef __ptrdiff_t ptrdiff_t; #if __BSD_VISIBLE #ifndef _RUNE_T_DECLARED typedef __rune_t rune_t; #define _RUNE_T_DECLARED #endif #endif #ifndef _SIZE_T_DECLARED typedef __size_t size_t; #define _SIZE_T_DECLARED #endif #ifndef __cplusplus #ifndef _WCHAR_T_DECLARED typedef __wchar_t wchar_t; #define _WCHAR_T_DECLARED #endif #endif #define offsetof(type, member) __offsetof(type, member) #endif /* _STDDEF_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/stdio.h000066400000000000000000000050641322600646200224100ustar00rootroot00000000000000/*- * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * Chris Torek. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)stdio.h 8.5 (Berkeley) 4/29/95 * $FreeBSD$ */ /* * Portions copyright (c) 2013-2014, ARM Limited and Contributors. * All rights reserved. */ #ifndef _STDIO_H_ #define _STDIO_H_ #include #include #include #ifndef _SIZE_T_DECLARED typedef __size_t size_t; #define _SIZE_T_DECLARED #endif #ifndef _SSIZE_T_DECLARED #define _SSIZE_T_DECLARED typedef __ssize_t ssize_t; #endif #define EOF (-1) int printf(const char * __restrict, ...); int putchar(int); int puts(const char *); int sprintf(char * __restrict, const char * __restrict, ...); int vsprintf(char * __restrict, const char * __restrict, __va_list); #if __ISO_C_VISIBLE >= 1999 int snprintf(char * __restrict, size_t, const char * __restrict, ...) __printflike(3, 4); int vsnprintf(char * __restrict, size_t, const char * __restrict, __va_list) __printflike(3, 0); #endif #endif /* !_STDIO_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/string.h000066400000000000000000000045741322600646200226010ustar00rootroot00000000000000/*- * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)string.h 8.1 (Berkeley) 6/2/93 * $FreeBSD$ */ /* * Portions copyright (c) 2013-2014, ARM Limited and Contributors. * All rights reserved. */ #ifndef _STRING_H_ #define _STRING_H_ #include #include #include #ifndef _SIZE_T_DECLARED typedef __size_t size_t; #define _SIZE_T_DECLARED #endif __BEGIN_DECLS void *memchr(const void *, int, size_t) __pure; int memcmp(const void *, const void *, size_t) __pure; void *memcpy(void * __restrict, const void * __restrict, size_t); void *memmove(void *, const void *, size_t); void *memset(void *, int, size_t); char *strchr(const char *, int) __pure; int strcmp(const char *, const char *) __pure; size_t strlen(const char *) __pure; int strncmp(const char *, const char *, size_t) __pure; __END_DECLS #endif /* _STRING_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/000077500000000000000000000000001322600646200217265ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/_null.h000066400000000000000000000032271322600646200232140ustar00rootroot00000000000000/*- * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef NULL #if !defined(__cplusplus) #define NULL ((void *)0) #else #if __cplusplus >= 201103L #define NULL nullptr #elif defined(__GNUG__) && defined(__GNUC__) && __GNUC__ >= 4 #define NULL __null #else #if defined(__LP64__) #define NULL (0L) #else #define NULL 0 #endif /* __LP64__ */ #endif /* __GNUG__ */ #endif /* !__cplusplus */ #endif arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/_stdint.h000066400000000000000000000045751322600646200235560ustar00rootroot00000000000000/*- * Copyright (c) 2011 David E. O'Brien * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _SYS__STDINT_H_ #define _SYS__STDINT_H_ #ifndef _INT8_T_DECLARED typedef __int8_t int8_t; #define _INT8_T_DECLARED #endif #ifndef _INT16_T_DECLARED typedef __int16_t int16_t; #define _INT16_T_DECLARED #endif #ifndef _INT32_T_DECLARED typedef __int32_t int32_t; #define _INT32_T_DECLARED #endif #ifndef _INT64_T_DECLARED typedef __int64_t int64_t; #define _INT64_T_DECLARED #endif #ifndef _UINT8_T_DECLARED typedef __uint8_t uint8_t; #define _UINT8_T_DECLARED #endif #ifndef _UINT16_T_DECLARED typedef __uint16_t uint16_t; #define _UINT16_T_DECLARED #endif #ifndef _UINT32_T_DECLARED typedef __uint32_t uint32_t; #define _UINT32_T_DECLARED #endif #ifndef _UINT64_T_DECLARED typedef __uint64_t uint64_t; #define _UINT64_T_DECLARED #endif #ifndef _INTPTR_T_DECLARED typedef __intptr_t intptr_t; #define _INTPTR_T_DECLARED #endif #ifndef _UINTPTR_T_DECLARED typedef __uintptr_t uintptr_t; #define _UINTPTR_T_DECLARED #endif #endif /* !_SYS__STDINT_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/_types.h000066400000000000000000000106231322600646200234040ustar00rootroot00000000000000/*- * Copyright (c) 2002 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _SYS__TYPES_H_ #define _SYS__TYPES_H_ #include #include /* * Standard type definitions. */ typedef __uint32_t __blksize_t; /* file block size */ typedef __int64_t __blkcnt_t; /* file block count */ typedef __int32_t __clockid_t; /* clock_gettime()... */ typedef __uint64_t __cap_rights_t; /* capability rights */ typedef __uint32_t __fflags_t; /* file flags */ typedef __uint64_t __fsblkcnt_t; typedef __uint64_t __fsfilcnt_t; typedef __uint32_t __gid_t; typedef __int64_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ typedef __uint32_t __ino_t; /* inode number */ typedef long __key_t; /* IPC key (for Sys V IPC) */ typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ typedef __uint16_t __mode_t; /* permissions */ typedef int __accmode_t; /* access permissions */ typedef int __nl_item; typedef __uint16_t __nlink_t; /* link count */ typedef __int64_t __off_t; /* file offset */ typedef __int32_t __pid_t; /* process [group] */ typedef __int64_t __rlim_t; /* resource limit - intentionally */ /* signed, because of legacy code */ /* that uses -1 for RLIM_INFINITY */ typedef __uint8_t __sa_family_t; typedef __uint32_t __socklen_t; typedef long __suseconds_t; /* microseconds (signed) */ typedef struct __timer *__timer_t; /* timer_gettime()... */ typedef struct __mq *__mqd_t; /* mq_open()... */ typedef __uint32_t __uid_t; typedef unsigned int __useconds_t; /* microseconds (unsigned) */ typedef int __cpuwhich_t; /* which parameter for cpuset. */ typedef int __cpulevel_t; /* level parameter for cpuset. */ typedef int __cpusetid_t; /* cpuset identifier. */ /* * Unusual type definitions. */ /* * rune_t is declared to be an ``int'' instead of the more natural * ``unsigned long'' or ``long''. Two things are happening here. It is not * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, * it looks like 10646 will be a 31 bit standard. This means that if your * ints cannot hold 32 bits, you will be in trouble. The reason an int was * chosen over a long is that the is*() and to*() routines take ints (says * ANSI C), but they use __ct_rune_t instead of int. * * NOTE: rune_t is not covered by ANSI nor other standards, and should not * be instantiated outside of lib/libc/locale. Use wchar_t. wchar_t and * rune_t must be the same type. Also, wint_t must be no narrower than * wchar_t, and should be able to hold all members of the largest * character set plus one extra value (WEOF), and must be at least 16 bits. */ typedef int __ct_rune_t; /* arg type for ctype funcs */ typedef __ct_rune_t __rune_t; /* rune_t (see above) */ typedef __ct_rune_t __wchar_t; /* wchar_t (see above) */ typedef __ct_rune_t __wint_t; /* wint_t (see above) */ typedef __uint32_t __dev_t; /* device number */ typedef __uint32_t __fixpt_t; /* fixed point number */ /* * mbstate_t is an opaque object to keep conversion state during multibyte * stream conversions. */ typedef union { char __mbstate8[128]; __int64_t _mbstateL; /* for alignment */ } __mbstate_t; #endif /* !_SYS__TYPES_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/cdefs.h000066400000000000000000000540451322600646200231730ustar00rootroot00000000000000/*- * Copyright (c) 1991, 1993 * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * Berkeley Software Design, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 * $FreeBSD$ */ #ifndef _SYS_CDEFS_H_ #define _SYS_CDEFS_H_ #if defined(__cplusplus) #define __BEGIN_DECLS extern "C" { #define __END_DECLS } #else #define __BEGIN_DECLS #define __END_DECLS #endif /* * This code has been put in place to help reduce the addition of * compiler specific defines in FreeBSD code. It helps to aid in * having a compiler-agnostic source tree. */ #if defined(__GNUC__) || defined(__INTEL_COMPILER) #if __GNUC__ >= 3 || defined(__INTEL_COMPILER) #define __GNUCLIKE_ASM 3 #define __GNUCLIKE_MATH_BUILTIN_CONSTANTS #else #define __GNUCLIKE_ASM 2 #endif #define __GNUCLIKE___TYPEOF 1 #define __GNUCLIKE___OFFSETOF 1 #define __GNUCLIKE___SECTION 1 #ifndef __INTEL_COMPILER # define __GNUCLIKE_CTOR_SECTION_HANDLING 1 #endif #define __GNUCLIKE_BUILTIN_CONSTANT_P 1 # if defined(__INTEL_COMPILER) && defined(__cplusplus) \ && __INTEL_COMPILER < 800 # undef __GNUCLIKE_BUILTIN_CONSTANT_P # endif #if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER) # define __GNUCLIKE_BUILTIN_VARARGS 1 # define __GNUCLIKE_BUILTIN_STDARG 1 # define __GNUCLIKE_BUILTIN_VAALIST 1 #endif #if defined(__GNUC__) # define __GNUC_VA_LIST_COMPATIBILITY 1 #endif #ifndef __INTEL_COMPILER # define __GNUCLIKE_BUILTIN_NEXT_ARG 1 # define __GNUCLIKE_MATH_BUILTIN_RELOPS #endif #define __GNUCLIKE_BUILTIN_MEMCPY 1 /* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */ #define __CC_SUPPORTS_INLINE 1 #define __CC_SUPPORTS___INLINE 1 #define __CC_SUPPORTS___INLINE__ 1 #define __CC_SUPPORTS___FUNC__ 1 #define __CC_SUPPORTS_WARNING 1 #define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */ #define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 #endif /* __GNUC__ || __INTEL_COMPILER */ /* * Macro to test if we're using a specific version of gcc or later. */ #if defined(__GNUC__) && !defined(__INTEL_COMPILER) #define __GNUC_PREREQ__(ma, mi) \ (__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi)) #else #define __GNUC_PREREQ__(ma, mi) 0 #endif /* * The __CONCAT macro is used to concatenate parts of symbol names, e.g. * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI * mode -- there must be no spaces between its arguments, and for nested * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also * concatenate double-quoted strings produced by the __STRING macro, but * this only works with ANSI C. * * __XSTRING is like __STRING, but it expands any macros in its argument * first. It is only available with ANSI C. */ #if defined(__STDC__) || defined(__cplusplus) #define __P(protos) protos /* full-blown ANSI C */ #define __CONCAT1(x,y) x ## y #define __CONCAT(x,y) __CONCAT1(x,y) #define __STRING(x) #x /* stringify without expanding x */ #define __XSTRING(x) __STRING(x) /* expand x, then stringify */ #define __const const /* define reserved names to standard */ #define __signed signed #define __volatile volatile #if defined(__cplusplus) #define __inline inline /* convert to C++ keyword */ #else #if !(defined(__CC_SUPPORTS___INLINE)) #define __inline /* delete GCC keyword */ #endif /* ! __CC_SUPPORTS___INLINE */ #endif /* !__cplusplus */ #else /* !(__STDC__ || __cplusplus) */ #define __P(protos) () /* traditional C preprocessor */ #define __CONCAT(x,y) x/**/y #define __STRING(x) "x" #if !defined(__CC_SUPPORTS___INLINE) #define __const /* delete pseudo-ANSI C keywords */ #define __inline #define __signed #define __volatile /* * In non-ANSI C environments, new programs will want ANSI-only C keywords * deleted from the program and old programs will want them left alone. * When using a compiler other than gcc, programs using the ANSI C keywords * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS. * When using "gcc -traditional", we assume that this is the intent; if * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone. */ #ifndef NO_ANSI_KEYWORDS #define const /* delete ANSI C keywords */ #define inline #define signed #define volatile #endif /* !NO_ANSI_KEYWORDS */ #endif /* !__CC_SUPPORTS___INLINE */ #endif /* !(__STDC__ || __cplusplus) */ /* * Compiler-dependent macros to help declare dead (non-returning) and * pure (no side effects) functions, and unused variables. They are * null except for versions of gcc that are known to support the features * properly (old versions of gcc-2 supported the dead and pure features * in a different (wrong) way). If we do not provide an implementation * for a given compiler, let the compile fail if it is told to use * a feature that we cannot live without. */ #ifdef lint #define __dead2 #define __pure2 #define __unused #define __packed #define __aligned(x) #define __section(x) #else #if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER) #define __dead2 #define __pure2 #define __unused #endif #if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER) #define __dead2 __attribute__((__noreturn__)) #define __pure2 __attribute__((__const__)) #define __unused /* XXX Find out what to do for __packed, __aligned and __section */ #endif #if __GNUC_PREREQ__(2, 7) #define __dead2 __attribute__((__noreturn__)) #define __pure2 __attribute__((__const__)) #define __unused __attribute__((__unused__)) #define __used __attribute__((__used__)) #define __packed __attribute__((__packed__)) #define __aligned(x) __attribute__((__aligned__(x))) #define __section(x) __attribute__((__section__(x))) #endif #if defined(__INTEL_COMPILER) #define __dead2 __attribute__((__noreturn__)) #define __pure2 __attribute__((__const__)) #define __unused __attribute__((__unused__)) #define __used __attribute__((__used__)) #define __packed __attribute__((__packed__)) #define __aligned(x) __attribute__((__aligned__(x))) #define __section(x) __attribute__((__section__(x))) #endif #endif #if !__GNUC_PREREQ__(2, 95) #define __alignof(x) __offsetof(struct { char __a; x __b; }, __b) #endif /* * Keywords added in C11. */ #if defined(__cplusplus) && __cplusplus >= 201103L #define _Alignas(e) alignas(e) #define _Alignof(e) alignof(e) #define _Noreturn [[noreturn]] #define _Static_assert(e, s) static_assert(e, s) /* FIXME: change this to thread_local when clang in base supports it */ #define _Thread_local __thread #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L /* Do nothing. They are language keywords. */ #else /* Not supported. Implement them using our versions. */ #define _Alignas(x) __aligned(x) #define _Alignof(x) __alignof(x) #define _Noreturn __dead2 #define _Thread_local __thread #ifdef __COUNTER__ #define _Static_assert(x, y) __Static_assert(x, __COUNTER__) #define __Static_assert(x, y) ___Static_assert(x, y) #define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] #else #define _Static_assert(x, y) struct __hack #endif #endif /* * Emulation of C11 _Generic(). Unlike the previously defined C11 * keywords, it is not possible to implement this using exactly the same * syntax. Therefore implement something similar under the name * __generic(). Unlike _Generic(), this macro can only distinguish * between a single type, so it requires nested invocations to * distinguish multiple cases. */ #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L #define __generic(expr, t, yes, no) \ _Generic(expr, t: yes, default: no) #elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus) #define __generic(expr, t, yes, no) \ __builtin_choose_expr( \ __builtin_types_compatible_p(__typeof(expr), t), yes, no) #endif #if __GNUC_PREREQ__(2, 96) #define __malloc_like __attribute__((__malloc__)) #define __pure __attribute__((__pure__)) #else #define __malloc_like #define __pure #endif #if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800) #define __always_inline __attribute__((__always_inline__)) #else #define __always_inline #endif #if __GNUC_PREREQ__(3, 1) #define __noinline __attribute__ ((__noinline__)) #else #define __noinline #endif #if __GNUC_PREREQ__(3, 3) #define __nonnull(x) __attribute__((__nonnull__(x))) #else #define __nonnull(x) #endif #if __GNUC_PREREQ__(3, 4) #define __fastcall __attribute__((__fastcall__)) #else #define __fastcall #endif #if __GNUC_PREREQ__(4, 1) #define __returns_twice __attribute__((__returns_twice__)) #else #define __returns_twice #endif /* XXX: should use `#if __STDC_VERSION__ < 199901'. */ #if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) #define __func__ NULL #endif #if (defined(__INTEL_COMPILER) || (defined(__GNUC__) && __GNUC__ >= 2)) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901 #define __LONG_LONG_SUPPORTED #endif /* C++11 exposes a load of C99 stuff */ #if defined(__cplusplus) && __cplusplus >= 201103L #define __LONG_LONG_SUPPORTED #ifndef __STDC_LIMIT_MACROS #define __STDC_LIMIT_MACROS #endif #ifndef __STDC_CONSTANT_MACROS #define __STDC_CONSTANT_MACROS #endif #endif /* * GCC 2.95 provides `__restrict' as an extension to C90 to support the * C99-specific `restrict' type qualifier. We happen to use `__restrict' as * a way to define the `restrict' type qualifier without disturbing older * software that is unaware of C99 keywords. */ #if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95) #if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint) #define __restrict #else #define __restrict restrict #endif #endif /* * GNU C version 2.96 adds explicit branch prediction so that * the CPU back-end can hint the processor and also so that * code blocks can be reordered such that the predicted path * sees a more linear flow, thus improving cache behavior, etc. * * The following two macros provide us with a way to utilize this * compiler feature. Use __predict_true() if you expect the expression * to evaluate to true, and __predict_false() if you expect the * expression to evaluate to false. * * A few notes about usage: * * * Generally, __predict_false() error condition checks (unless * you have some _strong_ reason to do otherwise, in which case * document it), and/or __predict_true() `no-error' condition * checks, assuming you want to optimize for the no-error case. * * * Other than that, if you don't know the likelihood of a test * succeeding from empirical or other `hard' evidence, don't * make predictions. * * * These are meant to be used in places that are run `a lot'. * It is wasteful to make predictions in code that is run * seldomly (e.g. at subsystem initialization time) as the * basic block reordering that this affects can often generate * larger code. */ #if __GNUC_PREREQ__(2, 96) #define __predict_true(exp) __builtin_expect((exp), 1) #define __predict_false(exp) __builtin_expect((exp), 0) #else #define __predict_true(exp) (exp) #define __predict_false(exp) (exp) #endif #if __GNUC_PREREQ__(4, 2) #define __hidden __attribute__((__visibility__("hidden"))) #define __exported __attribute__((__visibility__("default"))) #else #define __hidden #define __exported #endif /* * We define this here since , , and * require it. */ #if __GNUC_PREREQ__(4, 1) #define __offsetof(type, field) __builtin_offsetof(type, field) #else #ifndef __cplusplus #define __offsetof(type, field) \ ((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field)) #else #define __offsetof(type, field) \ (__offsetof__ (reinterpret_cast <__size_t> \ (&reinterpret_cast \ (static_cast (0)->field)))) #endif #endif #define __rangeof(type, start, end) \ (__offsetof(type, end) - __offsetof(type, start)) /* * Given the pointer x to the member m of the struct s, return * a pointer to the containing structure. When using GCC, we first * assign pointer x to a local variable, to check that its type is * compatible with member m. */ #if __GNUC_PREREQ__(3, 1) #define __containerof(x, s, m) ({ \ const volatile __typeof(((s *)0)->m) *__x = (x); \ __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\ }) #else #define __containerof(x, s, m) \ __DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m)) #endif /* * Compiler-dependent macros to declare that functions take printf-like * or scanf-like arguments. They are null except for versions of gcc * that are known to support the features properly (old versions of gcc-2 * didn't permit keeping the keywords out of the application namespace). */ #if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) #define __printflike(fmtarg, firstvararg) #define __scanflike(fmtarg, firstvararg) #define __format_arg(fmtarg) #define __strfmonlike(fmtarg, firstvararg) #define __strftimelike(fmtarg, firstvararg) #else #define __printflike(fmtarg, firstvararg) \ __attribute__((__format__ (__printf__, fmtarg, firstvararg))) #define __scanflike(fmtarg, firstvararg) \ __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) #define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) #define __strfmonlike(fmtarg, firstvararg) \ __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) #define __strftimelike(fmtarg, firstvararg) \ __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) #endif /* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ #if __FreeBSD_cc_version >= 300001 && defined(__GNUC__) && !defined(__INTEL_COMPILER) #define __printf0like(fmtarg, firstvararg) \ __attribute__((__format__ (__printf0__, fmtarg, firstvararg))) #else #define __printf0like(fmtarg, firstvararg) #endif #if defined(__GNUC__) || defined(__INTEL_COMPILER) #ifndef __INTEL_COMPILER #define __strong_reference(sym,aliassym) \ extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) #endif #ifdef __STDC__ #define __weak_reference(sym,alias) \ __asm__(".weak " #alias); \ __asm__(".equ " #alias ", " #sym) #define __warn_references(sym,msg) \ __asm__(".section .gnu.warning." #sym); \ __asm__(".asciz \"" msg "\""); \ __asm__(".previous") #define __sym_compat(sym,impl,verid) \ __asm__(".symver " #impl ", " #sym "@" #verid) #define __sym_default(sym,impl,verid) \ __asm__(".symver " #impl ", " #sym "@@" #verid) #else #define __weak_reference(sym,alias) \ __asm__(".weak alias"); \ __asm__(".equ alias, sym") #define __warn_references(sym,msg) \ __asm__(".section .gnu.warning.sym"); \ __asm__(".asciz \"msg\""); \ __asm__(".previous") #define __sym_compat(sym,impl,verid) \ __asm__(".symver impl, sym@verid") #define __sym_default(impl,sym,verid) \ __asm__(".symver impl, sym@@verid") #endif /* __STDC__ */ #endif /* __GNUC__ || __INTEL_COMPILER */ #define __GLOBL1(sym) __asm__(".globl " #sym) #define __GLOBL(sym) __GLOBL1(sym) #if defined(__GNUC__) || defined(__INTEL_COMPILER) #define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"") #else /* * The following definition might not work well if used in header files, * but it should be better than nothing. If you want a "do nothing" * version, then it should generate some harmless declaration, such as: * #define __IDSTRING(name,string) struct __hack */ #define __IDSTRING(name,string) static const char name[] __unused = string #endif /* * Embed the rcs id of a source file in the resulting library. Note that in * more recent ELF binutils, we use .ident allowing the ID to be stripped. * Usage: * __FBSDID("$FreeBSD$"); */ #ifndef __FBSDID #if !defined(lint) && !defined(STRIP_FBSDID) #define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) #else #define __FBSDID(s) struct __hack #endif #endif #ifndef __RCSID #ifndef NO__RCSID #define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) #else #define __RCSID(s) struct __hack #endif #endif #ifndef __RCSID_SOURCE #ifndef NO__RCSID_SOURCE #define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s) #else #define __RCSID_SOURCE(s) struct __hack #endif #endif #ifndef __SCCSID #ifndef NO__SCCSID #define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s) #else #define __SCCSID(s) struct __hack #endif #endif #ifndef __COPYRIGHT #ifndef NO__COPYRIGHT #define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s) #else #define __COPYRIGHT(s) struct __hack #endif #endif #ifndef __DECONST #define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var)) #endif #ifndef __DEVOLATILE #define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var)) #endif #ifndef __DEQUALIFY #define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var)) #endif /*- * The following definitions are an extension of the behavior originally * implemented in , but with a different level of granularity. * POSIX.1 requires that the macros we test be defined before any standard * header file is included. * * Here's a quick run-down of the versions: * defined(_POSIX_SOURCE) 1003.1-1988 * _POSIX_C_SOURCE == 1 1003.1-1990 * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option * _POSIX_C_SOURCE == 199309 1003.1b-1993 * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, * and the omnibus ISO/IEC 9945-1: 1996 * _POSIX_C_SOURCE == 200112 1003.1-2001 * _POSIX_C_SOURCE == 200809 1003.1-2008 * * In addition, the X/Open Portability Guide, which is now the Single UNIX * Specification, defines a feature-test macro which indicates the version of * that specification, and which subsumes _POSIX_C_SOURCE. * * Our macros begin with two underscores to avoid namespace screwage. */ /* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ #if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1 #undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */ #define _POSIX_C_SOURCE 199009 #endif /* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ #if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2 #undef _POSIX_C_SOURCE #define _POSIX_C_SOURCE 199209 #endif /* Deal with various X/Open Portability Guides and Single UNIX Spec. */ #ifdef _XOPEN_SOURCE #if _XOPEN_SOURCE - 0 >= 700 #define __XSI_VISIBLE 700 #undef _POSIX_C_SOURCE #define _POSIX_C_SOURCE 200809 #elif _XOPEN_SOURCE - 0 >= 600 #define __XSI_VISIBLE 600 #undef _POSIX_C_SOURCE #define _POSIX_C_SOURCE 200112 #elif _XOPEN_SOURCE - 0 >= 500 #define __XSI_VISIBLE 500 #undef _POSIX_C_SOURCE #define _POSIX_C_SOURCE 199506 #endif #endif /* * Deal with all versions of POSIX. The ordering relative to the tests above is * important. */ #if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) #define _POSIX_C_SOURCE 198808 #endif #ifdef _POSIX_C_SOURCE #if _POSIX_C_SOURCE >= 200809 #define __POSIX_VISIBLE 200809 #define __ISO_C_VISIBLE 1999 #elif _POSIX_C_SOURCE >= 200112 #define __POSIX_VISIBLE 200112 #define __ISO_C_VISIBLE 1999 #elif _POSIX_C_SOURCE >= 199506 #define __POSIX_VISIBLE 199506 #define __ISO_C_VISIBLE 1990 #elif _POSIX_C_SOURCE >= 199309 #define __POSIX_VISIBLE 199309 #define __ISO_C_VISIBLE 1990 #elif _POSIX_C_SOURCE >= 199209 #define __POSIX_VISIBLE 199209 #define __ISO_C_VISIBLE 1990 #elif _POSIX_C_SOURCE >= 199009 #define __POSIX_VISIBLE 199009 #define __ISO_C_VISIBLE 1990 #else #define __POSIX_VISIBLE 198808 #define __ISO_C_VISIBLE 0 #endif /* _POSIX_C_SOURCE */ #else /*- * Deal with _ANSI_SOURCE: * If it is defined, and no other compilation environment is explicitly * requested, then define our internal feature-test macros to zero. This * makes no difference to the preprocessor (undefined symbols in preprocessing * expressions are defined to have value zero), but makes it more convenient for * a test program to print out the values. * * If a program mistakenly defines _ANSI_SOURCE and some other macro such as * _POSIX_C_SOURCE, we will assume that it wants the broader compilation * environment (and in fact we will never get here). */ #if defined(_ANSI_SOURCE) /* Hide almost everything. */ #define __POSIX_VISIBLE 0 #define __XSI_VISIBLE 0 #define __BSD_VISIBLE 0 #define __ISO_C_VISIBLE 1990 #elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */ #define __POSIX_VISIBLE 0 #define __XSI_VISIBLE 0 #define __BSD_VISIBLE 0 #define __ISO_C_VISIBLE 1999 #else /* Default environment: show everything. */ #define __POSIX_VISIBLE 200809 #define __XSI_VISIBLE 700 #define __BSD_VISIBLE 1 #define __ISO_C_VISIBLE 1999 #endif #endif #ifndef __has_feature #define __has_feature(x) 0 #endif #ifndef __has_include #define __has_include(x) 0 #endif #ifndef __has_builtin #define __has_builtin(x) 0 #endif #if defined(__mips) || defined(__powerpc64__) || defined(__arm__) #define __NO_TLS 1 #endif #endif /* !_SYS_CDEFS_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/ctype.h000066400000000000000000000051621322600646200232270ustar00rootroot00000000000000/*- * Copyright (c) 1982, 1988, 1991, 1993 * The Regents of the University of California. All rights reserved. * (c) UNIX System Laboratories, Inc. * All or some portions of this file are derived from material licensed * to the University of California by American Telephone and Telegraph * Co. or Unix System Laboratories, Inc. and are reproduced herein with * the permission of UNIX System Laboratories, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Portions copyright (c) 2009-2014, ARM Limited and Contributors. * All rights reserved. */ #ifndef _SYS_CTYPE_H_ #define _SYS_CTYPE_H_ #define isspace(c) ((c) == ' ' || ((c) >= '\t' && (c) <= '\r')) #define isascii(c) (((c) & ~0x7f) == 0) #define isupper(c) ((c) >= 'A' && (c) <= 'Z') #define islower(c) ((c) >= 'a' && (c) <= 'z') #define isalpha(c) (isupper(c) || islower(c)) #define isdigit(c) ((c) >= '0' && (c) <= '9') #define isxdigit(c) (isdigit(c) \ || ((c) >= 'A' && (c) <= 'F') \ || ((c) >= 'a' && (c) <= 'f')) #define isprint(c) ((c) >= ' ' && (c) <= '~') #define toupper(c) ((c) - 0x20 * (((c) >= 'a') && ((c) <= 'z'))) #define tolower(c) ((c) + 0x20 * (((c) >= 'A') && ((c) <= 'Z'))) #endif /* !_SYS_CTYPE_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/errno.h000066400000000000000000000174311322600646200232320ustar00rootroot00000000000000/*- * Copyright (c) 1982, 1986, 1989, 1993 * The Regents of the University of California. All rights reserved. * (c) UNIX System Laboratories, Inc. * All or some portions of this file are derived from material licensed * to the University of California by American Telephone and Telegraph * Co. or Unix System Laboratories, Inc. and are reproduced herein with * the permission of UNIX System Laboratories, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)errno.h 8.5 (Berkeley) 1/21/94 * $FreeBSD$ */ #ifndef _SYS_ERRNO_H_ #define _SYS_ERRNO_H_ #ifndef _KERNEL #include __BEGIN_DECLS int * __error(void); __END_DECLS #define errno (* __error()) #endif #define EPERM 1 /* Operation not permitted */ #define ENOENT 2 /* No such file or directory */ #define ESRCH 3 /* No such process */ #define EINTR 4 /* Interrupted system call */ #define EIO 5 /* Input/output error */ #define ENXIO 6 /* Device not configured */ #define E2BIG 7 /* Argument list too long */ #define ENOEXEC 8 /* Exec format error */ #define EBADF 9 /* Bad file descriptor */ #define ECHILD 10 /* No child processes */ #define EDEADLK 11 /* Resource deadlock avoided */ /* 11 was EAGAIN */ #define ENOMEM 12 /* Cannot allocate memory */ #define EACCES 13 /* Permission denied */ #define EFAULT 14 /* Bad address */ #ifndef _POSIX_SOURCE #define ENOTBLK 15 /* Block device required */ #endif #define EBUSY 16 /* Device busy */ #define EEXIST 17 /* File exists */ #define EXDEV 18 /* Cross-device link */ #define ENODEV 19 /* Operation not supported by device */ #define ENOTDIR 20 /* Not a directory */ #define EISDIR 21 /* Is a directory */ #define EINVAL 22 /* Invalid argument */ #define ENFILE 23 /* Too many open files in system */ #define EMFILE 24 /* Too many open files */ #define ENOTTY 25 /* Inappropriate ioctl for device */ #ifndef _POSIX_SOURCE #define ETXTBSY 26 /* Text file busy */ #endif #define EFBIG 27 /* File too large */ #define ENOSPC 28 /* No space left on device */ #define ESPIPE 29 /* Illegal seek */ #define EROFS 30 /* Read-only filesystem */ #define EMLINK 31 /* Too many links */ #define EPIPE 32 /* Broken pipe */ /* math software */ #define EDOM 33 /* Numerical argument out of domain */ #define ERANGE 34 /* Result too large */ /* non-blocking and interrupt i/o */ #define EAGAIN 35 /* Resource temporarily unavailable */ #ifndef _POSIX_SOURCE #define EWOULDBLOCK EAGAIN /* Operation would block */ #define EINPROGRESS 36 /* Operation now in progress */ #define EALREADY 37 /* Operation already in progress */ /* ipc/network software -- argument errors */ #define ENOTSOCK 38 /* Socket operation on non-socket */ #define EDESTADDRREQ 39 /* Destination address required */ #define EMSGSIZE 40 /* Message too long */ #define EPROTOTYPE 41 /* Protocol wrong type for socket */ #define ENOPROTOOPT 42 /* Protocol not available */ #define EPROTONOSUPPORT 43 /* Protocol not supported */ #define ESOCKTNOSUPPORT 44 /* Socket type not supported */ #define EOPNOTSUPP 45 /* Operation not supported */ #define ENOTSUP EOPNOTSUPP /* Operation not supported */ #define EPFNOSUPPORT 46 /* Protocol family not supported */ #define EAFNOSUPPORT 47 /* Address family not supported by protocol family */ #define EADDRINUSE 48 /* Address already in use */ #define EADDRNOTAVAIL 49 /* Can't assign requested address */ /* ipc/network software -- operational errors */ #define ENETDOWN 50 /* Network is down */ #define ENETUNREACH 51 /* Network is unreachable */ #define ENETRESET 52 /* Network dropped connection on reset */ #define ECONNABORTED 53 /* Software caused connection abort */ #define ECONNRESET 54 /* Connection reset by peer */ #define ENOBUFS 55 /* No buffer space available */ #define EISCONN 56 /* Socket is already connected */ #define ENOTCONN 57 /* Socket is not connected */ #define ESHUTDOWN 58 /* Can't send after socket shutdown */ #define ETOOMANYREFS 59 /* Too many references: can't splice */ #define ETIMEDOUT 60 /* Operation timed out */ #define ECONNREFUSED 61 /* Connection refused */ #define ELOOP 62 /* Too many levels of symbolic links */ #endif /* _POSIX_SOURCE */ #define ENAMETOOLONG 63 /* File name too long */ /* should be rearranged */ #ifndef _POSIX_SOURCE #define EHOSTDOWN 64 /* Host is down */ #define EHOSTUNREACH 65 /* No route to host */ #endif /* _POSIX_SOURCE */ #define ENOTEMPTY 66 /* Directory not empty */ /* quotas & mush */ #ifndef _POSIX_SOURCE #define EPROCLIM 67 /* Too many processes */ #define EUSERS 68 /* Too many users */ #define EDQUOT 69 /* Disc quota exceeded */ /* Network File System */ #define ESTALE 70 /* Stale NFS file handle */ #define EREMOTE 71 /* Too many levels of remote in path */ #define EBADRPC 72 /* RPC struct is bad */ #define ERPCMISMATCH 73 /* RPC version wrong */ #define EPROGUNAVAIL 74 /* RPC prog. not avail */ #define EPROGMISMATCH 75 /* Program version wrong */ #define EPROCUNAVAIL 76 /* Bad procedure for program */ #endif /* _POSIX_SOURCE */ #define ENOLCK 77 /* No locks available */ #define ENOSYS 78 /* Function not implemented */ #ifndef _POSIX_SOURCE #define EFTYPE 79 /* Inappropriate file type or format */ #define EAUTH 80 /* Authentication error */ #define ENEEDAUTH 81 /* Need authenticator */ #define EIDRM 82 /* Identifier removed */ #define ENOMSG 83 /* No message of desired type */ #define EOVERFLOW 84 /* Value too large to be stored in data type */ #define ECANCELED 85 /* Operation canceled */ #define EILSEQ 86 /* Illegal byte sequence */ #define ENOATTR 87 /* Attribute not found */ #define EDOOFUS 88 /* Programming error */ #endif /* _POSIX_SOURCE */ #define EBADMSG 89 /* Bad message */ #define EMULTIHOP 90 /* Multihop attempted */ #define ENOLINK 91 /* Link has been severed */ #define EPROTO 92 /* Protocol error */ #ifndef _POSIX_SOURCE #define ENOTCAPABLE 93 /* Capabilities insufficient */ #define ECAPMODE 94 /* Not permitted in capability mode */ #endif /* _POSIX_SOURCE */ #ifndef _POSIX_SOURCE #define ELAST 94 /* Must be equal largest errno */ #endif /* _POSIX_SOURCE */ #ifdef _KERNEL /* pseudo-errors returned inside kernel to modify return to process */ #define ERESTART (-1) /* restart syscall */ #define EJUSTRETURN (-2) /* don't modify regs, just return */ #define ENOIOCTL (-3) /* ioctl not handled by this layer */ #define EDIRIOCTL (-4) /* do direct ioctl in GEOM */ #endif #endif arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/limits.h000066400000000000000000000072271322600646200234100ustar00rootroot00000000000000/*- * Copyright (c) 1988, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _SYS_LIMITS_H_ #define _SYS_LIMITS_H_ #include #include #define CHAR_BIT __CHAR_BIT /* number of bits in a char */ #define SCHAR_MAX __SCHAR_MAX /* max value for a signed char */ #define SCHAR_MIN __SCHAR_MIN /* min value for a signed char */ #define UCHAR_MAX __UCHAR_MAX /* max value for an unsigned char */ #ifdef __CHAR_UNSIGNED__ #define CHAR_MAX UCHAR_MAX /* max value for a char */ #define CHAR_MIN 0 /* min value for a char */ #else #define CHAR_MAX SCHAR_MAX #define CHAR_MIN SCHAR_MIN #endif #define USHRT_MAX __USHRT_MAX /* max value for an unsigned short */ #define SHRT_MAX __SHRT_MAX /* max value for a short */ #define SHRT_MIN __SHRT_MIN /* min value for a short */ #define UINT_MAX __UINT_MAX /* max value for an unsigned int */ #define INT_MAX __INT_MAX /* max value for an int */ #define INT_MIN __INT_MIN /* min value for an int */ #define ULONG_MAX __ULONG_MAX /* max for an unsigned long */ #define LONG_MAX __LONG_MAX /* max for a long */ #define LONG_MIN __LONG_MIN /* min for a long */ #ifdef __LONG_LONG_SUPPORTED #define ULLONG_MAX __ULLONG_MAX /* max for an unsigned long long */ #define LLONG_MAX __LLONG_MAX /* max for a long long */ #define LLONG_MIN __LLONG_MIN /* min for a long long */ #endif #if __POSIX_VISIBLE || __XSI_VISIBLE #define SSIZE_MAX __SSIZE_MAX /* max value for an ssize_t */ #endif #if __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE #define SIZE_T_MAX __SIZE_T_MAX /* max value for a size_t */ #define OFF_MAX __OFF_MAX /* max value for an off_t */ #define OFF_MIN __OFF_MIN /* min value for an off_t */ #endif #if __BSD_VISIBLE #define GID_MAX UINT_MAX /* max value for a gid_t */ #define UID_MAX UINT_MAX /* max value for a uid_t */ #define UQUAD_MAX (__UQUAD_MAX) /* max value for a uquad_t */ #define QUAD_MAX (__QUAD_MAX) /* max value for a quad_t */ #define QUAD_MIN (__QUAD_MIN) /* min value for a quad_t */ #endif #if __XSI_VISIBLE || __POSIX_VISIBLE >= 200809 #define LONG_BIT __LONG_BIT #define WORD_BIT __WORD_BIT #endif #if __POSIX_VISIBLE #define MQ_PRIO_MAX 64 #endif #endif /* !_SYS_LIMITS_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/stdarg.h000066400000000000000000000050121322600646200233610ustar00rootroot00000000000000/*- * Copyright (c) 2002 David E. O'Brien. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_STDARG_H_ #define _MACHINE_STDARG_H_ #include #include #ifndef _VA_LIST_DECLARED #define _VA_LIST_DECLARED typedef __va_list va_list; #endif #ifdef __GNUCLIKE_BUILTIN_STDARG #define va_start(ap, last) \ __builtin_va_start((ap), (last)) #define va_arg(ap, type) \ __builtin_va_arg((ap), type) #define __va_copy(dest, src) \ __builtin_va_copy((dest), (src)) #if __ISO_C_VISIBLE >= 1999 #define va_copy(dest, src) \ __va_copy(dest, src) #endif #define va_end(ap) \ __builtin_va_end(ap) #elif defined(lint) /* Provide a fake implementation for lint's benefit */ #define __va_size(type) \ (((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long)) #define va_start(ap, last) \ ((ap) = (va_list)&(last) + __va_size(last)) #define va_arg(ap, type) \ (*(type *)((ap) += __va_size(type), (ap) - __va_size(type))) #define va_end(ap) #else #error this file needs to be ported to your compiler #endif #endif /* !_MACHINE_STDARG_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/stdint.h000066400000000000000000000050511322600646200234050ustar00rootroot00000000000000/*- * Copyright (c) 2001 Mike Barcroft * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _SYS_STDINT_H_ #define _SYS_STDINT_H_ #include #include #include #include typedef __int_least8_t int_least8_t; typedef __int_least16_t int_least16_t; typedef __int_least32_t int_least32_t; typedef __int_least64_t int_least64_t; typedef __uint_least8_t uint_least8_t; typedef __uint_least16_t uint_least16_t; typedef __uint_least32_t uint_least32_t; typedef __uint_least64_t uint_least64_t; typedef __int_fast8_t int_fast8_t; typedef __int_fast16_t int_fast16_t; typedef __int_fast32_t int_fast32_t; typedef __int_fast64_t int_fast64_t; typedef __uint_fast8_t uint_fast8_t; typedef __uint_fast16_t uint_fast16_t; typedef __uint_fast32_t uint_fast32_t; typedef __uint_fast64_t uint_fast64_t; #ifndef _INTMAX_T_DECLARED typedef __intmax_t intmax_t; #define _INTMAX_T_DECLARED #endif #ifndef _UINTMAX_T_DECLARED typedef __uintmax_t uintmax_t; #define _UINTMAX_T_DECLARED #endif /* GNU and Darwin define this and people seem to think it's portable */ #if defined(UINTPTR_MAX) && defined(UINT64_MAX) && (UINTPTR_MAX == UINT64_MAX) #define __WORDSIZE 64 #else #define __WORDSIZE 32 #endif #endif /* !_SYS_STDINT_H_ */ arm-trusted-firmware-1.0-aw-6/include/stdlib/sys/uuid.h000066400000000000000000000040241322600646200230450ustar00rootroot00000000000000/*- * Copyright (c) 2002 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ /* * Portions copyright (c) 2014, ARM Limited and Contributors. * All rights reserved. */ #ifndef _SYS_UUID_H_ #define _SYS_UUID_H_ #include /* Length of a node address (an IEEE 802 address). */ #define _UUID_NODE_LEN 6 /* * See also: * http://www.opengroup.org/dce/info/draft-leach-uuids-guids-01.txt * http://www.opengroup.org/onlinepubs/009629399/apdxa.htm * * A DCE 1.1 compatible source representation of UUIDs. */ struct uuid { uint32_t time_low; uint16_t time_mid; uint16_t time_hi_and_version; uint8_t clock_seq_hi_and_reserved; uint8_t clock_seq_low; uint8_t node[_UUID_NODE_LEN]; }; /* XXX namespace pollution? */ typedef struct uuid uuid_t; #endif /* _SYS_UUID_H_ */ arm-trusted-firmware-1.0-aw-6/lib/000077500000000000000000000000001322600646200167525ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/aarch64/000077500000000000000000000000001322600646200202025ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/aarch64/cache_helpers.S000066400000000000000000000116731322600646200231230ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include .globl flush_dcache_range .globl inv_dcache_range .globl dcsw_op_louis .globl dcsw_op_all /* ------------------------------------------ * Clean+Invalidate from base address till * size. 'x0' = addr, 'x1' = size * ------------------------------------------ */ func flush_dcache_range dcache_line_size x2, x3 add x1, x0, x1 sub x3, x2, #1 bic x0, x0, x3 flush_loop: dc civac, x0 add x0, x0, x2 cmp x0, x1 b.lo flush_loop dsb sy ret /* ------------------------------------------ * Invalidate from base address till * size. 'x0' = addr, 'x1' = size * ------------------------------------------ */ func inv_dcache_range dcache_line_size x2, x3 add x1, x0, x1 sub x3, x2, #1 bic x0, x0, x3 inv_loop: dc ivac, x0 add x0, x0, x2 cmp x0, x1 b.lo inv_loop dsb sy ret /* --------------------------------------------------------------- * Data cache operations by set/way to the level specified * * The main function, do_dcsw_op requires: * x0: The operation type (0-2), as defined in arch.h * x3: The last cache level to operate on * x9: clidr_el1 * and will carry out the operation on each data cache from level 0 * to the level in x3 in sequence * * The dcsw_op macro sets up the x3 and x9 parameters based on * clidr_el1 cache information before invoking the main function * --------------------------------------------------------------- */ .macro dcsw_op shift, fw, ls mrs x9, clidr_el1 ubfx x3, x9, \shift, \fw lsl x3, x3, \ls b do_dcsw_op .endm func do_dcsw_op cbz x3, exit mov x10, xzr adr x14, dcsw_loop_table // compute inner loop address add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions mov x0, x9 mov w8, #1 loop1: add x2, x10, x10, lsr #1 // work out 3x current cache level lsr x1, x0, x2 // extract cache type bits from clidr and x1, x1, #7 // mask the bits for current cache only cmp x1, #2 // see what cache we have at this level b.lt level_done // nothing to do if no cache or icache msr csselr_el1, x10 // select current cache level in csselr isb // isb to sych the new cssr&csidr mrs x1, ccsidr_el1 // read the new ccsidr and x2, x1, #7 // extract the length of the cache lines add x2, x2, #4 // add 4 (line length offset) ubfx x4, x1, #3, #10 // maximum way number clz w5, w4 // bit position of way size increment lsl w9, w4, w5 // w9 = aligned max way number lsl w16, w8, w5 // w16 = way number loop decrement orr w9, w10, w9 // w9 = combine way and cache number ubfx w6, w1, #13, #15 // w6 = max set number lsl w17, w8, w2 // w17 = set number loop decrement dsb sy // barrier before we start this level br x14 // jump to DC operation specific loop .macro dcsw_loop _op loop2_\_op: lsl w7, w6, w2 // w7 = aligned max set number loop3_\_op: orr w11, w9, w7 // combine cache, way and set number dc \_op, x11 subs w7, w7, w17 // decrement set number b.ge loop3_\_op subs x9, x9, x16 // decrement way number b.ge loop2_\_op b level_done .endm level_done: add x10, x10, #2 // increment cache number cmp x3, x10 b.gt loop1 msr csselr_el1, xzr // select cache level 0 in csselr dsb sy // barrier to complete final cache operation isb exit: ret dcsw_loop_table: dcsw_loop isw dcsw_loop cisw dcsw_loop csw func dcsw_op_louis dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT func dcsw_op_all dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT arm-trusted-firmware-1.0-aw-6/lib/aarch64/misc_helpers.S000066400000000000000000000107151322600646200230070ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include .globl get_afflvl_shift .globl mpidr_mask_lower_afflvls .globl eret .globl smc .globl zeromem16 .globl memcpy16 .globl disable_mmu_el3 .globl disable_mmu_icache_el3 #if SUPPORT_VFP .globl enable_vfp #endif func get_afflvl_shift cmp x0, #3 cinc x0, x0, eq mov x1, #MPIDR_AFFLVL_SHIFT lsl x0, x0, x1 ret func mpidr_mask_lower_afflvls cmp x1, #3 cinc x1, x1, eq mov x2, #MPIDR_AFFLVL_SHIFT lsl x2, x1, x2 lsr x0, x0, x2 lsl x0, x0, x2 ret func eret eret func smc smc #0 /* ----------------------------------------------------------------------- * void zeromem16(void *mem, unsigned int length); * * Initialise a memory region to 0. * The memory address must be 16-byte aligned. * ----------------------------------------------------------------------- */ func zeromem16 #if ASM_ASSERTION tst x0, #0xf ASM_ASSERT(eq) #endif add x2, x0, x1 /* zero 16 bytes at a time */ z_loop16: sub x3, x2, x0 cmp x3, #16 b.lt z_loop1 stp xzr, xzr, [x0], #16 b z_loop16 /* zero byte per byte */ z_loop1: cmp x0, x2 b.eq z_end strb wzr, [x0], #1 b z_loop1 z_end: ret /* -------------------------------------------------------------------------- * void memcpy16(void *dest, const void *src, unsigned int length) * * Copy length bytes from memory area src to memory area dest. * The memory areas should not overlap. * Destination and source addresses must be 16-byte aligned. * -------------------------------------------------------------------------- */ func memcpy16 #if ASM_ASSERTION orr x3, x0, x1 tst x3, #0xf ASM_ASSERT(eq) #endif /* copy 16 bytes at a time */ m_loop16: cmp x2, #16 b.lt m_loop1 ldp x3, x4, [x1], #16 stp x3, x4, [x0], #16 sub x2, x2, #16 b m_loop16 /* copy byte per byte */ m_loop1: cbz x2, m_end ldrb w3, [x1], #1 strb w3, [x0], #1 subs x2, x2, #1 b.ne m_loop1 m_end: ret /* --------------------------------------------------------------------------- * Disable the MMU at EL3 * This is implemented in assembler to ensure that the data cache is cleaned * and invalidated after the MMU is disabled without any intervening cacheable * data accesses * --------------------------------------------------------------------------- */ func disable_mmu_el3 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT) do_disable_mmu: mrs x0, sctlr_el3 bic x0, x0, x1 msr sctlr_el3, x0 isb // ensure MMU is off mov x0, #DCCISW // DCache clean and invalidate b dcsw_op_all func disable_mmu_icache_el3 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) b do_disable_mmu /* --------------------------------------------------------------------------- * Enable the use of VFP at EL3 * --------------------------------------------------------------------------- */ #if SUPPORT_VFP func enable_vfp mrs x0, cpacr_el1 orr x0, x0, #CPACR_VFP_BITS msr cpacr_el1, x0 mrs x0, cptr_el3 mov x1, #AARCH64_CPTR_TFP bic x0, x0, x1 msr cptr_el3, x0 isb ret #endif arm-trusted-firmware-1.0-aw-6/lib/aarch64/xlat_helpers.c000066400000000000000000000113211322600646200230360ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include /******************************************************************************* * Helper to create a level 1/2 table descriptor which points to a level 2/3 * table. ******************************************************************************/ unsigned long create_table_desc(unsigned long *next_table_ptr) { unsigned long desc = (unsigned long) next_table_ptr; /* Clear the last 12 bits */ desc >>= FOUR_KB_SHIFT; desc <<= FOUR_KB_SHIFT; desc |= TABLE_DESC; return desc; } /******************************************************************************* * Helper to create a level 1/2/3 block descriptor which maps the va to addr ******************************************************************************/ unsigned long create_block_desc(unsigned long desc, unsigned long addr, unsigned int level) { switch (level) { case LEVEL1: desc |= (addr << FIRST_LEVEL_DESC_N) | BLOCK_DESC; break; case LEVEL2: desc |= (addr << SECOND_LEVEL_DESC_N) | BLOCK_DESC; break; case LEVEL3: desc |= (addr << THIRD_LEVEL_DESC_N) | TABLE_DESC; break; default: assert(0); } return desc; } /******************************************************************************* * Helper to create a level 1/2/3 block descriptor which maps the va to output_ * addr with Device nGnRE attributes. ******************************************************************************/ unsigned long create_device_block(unsigned long output_addr, unsigned int level, unsigned int ns) { unsigned long upper_attrs, lower_attrs, desc; lower_attrs = LOWER_ATTRS(ACCESS_FLAG | OSH | AP_RW); lower_attrs |= LOWER_ATTRS(ns | ATTR_DEVICE_INDEX); upper_attrs = UPPER_ATTRS(XN); desc = upper_attrs | lower_attrs; return create_block_desc(desc, output_addr, level); } /******************************************************************************* * Helper to create a level 1/2/3 block descriptor which maps the va to output_ * addr with inner-shareable normal wbwa read-only memory attributes. ******************************************************************************/ unsigned long create_romem_block(unsigned long output_addr, unsigned int level, unsigned int ns) { unsigned long upper_attrs, lower_attrs, desc; lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RO); lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); upper_attrs = UPPER_ATTRS(0ull); desc = upper_attrs | lower_attrs; return create_block_desc(desc, output_addr, level); } /******************************************************************************* * Helper to create a level 1/2/3 block descriptor which maps the va to output_ * addr with inner-shareable normal wbwa read-write memory attributes. ******************************************************************************/ unsigned long create_rwmem_block(unsigned long output_addr, unsigned int level, unsigned int ns) { unsigned long upper_attrs, lower_attrs, desc; lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RW); lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); upper_attrs = UPPER_ATTRS(XN); desc = upper_attrs | lower_attrs; return create_block_desc(desc, output_addr, level); } arm-trusted-firmware-1.0-aw-6/lib/aarch64/xlat_tables.c000066400000000000000000000236171322600646200226610ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #ifndef DEBUG_XLAT_TABLE #define DEBUG_XLAT_TABLE 0 #endif #if DEBUG_XLAT_TABLE #define debug_print(...) printf(__VA_ARGS__) #else #define debug_print(...) ((void)0) #endif CASSERT(ADDR_SPACE_SIZE > 0, assert_valid_addr_space_size); #define UNSET_DESC ~0ul #define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) static uint64_t l1_xlation_table[NUM_L1_ENTRIES] __aligned(NUM_L1_ENTRIES * sizeof(uint64_t)); static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] __aligned(XLAT_TABLE_SIZE) __attribute__((section("xlat_table"))); static unsigned next_xlat; static unsigned long max_pa; static unsigned long max_va; static unsigned long tcr_ps_bits; /* * Array of all memory regions stored in order of ascending base address. * The list is terminated by the first entry with size == 0. */ static mmap_region_t mmap[MAX_MMAP_REGIONS + 1]; static void print_mmap(void) { #if DEBUG_XLAT_TABLE debug_print("mmap:\n"); mmap_region_t *mm = mmap; while (mm->size) { debug_print(" %010lx %010lx %10lx %x\n", mm->base_va, mm->base_pa, mm->size, mm->attr); ++mm; }; debug_print("\n"); #endif } void mmap_add_region(unsigned long base_pa, unsigned long base_va, unsigned long size, unsigned attr) { mmap_region_t *mm = mmap; mmap_region_t *mm_last = mm + sizeof(mmap) / sizeof(mmap[0]) - 1; unsigned long pa_end = base_pa + size - 1; unsigned long va_end = base_va + size - 1; assert(IS_PAGE_ALIGNED(base_pa)); assert(IS_PAGE_ALIGNED(base_va)); assert(IS_PAGE_ALIGNED(size)); if (!size) return; /* Find correct place in mmap to insert new region */ while (mm->base_va < base_va && mm->size) ++mm; /* Make room for new region by moving other regions up by one place */ memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); /* Check we haven't lost the empty sentinal from the end of the array */ assert(mm_last->size == 0); mm->base_pa = base_pa; mm->base_va = base_va; mm->size = size; mm->attr = attr; if (pa_end > max_pa) max_pa = pa_end; if (va_end > max_va) max_va = va_end; } void mmap_add(const mmap_region_t *mm) { while (mm->size) { mmap_add_region(mm->base_pa, mm->base_va, mm->size, mm->attr); ++mm; } } static unsigned long mmap_desc(unsigned attr, unsigned long addr_pa, unsigned level) { unsigned long desc = addr_pa; desc |= level == 3 ? TABLE_DESC : BLOCK_DESC; desc |= attr & MT_NS ? LOWER_ATTRS(NS) : 0; desc |= attr & MT_RW ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO); desc |= LOWER_ATTRS(ACCESS_FLAG); if (attr & MT_MEMORY) { desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH); if (attr & MT_RW) desc |= UPPER_ATTRS(XN); } else { desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH); desc |= UPPER_ATTRS(XN); } debug_print(attr & MT_MEMORY ? "MEM" : "DEV"); debug_print(attr & MT_RW ? "-RW" : "-RO"); debug_print(attr & MT_NS ? "-NS" : "-S"); return desc; } static int mmap_region_attr(mmap_region_t *mm, unsigned long base_va, unsigned long size) { int attr = mm->attr; for (;;) { ++mm; if (!mm->size) return attr; /* Reached end of list */ if (mm->base_va >= base_va + size) return attr; /* Next region is after area so end */ if (mm->base_va + mm->size <= base_va) continue; /* Next region has already been overtaken */ if ((mm->attr & attr) == attr) continue; /* Region doesn't override attribs so skip */ attr &= mm->attr; if (mm->base_va > base_va || mm->base_va + mm->size < base_va + size) return -1; /* Region doesn't fully cover our area */ } } static mmap_region_t *init_xlation_table(mmap_region_t *mm, unsigned long base_va, unsigned long *table, unsigned level) { unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) * XLAT_TABLE_ENTRIES_SHIFT; unsigned level_size = 1 << level_size_shift; unsigned long level_index_mask = XLAT_TABLE_ENTRIES_MASK << level_size_shift; assert(level <= 3); debug_print("New xlat table:\n"); do { unsigned long desc = UNSET_DESC; if (mm->base_va + mm->size <= base_va) { /* Area now after the region so skip it */ ++mm; continue; } debug_print(" %010lx %8lx " + 6 - 2 * level, base_va, level_size); if (mm->base_va >= base_va + level_size) { /* Next region is after area so nothing to map yet */ desc = INVALID_DESC; } else if (mm->base_va <= base_va && mm->base_va + mm->size >= base_va + level_size) { /* Next region covers all of area */ int attr = mmap_region_attr(mm, base_va, level_size); if (attr >= 0) desc = mmap_desc(attr, base_va - mm->base_va + mm->base_pa, level); } /* else Next region only partially covers area, so need */ if (desc == UNSET_DESC) { /* Area not covered by a region so need finer table */ unsigned long *new_table = xlat_tables[next_xlat++]; assert(next_xlat <= MAX_XLAT_TABLES); desc = TABLE_DESC | (unsigned long)new_table; /* Recurse to fill in new table */ mm = init_xlation_table(mm, base_va, new_table, level+1); } debug_print("\n"); *table++ = desc; base_va += level_size; } while (mm->size && (base_va & level_index_mask)); return mm; } static unsigned int calc_physical_addr_size_bits(unsigned long max_addr) { /* Physical address can't exceed 48 bits */ assert((max_addr & ADDR_MASK_48_TO_63) == 0); /* 48 bits address */ if (max_addr & ADDR_MASK_44_TO_47) return TCR_PS_BITS_256TB; /* 44 bits address */ if (max_addr & ADDR_MASK_42_TO_43) return TCR_PS_BITS_16TB; /* 42 bits address */ if (max_addr & ADDR_MASK_40_TO_41) return TCR_PS_BITS_4TB; /* 40 bits address */ if (max_addr & ADDR_MASK_36_TO_39) return TCR_PS_BITS_1TB; /* 36 bits address */ if (max_addr & ADDR_MASK_32_TO_35) return TCR_PS_BITS_64GB; return TCR_PS_BITS_4GB; } void init_xlat_tables(void) { print_mmap(); init_xlation_table(mmap, 0, l1_xlation_table, 1); tcr_ps_bits = calc_physical_addr_size_bits(max_pa); assert(max_va < ADDR_SPACE_SIZE); } /******************************************************************************* * Macro generating the code for the function enabling the MMU in the given * exception level, assuming that the pagetables have already been created. * * _el: Exception level at which the function will run * _tcr_extra: Extra bits to set in the TCR register. This mask will * be OR'ed with the default TCR value. * _tlbi_fct: Function to invalidate the TLBs at the current * exception level ******************************************************************************/ #define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \ void enable_mmu_el##_el(uint32_t flags) \ { \ uint64_t mair, tcr, ttbr; \ uint32_t sctlr; \ \ assert(IS_IN_EL(_el)); \ assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \ \ /* Set attributes in the right indices of the MAIR */ \ mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \ mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \ ATTR_IWBWA_OWBWA_NTR_INDEX); \ write_mair_el##_el(mair); \ \ /* Invalidate TLBs at the current exception level */ \ _tlbi_fct(); \ \ /* Set TCR bits as well. */ \ /* Inner & outer WBWA & shareable + T0SZ = 32 */ \ tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \ TCR_RGN_INNER_WBA | \ (64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \ tcr |= _tcr_extra; \ write_tcr_el##_el(tcr); \ \ /* Set TTBR bits as well */ \ ttbr = (uint64_t) l1_xlation_table; \ write_ttbr0_el##_el(ttbr); \ \ /* Ensure all translation table writes have drained */ \ /* into memory, the TLB invalidation is complete, */ \ /* and translation register writes are committed */ \ /* before enabling the MMU */ \ dsb(); \ isb(); \ \ sctlr = read_sctlr_el##_el(); \ sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ \ if (flags & DISABLE_DCACHE) \ sctlr &= ~SCTLR_C_BIT; \ else \ sctlr |= SCTLR_C_BIT; \ \ write_sctlr_el##_el(sctlr); \ \ /* Ensure the MMU enable takes effect immediately */ \ isb(); \ } /* Define EL1 and EL3 variants of the function enabling the MMU */ DEFINE_ENABLE_MMU_EL(1, (tcr_ps_bits << TCR_EL1_IPS_SHIFT), tlbivmalle1) DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT), tlbialle3) arm-trusted-firmware-1.0-aw-6/lib/cpus/000077500000000000000000000000001322600646200177245ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/cpus/aarch64/000077500000000000000000000000001322600646200211545ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/cpus/aarch64/aem_generic.S000066400000000000000000000057351322600646200235500ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include func aem_generic_core_pwr_dwn /* --------------------------------------------- * Disable the Data Cache. * --------------------------------------------- */ mrs x1, sctlr_el3 bic x1, x1, #SCTLR_C_BIT msr sctlr_el3, x1 isb mov x0, #DCCISW /* --------------------------------------------- * Flush L1 cache to PoU. * --------------------------------------------- */ b dcsw_op_louis func aem_generic_cluster_pwr_dwn /* --------------------------------------------- * Disable the Data Cache. * --------------------------------------------- */ mrs x1, sctlr_el3 bic x1, x1, #SCTLR_C_BIT msr sctlr_el3, x1 isb /* --------------------------------------------- * Flush L1 and L2 caches to PoC. * --------------------------------------------- */ mov x0, #DCCISW b dcsw_op_all /* --------------------------------------------- * This function provides cpu specific * register information for crash reporting. * It needs to return with x6 pointing to * a list of register names in ascii and * x8 - x15 having values of registers to be * reported. * --------------------------------------------- */ func aem_generic_cpu_reg_dump mov x6, #0 /* no registers to report */ ret /* cpu_ops for Base AEM FVP */ declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1 /* cpu_ops for Foundation FVP */ declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, 1 arm-trusted-firmware-1.0-aw-6/lib/cpus/aarch64/cortex_a53.S000066400000000000000000000103621322600646200232560ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include /* --------------------------------------------- * Disable L1 data cache and unified L2 cache * --------------------------------------------- */ func cortex_a53_disable_dcache mrs x1, sctlr_el3 bic x1, x1, #SCTLR_C_BIT msr sctlr_el3, x1 isb ret /* --------------------------------------------- * Disable intra-cluster coherency * --------------------------------------------- */ func cortex_a53_disable_smp mrs x0, CPUECTLR_EL1 bic x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 isb dsb sy ret func cortex_a53_reset_func /* --------------------------------------------- * As a bare minimum enable the SMP bit. * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 isb ret func cortex_a53_core_pwr_dwn mov x18, x30 /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache /* --------------------------------------------- * Flush L1 cache to PoU. * --------------------------------------------- */ mov x0, #DCCISW bl dcsw_op_louis /* --------------------------------------------- * Come out of intra cluster coherency * --------------------------------------------- */ mov x30, x18 b cortex_a53_disable_smp func cortex_a53_cluster_pwr_dwn mov x18, x30 /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache /* --------------------------------------------- * Disable the optional ACP. * --------------------------------------------- */ bl plat_disable_acp /* --------------------------------------------- * Flush L1 and L2 caches to PoC. * --------------------------------------------- */ mov x0, #DCCISW bl dcsw_op_all /* --------------------------------------------- * Come out of intra cluster coherency * --------------------------------------------- */ mov x30, x18 b cortex_a53_disable_smp /* --------------------------------------------- * This function provides cortex_a53 specific * register information for crash reporting. * It needs to return with x6 pointing to * a list of register names in ascii and * x8 - x15 having values of registers to be * reported. * --------------------------------------------- */ .section .rodata.cortex_a53_regs, "aS" cortex_a53_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" func cortex_a53_cpu_reg_dump adr x6, cortex_a53_regs mrs x8, CPUECTLR_EL1 ret declare_cpu_ops cortex_a53, CORTEX_A53_MIDR arm-trusted-firmware-1.0-aw-6/lib/cpus/aarch64/cortex_a57.S000066400000000000000000000141641322600646200232660ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include /* --------------------------------------------- * Disable L1 data cache and unified L2 cache * --------------------------------------------- */ func cortex_a57_disable_dcache mrs x1, sctlr_el3 bic x1, x1, #SCTLR_C_BIT msr sctlr_el3, x1 isb ret /* --------------------------------------------- * Disable all types of L2 prefetches. * --------------------------------------------- */ func cortex_a57_disable_l2_prefetch mrs x0, CPUECTLR_EL1 orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK bic x0, x0, x1 msr CPUECTLR_EL1, x0 isb dsb sy ret /* --------------------------------------------- * Disable intra-cluster coherency * --------------------------------------------- */ func cortex_a57_disable_smp mrs x0, CPUECTLR_EL1 bic x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 ret /* --------------------------------------------- * Disable debug interfaces * --------------------------------------------- */ func cortex_a57_disable_ext_debug mov x0, #1 msr osdlr_el1, x0 isb dsb sy ret func cortex_a57_reset_func #if ERRATA_A57_806969 || ERRATA_A57_813420 /* --------------------------------------------- * Ensure that the following errata is only * applied on r0p0 parts. * --------------------------------------------- */ #if ASM_ASSERTION mrs x0, midr_el1 ubfx x1, x0, #MIDR_VAR_SHIFT, #4 ubfx x2, x0, #MIDR_REV_SHIFT, #4 orr x0, x1, x2 cmp x0, #0 ASM_ASSERT(eq) #endif mov x1, xzr #if ERRATA_A57_806969 orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA #endif #if ERRATA_A57_813420 orr x1, x1, #CPUACTLR_DCC_AS_DCCI #endif mrs x0, CPUACTLR_EL1 orr x0, x0, x1 msr CPUACTLR_EL1, x0 #endif /* --------------------------------------------- * As a bare minimum enable the SMP bit. * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 isb ret func cortex_a57_core_pwr_dwn mov x18, x30 /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a57_disable_dcache /* --------------------------------------------- * Disable the L2 prefetches. * --------------------------------------------- */ bl cortex_a57_disable_l2_prefetch /* --------------------------------------------- * Flush L1 cache to PoU. * --------------------------------------------- */ mov x0, #DCCISW bl dcsw_op_louis /* --------------------------------------------- * Come out of intra cluster coherency * --------------------------------------------- */ bl cortex_a57_disable_smp /* --------------------------------------------- * Force the debug interfaces to be quiescent * --------------------------------------------- */ mov x30, x18 b cortex_a57_disable_ext_debug func cortex_a57_cluster_pwr_dwn mov x18, x30 /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a57_disable_dcache /* --------------------------------------------- * Disable the L2 prefetches. * --------------------------------------------- */ bl cortex_a57_disable_l2_prefetch /* --------------------------------------------- * Disable the optional ACP. * --------------------------------------------- */ bl plat_disable_acp /* --------------------------------------------- * Flush L1 and L2 caches to PoC. * --------------------------------------------- */ mov x0, #DCCISW bl dcsw_op_all /* --------------------------------------------- * Come out of intra cluster coherency * --------------------------------------------- */ bl cortex_a57_disable_smp /* --------------------------------------------- * Force the debug interfaces to be quiescent * --------------------------------------------- */ mov x30, x18 b cortex_a57_disable_ext_debug /* --------------------------------------------- * This function provides cortex_a57 specific * register information for crash reporting. * It needs to return with x6 pointing to * a list of register names in ascii and * x8 - x15 having values of registers to be * reported. * --------------------------------------------- */ .section .rodata.cortex_a57_regs, "aS" cortex_a57_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" func cortex_a57_cpu_reg_dump adr x6, cortex_a57_regs mrs x8, CPUECTLR_EL1 ret declare_cpu_ops cortex_a57, CORTEX_A57_MIDR arm-trusted-firmware-1.0-aw-6/lib/cpus/aarch64/cpu_helpers.S000066400000000000000000000124401322600646200236120ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #if IMAGE_BL31 #include #endif /* Reset fn is needed in BL at reset vector */ #if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) /* * The reset handler common to all platforms. After a matching * cpu_ops structure entry is found, the correponding reset_handler * in the cpu_ops is invoked. */ .globl reset_handler func reset_handler mov x10, x30 bl plat_reset_handler /* Get the matching cpu_ops pointer */ bl get_cpu_ops_ptr #if ASM_ASSERTION cmp x0, #0 ASM_ASSERT(ne) #endif /* Get the cpu_ops reset handler */ ldr x2, [x0, #CPU_RESET_FUNC] cbz x2, 1f blr x2 1: ret x10 #endif /* IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31) */ #if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ /* * The prepare core power down function for all platforms. After * the cpu_ops pointer is retrieved from cpu_data, the corresponding * pwr_dwn_core in the cpu_ops is invoked. */ .globl prepare_core_pwr_dwn func prepare_core_pwr_dwn mrs x1, tpidr_el3 ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] #if ASM_ASSERTION cmp x0, #0 ASM_ASSERT(ne) #endif /* Get the cpu_ops core_pwr_dwn handler */ ldr x1, [x0, #CPU_PWR_DWN_CORE] br x1 /* * The prepare cluster power down function for all platforms. After * the cpu_ops pointer is retrieved from cpu_data, the corresponding * pwr_dwn_cluster in the cpu_ops is invoked. */ .globl prepare_cluster_pwr_dwn func prepare_cluster_pwr_dwn mrs x1, tpidr_el3 ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] #if ASM_ASSERTION cmp x0, #0 ASM_ASSERT(ne) #endif /* Get the cpu_ops cluster_pwr_dwn handler */ ldr x1, [x0, #CPU_PWR_DWN_CLUSTER] br x1 /* * Initializes the cpu_ops_ptr if not already initialized * in cpu_data. This can be called without a runtime stack, but may * only be called after the MMU is enabled. * clobbers: x0 - x6, x10 */ .globl init_cpu_ops func init_cpu_ops mrs x6, tpidr_el3 ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR] cbnz x0, 1f mov x10, x30 bl get_cpu_ops_ptr #if ASM_ASSERTION cmp x0, #0 ASM_ASSERT(ne) #endif str x0, [x6, #CPU_DATA_CPU_OPS_PTR]! mov x30, x10 1: ret #endif /* IMAGE_BL31 */ #if IMAGE_BL31 && CRASH_REPORTING /* * The cpu specific registers which need to be reported in a crash * are reported via cpu_ops cpu_reg_dump function. After a matching * cpu_ops structure entry is found, the correponding cpu_reg_dump * in the cpu_ops is invoked. */ .globl do_cpu_reg_dump func do_cpu_reg_dump mov x16, x30 /* Get the matching cpu_ops pointer */ bl get_cpu_ops_ptr cbz x0, 1f /* Get the cpu_ops cpu_reg_dump */ ldr x2, [x0, #CPU_REG_DUMP] cbz x2, 1f blr x2 1: mov x30, x16 ret #endif /* * The below function returns the cpu_ops structure matching the * midr of the core. It reads the MIDR_EL1 and finds the matching * entry in cpu_ops entries. Only the implementation and part number * are used to match the entries. * Return : * x0 - The matching cpu_ops pointer on Success * x0 - 0 on failure. * Clobbers : x0 - x5 */ .globl get_cpu_ops_ptr func get_cpu_ops_ptr /* Get the cpu_ops start and end locations */ adr x4, (__CPU_OPS_START__ + CPU_MIDR) adr x5, (__CPU_OPS_END__ + CPU_MIDR) /* Initialize the return parameter */ mov x0, #0 /* Read the MIDR_EL1 */ mrs x2, midr_el1 mov_imm x3, CPU_IMPL_PN_MASK /* Retain only the implementation and part number using mask */ and w2, w2, w3 1: /* Check if we have reached end of list */ cmp x4, x5 b.eq error_exit /* load the midr from the cpu_ops */ ldr x1, [x4], #CPU_OPS_SIZE and w1, w1, w3 /* Check if midr matches to midr of this core */ cmp w1, w2 b.ne 1b /* Subtract the increment and offset to get the cpu-ops pointer */ sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) error_exit: ret arm-trusted-firmware-1.0-aw-6/lib/cpus/cpu-errata.mk000066400000000000000000000041531322600646200223230ustar00rootroot00000000000000# # Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # CPU Errata Build flags. These should be enabled by the # platform if the errata needs to be applied. # Flag to apply errata 806969 during reset. This errata applies only to # revision r0p0 of the Cortex A57 cpu. ERRATA_A57_806969 ?=0 # Flag to apply errata 813420 during reset. This errata applies only to # revision r0p0 of the Cortex A57 cpu. ERRATA_A57_813420 ?=0 # Process ERRATA_A57_806969 flag $(eval $(call assert_boolean,ERRATA_A57_806969)) $(eval $(call add_define,ERRATA_A57_806969)) # Process ERRATA_A57_813420 flag $(eval $(call assert_boolean,ERRATA_A57_813420)) $(eval $(call add_define,ERRATA_A57_813420)) arm-trusted-firmware-1.0-aw-6/lib/locks/000077500000000000000000000000001322600646200200655ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/locks/bakery/000077500000000000000000000000001322600646200213425ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/locks/bakery/bakery_lock.c000066400000000000000000000146531322600646200240040ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include /* * Functions in this file implement Bakery Algorithm for mutual exclusion. * * ARM architecture offers a family of exclusive access instructions to * efficiently implement mutual exclusion with hardware support. However, as * well as depending on external hardware, the these instructions have defined * behavior only on certain memory types (cacheable and Normal memory in * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases * in trusted firmware are such that mutual exclusion implementation cannot * expect that accesses to the lock have the specific type required by the * architecture for these primitives to function (for example, not all * contenders may have address translation enabled). * * This implementation does not use mutual exclusion primitives. It expects * memory regions where the locks reside to be fully ordered and coherent * (either by disabling address translation, or by assigning proper attributes * when translation is enabled). * * Note that the ARM architecture guarantees single-copy atomicity for aligned * accesses regardless of status of address translation. */ #define assert_bakery_entry_valid(entry, bakery) do { \ assert(bakery); \ assert(entry < BAKERY_LOCK_MAX_CPUS); \ } while (0) /* Convert a ticket to priority */ #define PRIORITY(t, pos) (((t) << 8) | (pos)) /* Initialize Bakery Lock to reset ownership and all ticket values */ void bakery_lock_init(bakery_lock_t *bakery) { assert(bakery); /* All ticket values need to be 0 */ memset(bakery, 0, sizeof(*bakery)); bakery->owner = NO_OWNER; } /* Obtain a ticket for a given CPU */ static unsigned int bakery_get_ticket(bakery_lock_t *bakery, unsigned int me) { unsigned int my_ticket, their_ticket; unsigned int they; /* * Flag that we're busy getting our ticket. All CPUs are iterated in the * order of their ordinal position to decide the maximum ticket value * observed so far. Our priority is set to be greater than the maximum * observed priority * * Note that it's possible that more than one contender gets the same * ticket value. That's OK as the lock is acquired based on the priority * value, not the ticket value alone. */ my_ticket = 0; bakery->entering[me] = 1; for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { their_ticket = bakery->number[they]; if (their_ticket > my_ticket) my_ticket = their_ticket; } /* * Compute ticket; then signal to other contenders waiting for us to * finish calculating our ticket value that we're done */ ++my_ticket; bakery->number[me] = my_ticket; bakery->entering[me] = 0; dsb(); sev(); return my_ticket; } /* * Acquire bakery lock * * Contending CPUs need first obtain a non-zero ticket and then calculate * priority value. A contending CPU iterate over all other CPUs in the platform, * which may be contending for the same lock, in the order of their ordinal * position (CPU0, CPU1 and so on). A non-contending CPU will have its ticket * (and priority) value as 0. The contending CPU compares its priority with that * of others'. The CPU with the highest priority (lowest numerical value) * acquires the lock */ void bakery_lock_get(bakery_lock_t *bakery) { unsigned int they, me; unsigned int my_ticket, my_prio, their_ticket; me = platform_get_core_pos(read_mpidr_el1()); assert_bakery_entry_valid(me, bakery); /* Prevent recursive acquisition */ assert(bakery->owner != me); /* Get a ticket */ my_ticket = bakery_get_ticket(bakery, me); /* * Now that we got our ticket, compute our priority value, then compare * with that of others, and proceed to acquire the lock */ my_prio = PRIORITY(my_ticket, me); for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { if (me == they) continue; /* Wait for the contender to get their ticket */ while (bakery->entering[they]) wfe(); /* * If the other party is a contender, they'll have non-zero * (valid) ticket value. If they do, compare priorities */ their_ticket = bakery->number[they]; if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) { /* * They have higher priority (lower value). Wait for * their ticket value to change (either release the lock * to have it dropped to 0; or drop and probably content * again for the same lock to have an even higher value) */ do { wfe(); } while (their_ticket == bakery->number[they]); } } /* Lock acquired */ bakery->owner = me; } /* Release the lock and signal contenders */ void bakery_lock_release(bakery_lock_t *bakery) { unsigned int me = platform_get_core_pos(read_mpidr_el1()); assert_bakery_entry_valid(me, bakery); assert(bakery->owner == me); /* * Release lock by resetting ownership and ticket. Then signal other * waiting contenders */ bakery->owner = NO_OWNER; bakery->number[me] = 0; dsb(); sev(); } arm-trusted-firmware-1.0-aw-6/lib/locks/exclusive/000077500000000000000000000000001322600646200220745ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/locks/exclusive/spinlock.S000066400000000000000000000033621322600646200240460ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include .globl spin_lock .globl spin_unlock func spin_lock mov w2, #1 sevl l1: wfe l2: ldaxr w1, [x0] cbnz w1, l1 stxr w1, w2, [x0] cbnz w1, l2 ret func spin_unlock stlr wzr, [x0] ret arm-trusted-firmware-1.0-aw-6/lib/semihosting/000077500000000000000000000000001322600646200213035ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/semihosting/aarch64/000077500000000000000000000000001322600646200225335ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/semihosting/aarch64/semihosting_call.S000066400000000000000000000031661322600646200262110ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include .globl semihosting_call func semihosting_call hlt #0xf000 ret arm-trusted-firmware-1.0-aw-6/lib/semihosting/semihosting.c000066400000000000000000000136261322600646200240100ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #ifndef SEMIHOSTING_SUPPORTED #define SEMIHOSTING_SUPPORTED 1 #endif long semihosting_call(unsigned long operation, void *system_block_address); typedef struct { const char *file_name; unsigned long mode; size_t name_length; } smh_file_open_block_t; typedef struct { long handle; uintptr_t buffer; size_t length; } smh_file_read_write_block_t; typedef struct { long handle; ssize_t location; } smh_file_seek_block_t; typedef struct { char *command_line; size_t command_length; } smh_system_block_t; long semihosting_connection_supported(void) { return SEMIHOSTING_SUPPORTED; } long semihosting_file_open(const char *file_name, size_t mode) { smh_file_open_block_t open_block; open_block.file_name = file_name; open_block.mode = mode; open_block.name_length = strlen(file_name); return semihosting_call(SEMIHOSTING_SYS_OPEN, (void *) &open_block); } long semihosting_file_seek(long file_handle, ssize_t offset) { smh_file_seek_block_t seek_block; long result; seek_block.handle = file_handle; seek_block.location = offset; result = semihosting_call(SEMIHOSTING_SYS_SEEK, (void *) &seek_block); if (result) result = semihosting_call(SEMIHOSTING_SYS_ERRNO, 0); return result; } long semihosting_file_read(long file_handle, size_t *length, uintptr_t buffer) { smh_file_read_write_block_t read_block; long result = -EINVAL; if ((length == NULL) || (buffer == (uintptr_t)NULL)) return result; read_block.handle = file_handle; read_block.buffer = buffer; read_block.length = *length; result = semihosting_call(SEMIHOSTING_SYS_READ, (void *) &read_block); if (result == *length) { return -EINVAL; } else if (result < *length) { *length -= result; return 0; } else return result; } long semihosting_file_write(long file_handle, size_t *length, const uintptr_t buffer) { smh_file_read_write_block_t write_block; if ((length == NULL) || (buffer == (uintptr_t)NULL)) return -EINVAL; write_block.handle = file_handle; write_block.buffer = (uintptr_t)buffer; /* cast away const */ write_block.length = *length; *length = semihosting_call(SEMIHOSTING_SYS_WRITE, (void *) &write_block); return *length; } long semihosting_file_close(long file_handle) { return semihosting_call(SEMIHOSTING_SYS_CLOSE, (void *) &file_handle); } long semihosting_file_length(long file_handle) { return semihosting_call(SEMIHOSTING_SYS_FLEN, (void *) &file_handle); } char semihosting_read_char(void) { return semihosting_call(SEMIHOSTING_SYS_READC, NULL); } void semihosting_write_char(char character) { semihosting_call(SEMIHOSTING_SYS_WRITEC, (void *) &character); } void semihosting_write_string(char *string) { semihosting_call(SEMIHOSTING_SYS_WRITE0, (void *) string); } long semihosting_system(char *command_line) { smh_system_block_t system_block; system_block.command_line = command_line; system_block.command_length = strlen(command_line); return semihosting_call(SEMIHOSTING_SYS_SYSTEM, (void *) &system_block); } long semihosting_get_flen(const char *file_name) { long file_handle; size_t length; assert(semihosting_connection_supported()); file_handle = semihosting_file_open(file_name, FOPEN_MODE_RB); if (file_handle == -1) return file_handle; /* Find the length of the file */ length = semihosting_file_length(file_handle); return semihosting_file_close(file_handle) ? -1 : length; } long semihosting_download_file(const char *file_name, size_t buf_size, uintptr_t buf) { long ret = -EINVAL; size_t length; long file_handle; /* Null pointer check */ if (!buf) return ret; assert(semihosting_connection_supported()); file_handle = semihosting_file_open(file_name, FOPEN_MODE_RB); if (file_handle == -1) return ret; /* Find the actual length of the file */ length = semihosting_file_length(file_handle); if (length == -1) goto semihosting_fail; /* Signal error if we do not have enough space for the file */ if (length > buf_size) goto semihosting_fail; /* * A successful read will return 0 in which case we pass back * the actual number of bytes read. Else we pass a negative * value indicating an error. */ ret = semihosting_file_read(file_handle, &length, buf); if (ret) goto semihosting_fail; else ret = length; semihosting_fail: semihosting_file_close(file_handle); return ret; } arm-trusted-firmware-1.0-aw-6/lib/stdlib/000077500000000000000000000000001322600646200202335ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/lib/stdlib/abort.c000066400000000000000000000032441322600646200215110ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include /* * This is a basic implementation. This could be improved. */ void abort (void) { ERROR("ABORT\n"); panic(); } arm-trusted-firmware-1.0-aw-6/lib/stdlib/assert.c000066400000000000000000000034441322600646200217050ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include /* * This is a basic implementation. This could be improved. */ void __assert (const char *function, const char *file, unsigned int line, const char *assertion) { tf_printf("ASSERT: %s <%d> : %s\n", function, line, assertion); while(1); } arm-trusted-firmware-1.0-aw-6/lib/stdlib/mem.c000066400000000000000000000062621322600646200211630ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include /* size_t */ /* * Fill @count bytes of memory pointed to by @dst with @val */ void *memset(void *dst, int val, size_t count) { char *ptr = dst; while (count--) *ptr++ = val; return dst; } /* * Compare @len bytes of @s1 and @s2 */ int memcmp(const void *s1, const void *s2, size_t len) { const char *s = s1; const char *d = s2; char dc; char sc; while (len--) { sc = *s++; dc = *d++; if (sc - dc) return (sc - dc); } return 0; } /* * Copy @len bytes from @src to @dst */ void *memcpy(void *dst, const void *src, size_t len) { const char *s = src; char *d = dst; while (len--) *d++ = *s++; return dst; } /* * Move @len bytes from @src to @dst */ void *memmove(void *dst, const void *src, size_t len) { /* * The following test makes use of unsigned arithmetic overflow to * more efficiently test the condition !(src <= dst && dst < str+len). * It also avoids the situation where the more explicit test would give * incorrect results were the calculation str+len to overflow (though * that issue is probably moot as such usage is probably undefined * behaviour and a bug anyway. */ if ((size_t)dst - (size_t)src >= len) { /* destination not in source data, so can safely use memcpy */ return memcpy(dst, src, len); } else { /* copy backwards... */ const char *end = dst; const char *s = (const char *)src + len; char *d = (char *)dst + len; while (d != end) *--d = *--s; } return dst; } /* * Scan @len bytes of @src for value @c */ void *memchr(const void *src, int c, size_t len) { const char *s = src; while (len--) { if (*s == c) return (void *) s; s++; } return NULL; } arm-trusted-firmware-1.0-aw-6/lib/stdlib/printf.c000066400000000000000000000040451322600646200217040ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include /* Choose max of 128 chars for now. */ #define PRINT_BUFFER_SIZE 128 int printf(const char *fmt, ...) { va_list args; char buf[PRINT_BUFFER_SIZE]; int count; va_start(args, fmt); vsnprintf(buf, sizeof(buf) - 1, fmt, args); va_end(args); /* Use putchar directly as 'puts()' adds a newline. */ buf[PRINT_BUFFER_SIZE - 1] = '\0'; count = 0; while (buf[count]) { if (putchar(buf[count]) != EOF) { count++; } else { count = EOF; break; } } return count; } arm-trusted-firmware-1.0-aw-6/lib/stdlib/putchar.c000066400000000000000000000037321322600646200220520ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include /* Putchar() should either return the character printed or EOF in case of error. * Our current console_putc() function assumes success and returns the * character. Write all other printing functions in terms of putchar(), if * possible, so they all benefit when this is improved. */ int putchar(int c) { int res; if (console_putc((unsigned char)c) >= 0) res = c; else res = EOF; return res; } arm-trusted-firmware-1.0-aw-6/lib/stdlib/puts.c000066400000000000000000000035741322600646200214030ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include int puts(const char *s) { int count = 0; while(*s) { if (putchar(*s++) != EOF) { count++; } else { count = EOF; break; } } /* According to the puts(3) manpage, the function should write a * trailing newline. */ if ((count != EOF) && (putchar('\n') != EOF)) count++; else count = EOF; return count; } arm-trusted-firmware-1.0-aw-6/lib/stdlib/std.c000066400000000000000000000034461322600646200212000ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* Include the various implemented functions */ #include "abort.c" #include "assert.c" #include "mem.c" #include "printf.c" #include "putchar.c" #include "puts.c" #include "strchr.c" #include "strcmp.c" #include "strlen.c" #include "strncmp.c" #include "subr_prf.c" arm-trusted-firmware-1.0-aw-6/lib/stdlib/strchr.c000066400000000000000000000036121322600646200217060ustar00rootroot00000000000000/*- * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Portions copyright (c) 2013-2014, ARM Limited and Contributors. * All rights reserved. */ #include #include #include char * strchr(const char *p, int ch) { char c; c = ch; for (;; ++p) { if (*p == c) return ((char *)p); if (*p == '\0') return (NULL); } /* NOTREACHED */ } arm-trusted-firmware-1.0-aw-6/lib/stdlib/strcmp.c000066400000000000000000000037431322600646200217160ustar00rootroot00000000000000/*- * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * This code is derived from software contributed to Berkeley by * Chris Torek. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Portions copyright (c) 2014, ARM Limited and Contributors. * All rights reserved. */ #include #include /* * Compare strings. */ int strcmp(const char *s1, const char *s2) { while (*s1 == *s2++) if (*s1++ == '\0') return 0; return *(const unsigned char *)s1 - *(const unsigned char *)(s2 - 1); } arm-trusted-firmware-1.0-aw-6/lib/stdlib/strlen.c000066400000000000000000000034371322600646200217150ustar00rootroot00000000000000/*- * Copyright (c) 1990, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Portions copyright (c) 2009-2014, ARM Limited and Contributors. All rights reserved. */ #include size_t strlen(str) const char *str; { register const char *s; for (s = str; *s; ++s); return(s - str); } arm-trusted-firmware-1.0-aw-6/lib/stdlib/strncmp.c000066400000000000000000000037011322600646200220660ustar00rootroot00000000000000/* * Copyright (c) 1989, 1993 * The Regents of the University of California. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Portions copyright (c) 2014, ARM Limited and Contributors. * All rights reserved. */ #include #include int strncmp(const char *s1, const char *s2, size_t n) { if (n == 0) return 0; do { if (*s1 != *s2++) return (*(const unsigned char *)s1 - *(const unsigned char *)(s2 - 1)); if (*s1++ == '\0') break; } while (--n != 0); return 0; } arm-trusted-firmware-1.0-aw-6/lib/stdlib/subr_prf.c000066400000000000000000000277361322600646200222400ustar00rootroot00000000000000/*- * Copyright (c) 1986, 1988, 1991, 1993 * The Regents of the University of California. All rights reserved. * (c) UNIX System Laboratories, Inc. * All or some portions of this file are derived from material licensed * to the University of California by American Telephone and Telegraph * Co. or Unix System Laboratories, Inc. and are reproduced herein with * the permission of UNIX System Laboratories, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 4. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)subr_prf.c 8.3 (Berkeley) 1/21/94 */ /* * Portions copyright (c) 2009-2014, ARM Limited and Contributors. * All rights reserved. */ #include #include #include #include #include #include typedef unsigned char u_char; typedef unsigned int u_int; typedef int64_t quad_t; typedef uint64_t u_quad_t; typedef unsigned long u_long; typedef unsigned short u_short; static inline int imax(int a, int b) { return (a > b ? a : b); } /* * Note that stdarg.h and the ANSI style va_start macro is used for both * ANSI and traditional C compilers. */ #define TOCONS 0x01 #define TOTTY 0x02 #define TOLOG 0x04 /* Max number conversion buffer length: a u_quad_t in base 2, plus NUL byte. */ #define MAXNBUF (sizeof(intmax_t) * 8 + 1) struct putchar_arg { int flags; int pri; struct tty *tty; char *p_bufr; size_t n_bufr; char *p_next; size_t remain; }; struct snprintf_arg { char *str; size_t remain; }; extern int log_open; static char *ksprintn(char *nbuf, uintmax_t num, int base, int *len, int upper); static void snprintf_func(int ch, void *arg); static int kvprintf(char const *fmt, void (*func)(int, void*), void *arg, int radix, va_list ap); int vsnprintf(char *str, size_t size, const char *format, va_list ap); static char const hex2ascii_data[] = "0123456789abcdefghijklmnopqrstuvwxyz"; #define hex2ascii(hex) (hex2ascii_data[hex]) /* * Scaled down version of sprintf(3). */ int sprintf(char *buf, const char *cfmt, ...) { int retval; va_list ap; va_start(ap, cfmt); retval = kvprintf(cfmt, NULL, (void *)buf, 10, ap); buf[retval] = '\0'; va_end(ap); return (retval); } /* * Scaled down version of vsprintf(3). */ int vsprintf(char *buf, const char *cfmt, va_list ap) { int retval; retval = kvprintf(cfmt, NULL, (void *)buf, 10, ap); buf[retval] = '\0'; return (retval); } /* * Scaled down version of snprintf(3). */ int snprintf(char *str, size_t size, const char *format, ...) { int retval; va_list ap; va_start(ap, format); retval = vsnprintf(str, size, format, ap); va_end(ap); return(retval); } /* * Scaled down version of vsnprintf(3). */ int vsnprintf(char *str, size_t size, const char *format, va_list ap) { struct snprintf_arg info; int retval; info.str = str; info.remain = size; retval = kvprintf(format, snprintf_func, &info, 10, ap); if (info.remain >= 1) *info.str++ = '\0'; return (retval); } static void snprintf_func(int ch, void *arg) { struct snprintf_arg *const info = arg; if (info->remain >= 2) { *info->str++ = ch; info->remain--; } } /* * Kernel version which takes radix argument vsnprintf(3). */ int vsnrprintf(char *str, size_t size, int radix, const char *format, va_list ap) { struct snprintf_arg info; int retval; info.str = str; info.remain = size; retval = kvprintf(format, snprintf_func, &info, radix, ap); if (info.remain >= 1) *info.str++ = '\0'; return (retval); } /* * Put a NUL-terminated ASCII number (base <= 36) in a buffer in reverse * order; return an optional length and a pointer to the last character * written in the buffer (i.e., the first character of the string). * The buffer pointed to by `nbuf' must have length >= MAXNBUF. */ static char * ksprintn(char *nbuf, uintmax_t num, int base, int *lenp, int upper) { char *p, c; p = nbuf; *p = '\0'; do { c = hex2ascii(num % base); *++p = upper ? toupper(c) : c; } while (num /= base); if (lenp) *lenp = p - nbuf; return (p); } /* * Scaled down version of printf(3). * * Two additional formats: * * The format %b is supported to decode error registers. * Its usage is: * * printf("reg=%b\n", regval, "*"); * * where is the output base expressed as a control character, e.g. * \10 gives octal; \20 gives hex. Each arg is a sequence of characters, * the first of which gives the bit number to be inspected (origin 1), and * the next characters (up to a control character, i.e. a character <= 32), * give the name of the register. Thus: * * kvprintf("reg=%b\n", 3, "\10\2BITTWO\1BITONE\n"); * * would produce output: * * reg=3 * * XXX: %D -- Hexdump, takes pointer and separator string: * ("%6D", ptr, ":") -> XX:XX:XX:XX:XX:XX * ("%*D", len, ptr, " " -> XX XX XX XX ... */ int kvprintf(char const *fmt, void (*func)(int, void*), void *arg, int radix, va_list ap) { #define PCHAR(c) {int cc=(c); if (func) (*func)(cc,arg); else *d++ = cc; retval++; } char nbuf[MAXNBUF]; char *d; const char *p, *percent, *q; u_char *up; int ch, n; uintmax_t num; int base, lflag, qflag, tmp, width, ladjust, sharpflag, neg, sign, dot; int cflag, hflag, jflag, tflag, zflag; int dwidth, upper; char padc; int stop = 0, retval = 0; num = 0; if (!func) d = (char *) arg; else d = NULL; if (fmt == NULL) fmt = "(fmt null)\n"; if (radix < 2 || radix > 36) radix = 10; for (;;) { padc = ' '; width = 0; while ((ch = (u_char)*fmt++) != '%' || stop) { if (ch == '\0') return (retval); PCHAR(ch); } percent = fmt - 1; qflag = 0; lflag = 0; ladjust = 0; sharpflag = 0; neg = 0; sign = 0; dot = 0; dwidth = 0; upper = 0; cflag = 0; hflag = 0; jflag = 0; tflag = 0; zflag = 0; reswitch: switch (ch = (u_char)*fmt++) { case '.': dot = 1; goto reswitch; case '#': sharpflag = 1; goto reswitch; case '+': sign = 1; goto reswitch; case '-': ladjust = 1; goto reswitch; case '%': PCHAR(ch); break; case '*': if (!dot) { width = va_arg(ap, int); if (width < 0) { ladjust = !ladjust; width = -width; } } else { dwidth = va_arg(ap, int); } goto reswitch; case '0': if (!dot) { padc = '0'; goto reswitch; } case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': for (n = 0;; ++fmt) { n = n * 10 + ch - '0'; ch = *fmt; if (ch < '0' || ch > '9') break; } if (dot) dwidth = n; else width = n; goto reswitch; case 'b': num = (u_int)va_arg(ap, int); p = va_arg(ap, char *); for (q = ksprintn(nbuf, num, *p++, NULL, 0); *q;) PCHAR(*q--); if (num == 0) break; for (tmp = 0; *p;) { n = *p++; if (num & (1 << (n - 1))) { PCHAR(tmp ? ',' : '<'); for (; (n = *p) > ' '; ++p) PCHAR(n); tmp = 1; } else for (; *p > ' '; ++p) continue; } if (tmp) PCHAR('>'); break; case 'c': PCHAR(va_arg(ap, int)); break; case 'D': up = va_arg(ap, u_char *); p = va_arg(ap, char *); if (!width) width = 16; while(width--) { PCHAR(hex2ascii(*up >> 4)); PCHAR(hex2ascii(*up & 0x0f)); up++; if (width) for (q=p;*q;q++) PCHAR(*q); } break; case 'd': case 'i': base = 10; sign = 1; goto handle_sign; case 'h': if (hflag) { hflag = 0; cflag = 1; } else hflag = 1; goto reswitch; case 'j': jflag = 1; goto reswitch; case 'l': if (lflag) { lflag = 0; qflag = 1; } else lflag = 1; goto reswitch; case 'n': if (jflag) *(va_arg(ap, intmax_t *)) = retval; else if (qflag) *(va_arg(ap, quad_t *)) = retval; else if (lflag) *(va_arg(ap, long *)) = retval; else if (zflag) *(va_arg(ap, size_t *)) = retval; else if (hflag) *(va_arg(ap, short *)) = retval; else if (cflag) *(va_arg(ap, char *)) = retval; else *(va_arg(ap, int *)) = retval; break; case 'o': base = 8; goto handle_nosign; case 'p': base = 16; sharpflag = (width == 0); sign = 0; num = (uintptr_t)va_arg(ap, void *); goto number; case 'q': qflag = 1; goto reswitch; case 'r': base = radix; if (sign) goto handle_sign; goto handle_nosign; case 's': p = va_arg(ap, char *); if (p == NULL) p = "(null)"; if (!dot) n = strlen (p); else for (n = 0; n < dwidth && p[n]; n++) continue; width -= n; if (!ladjust && width > 0) while (width--) PCHAR(padc); while (n--) PCHAR(*p++); if (ladjust && width > 0) while (width--) PCHAR(padc); break; case 't': tflag = 1; goto reswitch; case 'u': base = 10; goto handle_nosign; case 'X': upper = 1; case 'x': base = 16; goto handle_nosign; case 'y': base = 16; sign = 1; goto handle_sign; case 'z': zflag = 1; goto reswitch; handle_nosign: sign = 0; if (jflag) num = va_arg(ap, uintmax_t); else if (qflag) num = va_arg(ap, u_quad_t); else if (tflag) num = va_arg(ap, ptrdiff_t); else if (lflag) num = va_arg(ap, u_long); else if (zflag) num = va_arg(ap, size_t); else if (hflag) num = (u_short)va_arg(ap, int); else if (cflag) num = (u_char)va_arg(ap, int); else num = va_arg(ap, u_int); goto number; handle_sign: if (jflag) num = va_arg(ap, intmax_t); else if (qflag) num = va_arg(ap, quad_t); else if (tflag) num = va_arg(ap, ptrdiff_t); else if (lflag) num = va_arg(ap, long); else if (zflag) num = va_arg(ap, ssize_t); else if (hflag) num = (short)va_arg(ap, int); else if (cflag) num = (char)va_arg(ap, int); else num = va_arg(ap, int); number: if (sign && (intmax_t)num < 0) { neg = 1; num = -(intmax_t)num; } p = ksprintn(nbuf, num, base, &n, upper); tmp = 0; if (sharpflag && num != 0) { if (base == 8) tmp++; else if (base == 16) tmp += 2; } if (neg) tmp++; if (!ladjust && padc == '0') dwidth = width - tmp; width -= tmp + imax(dwidth, n); dwidth -= n; if (!ladjust) while (width-- > 0) PCHAR(' '); if (neg) PCHAR('-'); if (sharpflag && num != 0) { if (base == 8) { PCHAR('0'); } else if (base == 16) { PCHAR('0'); PCHAR('x'); } } while (dwidth-- > 0) PCHAR('0'); while (*p) PCHAR(*p--); if (ladjust) while (width-- > 0) PCHAR(' '); break; default: while (percent < fmt) PCHAR(*percent++); /* * Since we ignore an formatting argument it is no * longer safe to obey the remaining formatting * arguments as the arguments will no longer match * the format specs. */ stop = 1; break; } } #undef PCHAR } arm-trusted-firmware-1.0-aw-6/license.md000066400000000000000000000027271322600646200201600ustar00rootroot00000000000000Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. arm-trusted-firmware-1.0-aw-6/plat/000077500000000000000000000000001322600646200171445ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/common/000077500000000000000000000000001322600646200204345ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/common/aarch64/000077500000000000000000000000001322600646200216645ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/common/aarch64/plat_common.c000066400000000000000000000037241322600646200243460ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include /* * The following 2 platform setup functions are weakly defined. They * provide typical implementations that may be re-used by multiple * platforms but may also be overridden by a platform if required. */ #pragma weak bl31_plat_enable_mmu #pragma weak bl32_plat_enable_mmu void bl31_plat_enable_mmu(uint32_t flags) { enable_mmu_el3(flags); } void bl32_plat_enable_mmu(uint32_t flags) { enable_mmu_el1(flags); } arm-trusted-firmware-1.0-aw-6/plat/common/aarch64/platform_helpers.S000066400000000000000000000071121322600646200253570ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include .weak platform_get_core_pos .weak platform_check_mpidr .weak plat_report_exception .weak plat_crash_console_init .weak plat_crash_console_putc .weak plat_reset_handler .weak plat_disable_acp /* ----------------------------------------------------- * int platform_get_core_pos(int mpidr); * With this function: CorePos = (ClusterId * 4) + * CoreId * ----------------------------------------------------- */ func platform_get_core_pos and x1, x0, #MPIDR_CPU_MASK and x0, x0, #MPIDR_CLUSTER_MASK add x0, x1, x0, LSR #6 ret /* ----------------------------------------------------- * Placeholder function which should be redefined by * each platform. * ----------------------------------------------------- */ func platform_check_mpidr mov x0, xzr ret /* ----------------------------------------------------- * Placeholder function which should be redefined by * each platform. * ----------------------------------------------------- */ func plat_report_exception ret /* ----------------------------------------------------- * Placeholder function which should be redefined by * each platform. * ----------------------------------------------------- */ func plat_crash_console_init mov x0, #0 ret /* ----------------------------------------------------- * Placeholder function which should be redefined by * each platform. * ----------------------------------------------------- */ func plat_crash_console_putc ret /* ----------------------------------------------------- * Placeholder function which should be redefined by * each platform. This function should preserve x10. * ----------------------------------------------------- */ func plat_reset_handler ret /* ----------------------------------------------------- * Placeholder function which should be redefined by * each platform. This function is allowed to use * registers x0 - x17. * ----------------------------------------------------- */ func plat_disable_acp ret arm-trusted-firmware-1.0-aw-6/plat/common/aarch64/platform_mp_stack.S000066400000000000000000000053531322600646200255230ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include .local platform_normal_stacks .weak platform_set_stack .weak platform_get_stack /* ----------------------------------------------------- * unsigned long platform_get_stack (unsigned long mpidr) * * For a given CPU, this function returns the stack * pointer for a stack allocated in device memory. * ----------------------------------------------------- */ func platform_get_stack mov x10, x30 // lr get_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE ret x10 /* ----------------------------------------------------- * void platform_set_stack (unsigned long mpidr) * * For a given CPU, this function sets the stack pointer * to a stack allocated in normal memory. * ----------------------------------------------------- */ func platform_set_stack mov x9, x30 // lr bl platform_get_stack mov sp, x0 ret x9 /* ----------------------------------------------------- * Per-cpu stacks in normal memory. Each cpu gets a * stack of PLATFORM_STACK_SIZE bytes. * ----------------------------------------------------- */ declare_stack platform_normal_stacks, tzfw_normal_stacks, \ PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT arm-trusted-firmware-1.0-aw-6/plat/common/aarch64/platform_up_stack.S000066400000000000000000000054711322600646200255340ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include .local platform_normal_stacks .globl platform_set_stack .globl platform_get_stack /* ----------------------------------------------------- * unsigned long platform_get_stack (unsigned long) * * For cold-boot BL images, only the primary CPU needs a * stack. This function returns the stack pointer for a * stack allocated in device memory. * ----------------------------------------------------- */ func platform_get_stack get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE ret /* ----------------------------------------------------- * void platform_set_stack (unsigned long) * * For cold-boot BL images, only the primary CPU needs a * stack. This function sets the stack pointer to a stack * allocated in normal memory. * ----------------------------------------------------- */ func platform_set_stack get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE mov sp, x0 ret /* ----------------------------------------------------- * Single cpu stack in normal memory. * Used for C code during boot, PLATFORM_STACK_SIZE bytes * are allocated * ----------------------------------------------------- */ declare_stack platform_normal_stacks, tzfw_normal_stacks, \ PLATFORM_STACK_SIZE, 1 arm-trusted-firmware-1.0-aw-6/plat/common/plat_gic.c000066400000000000000000000051331322600646200223640ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include /* * The following platform GIC functions are weakly defined. They * provide typical implementations that may be re-used by multiple * platforms but may also be overridden by a platform if required. */ #pragma weak plat_ic_get_pending_interrupt_id #pragma weak plat_ic_get_pending_interrupt_type #pragma weak plat_ic_acknowledge_interrupt #pragma weak plat_ic_get_interrupt_type #pragma weak plat_ic_end_of_interrupt #pragma weak plat_interrupt_type_to_line uint32_t plat_ic_get_pending_interrupt_id(void) { return arm_gic_get_pending_interrupt_id(); } uint32_t plat_ic_get_pending_interrupt_type(void) { return arm_gic_get_pending_interrupt_type(); } uint32_t plat_ic_acknowledge_interrupt(void) { return arm_gic_acknowledge_interrupt(); } uint32_t plat_ic_get_interrupt_type(uint32_t id) { return arm_gic_get_interrupt_type(id); } void plat_ic_end_of_interrupt(uint32_t id) { arm_gic_end_of_interrupt(id); } uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) { return arm_gic_interrupt_type_to_line(type, security_state); } arm-trusted-firmware-1.0-aw-6/plat/fvp/000077500000000000000000000000001322600646200177375ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/fvp/aarch64/000077500000000000000000000000001322600646200211675ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/fvp/aarch64/fvp_common.c000066400000000000000000000225771322600646200235130ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include "../fvp_def.h" /******************************************************************************* * plat_config holds the characteristics of the differences between the three * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold * boot at each boot stage by the primary before enabling the MMU (to allow cci * configuration) & used thereafter. Each BL will have its own copy to allow * independent operation. ******************************************************************************/ plat_config_t plat_config; /* * Table of regions to map using the MMU. * This doesn't include TZRAM as the 'mem_layout' argument passed to * configure_mmu_elx() will give the available subset of that, */ const mmap_region_t fvp_mmap[] = { { FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE }, { FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE }, { FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE, MT_MEMORY | MT_RO | MT_SECURE }, { FLASH1_BASE, FLASH1_BASE, FLASH1_SIZE, MT_MEMORY | MT_RO | MT_SECURE }, { VRAM_BASE, VRAM_BASE, VRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE }, { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, /* 2nd GB as device for now...*/ { 0x40000000, 0x40000000, 0x40000000, MT_DEVICE | MT_RW | MT_SECURE }, { DRAM1_BASE, DRAM1_BASE, DRAM1_SIZE, MT_MEMORY | MT_RW | MT_NS }, {0} }; /* Array of secure interrupts to be configured by the gic driver */ const unsigned int irq_sec_array[] = { IRQ_TZ_WDOG, IRQ_SEC_PHY_TIMER, IRQ_SEC_SGI_0, IRQ_SEC_SGI_1, IRQ_SEC_SGI_2, IRQ_SEC_SGI_3, IRQ_SEC_SGI_4, IRQ_SEC_SGI_5, IRQ_SEC_SGI_6, IRQ_SEC_SGI_7 }; const unsigned int num_sec_irqs = sizeof(irq_sec_array) / sizeof(irq_sec_array[0]); /******************************************************************************* * Macro generating the code for the function setting up the pagetables as per * the platform memory map & initialize the mmu, for the given exception level ******************************************************************************/ #define DEFINE_CONFIGURE_MMU_EL(_el) \ void fvp_configure_mmu_el##_el(unsigned long total_base, \ unsigned long total_size, \ unsigned long ro_start, \ unsigned long ro_limit, \ unsigned long coh_start, \ unsigned long coh_limit) \ { \ mmap_add_region(total_base, total_base, \ total_size, \ MT_MEMORY | MT_RW | MT_SECURE); \ mmap_add_region(ro_start, ro_start, \ ro_limit - ro_start, \ MT_MEMORY | MT_RO | MT_SECURE); \ mmap_add_region(coh_start, coh_start, \ coh_limit - coh_start, \ MT_DEVICE | MT_RW | MT_SECURE); \ mmap_add(fvp_mmap); \ init_xlat_tables(); \ \ enable_mmu_el##_el(0); \ } /* Define EL1 and EL3 variants of the function initialising the MMU */ DEFINE_CONFIGURE_MMU_EL(1) DEFINE_CONFIGURE_MMU_EL(3) /******************************************************************************* * A single boot loader stack is expected to work on both the Foundation FVP * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The * SYS_ID register provides a mechanism for detecting the differences between * these platforms. This information is stored in a per-BL array to allow the * code to take the correct path.Per BL platform configuration. ******************************************************************************/ int fvp_config_setup(void) { unsigned int rev, hbi, bld, arch, sys_id; sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID); rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK; hbi = (sys_id >> SYS_ID_HBI_SHIFT) & SYS_ID_HBI_MASK; bld = (sys_id >> SYS_ID_BLD_SHIFT) & SYS_ID_BLD_MASK; arch = (sys_id >> SYS_ID_ARCH_SHIFT) & SYS_ID_ARCH_MASK; if (arch != ARCH_MODEL) { ERROR("This firmware is for FVP models\n"); panic(); } /* * The build field in the SYS_ID tells which variant of the GIC * memory is implemented by the model. */ switch (bld) { case BLD_GIC_VE_MMAP: plat_config.gicd_base = VE_GICD_BASE; plat_config.gicc_base = VE_GICC_BASE; plat_config.gich_base = VE_GICH_BASE; plat_config.gicv_base = VE_GICV_BASE; break; case BLD_GIC_A53A57_MMAP: plat_config.gicd_base = BASE_GICD_BASE; plat_config.gicc_base = BASE_GICC_BASE; plat_config.gich_base = BASE_GICH_BASE; plat_config.gicv_base = BASE_GICV_BASE; break; default: ERROR("Unsupported board build %x\n", bld); panic(); } /* * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 * for the Foundation FVP. */ switch (hbi) { case HBI_FOUNDATION: plat_config.max_aff0 = 4; plat_config.max_aff1 = 1; plat_config.flags = 0; /* * Check for supported revisions of Foundation FVP * Allow future revisions to run but emit warning diagnostic */ switch (rev) { case REV_FOUNDATION_V2_0: case REV_FOUNDATION_V2_1: break; default: WARN("Unrecognized Foundation FVP revision %x\n", rev); break; } break; case HBI_FVP_BASE: plat_config.max_aff0 = 4; plat_config.max_aff1 = 2; plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI | CONFIG_HAS_TZC; /* * Check for supported revisions * Allow future revisions to run but emit warning diagnostic */ switch (rev) { case REV_FVP_BASE_V0: break; default: WARN("Unrecognized Base FVP revision %x\n", rev); break; } break; default: ERROR("Unsupported board HBI number 0x%x\n", hbi); panic(); } return 0; } unsigned long plat_get_ns_image_entrypoint(void) { return NS_IMAGE_OFFSET; } uint64_t plat_get_syscnt_freq(void) { uint64_t counter_base_frequency; /* Read the frequency from Frequency modes table */ counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); /* The first entry of the frequency modes table must not be 0 */ if (counter_base_frequency == 0) panic(); return counter_base_frequency; } void fvp_cci_init(void) { /* * Initialize CCI-400 driver */ if (plat_config.flags & CONFIG_HAS_CCI) cci_init(CCI400_BASE, CCI400_SL_IFACE3_CLUSTER_IX, CCI400_SL_IFACE4_CLUSTER_IX); } void fvp_cci_enable(void) { /* * Enable CCI-400 coherency for this cluster. No need * for locks as no other cpu is active at the * moment */ if (plat_config.flags & CONFIG_HAS_CCI) cci_enable_cluster_coherency(read_mpidr()); } void fvp_gic_init(void) { arm_gic_init(plat_config.gicc_base, plat_config.gicd_base, BASE_GICR_BASE, irq_sec_array, num_sec_irqs); } /******************************************************************************* * Gets SPSR for BL32 entry ******************************************************************************/ uint32_t fvp_get_spsr_for_bl32_entry(void) { /* * The Secure Payload Dispatcher service is responsible for * setting the SPSR prior to entry into the BL32 image. */ return 0; } /******************************************************************************* * Gets SPSR for BL33 entry ******************************************************************************/ uint32_t fvp_get_spsr_for_bl33_entry(void) { unsigned long el_status; unsigned int mode; uint32_t spsr; /* Figure out what mode we enter the non-secure world in */ el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; el_status &= ID_AA64PFR0_ELX_MASK; if (el_status) mode = MODE_EL2; else mode = MODE_EL1; /* * TODO: Consider the possibility of specifying the SPSR in * the FIP ToC and allowing the platform to have a say as * well. */ spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); return spsr; } arm-trusted-firmware-1.0-aw-6/plat/fvp/aarch64/fvp_helpers.S000066400000000000000000000165631322600646200236430ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include "../drivers/pwrc/fvp_pwrc.h" .globl platform_get_entrypoint .globl plat_secondary_cold_boot_setup .globl platform_mem_init .globl plat_report_exception .globl platform_is_primary_cpu .globl plat_crash_console_init .globl plat_crash_console_putc .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res ldr \x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID ldr \w_tmp, [\x_tmp] ubfx \w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH cmp \w_tmp, #BLD_GIC_VE_MMAP csel \res, \param1, \param2, eq .endm /* ----------------------------------------------------- * void plat_secondary_cold_boot_setup (void); * * This function performs any platform specific actions * needed for a secondary cpu after a cold reset e.g * mark the cpu's presence, mechanism to place it in a * holding pen etc. * TODO: Should we read the PSYS register to make sure * that the request has gone through. * ----------------------------------------------------- */ func plat_secondary_cold_boot_setup /* --------------------------------------------- * Power down this cpu. * TODO: Do we need to worry about powering the * cluster down as well here. That will need * locks which we won't have unless an elf- * loader zeroes out the zi section. * --------------------------------------------- */ mrs x0, mpidr_el1 ldr x1, =PWRC_BASE str w0, [x1, #PPOFFR_OFF] /* --------------------------------------------- * Deactivate the gic cpu interface as well * --------------------------------------------- */ ldr x0, =VE_GICC_BASE ldr x1, =BASE_GICC_BASE fvp_choose_gicmmap x0, x1, x2, w2, x1 mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) str w0, [x1, #GICC_CTLR] /* --------------------------------------------- * There is no sane reason to come out of this * wfi so panic if we do. This cpu will be pow- * ered on and reset by the cpu_on pm api * --------------------------------------------- */ dsb sy wfi cb_panic: b cb_panic /* ----------------------------------------------------- * void platform_get_entrypoint (unsigned int mpid); * * Main job of this routine is to distinguish between * a cold and warm boot. * On a cold boot the secondaries first wait for the * platform to be initialized after which they are * hotplugged in. The primary proceeds to perform the * platform initialization. * On a warm boot, each cpu jumps to the address in its * mailbox. * * TODO: Not a good idea to save lr in a temp reg * TODO: PSYSR is a common register and should be * accessed using locks. Since its not possible * to use locks immediately after a cold reset * we are relying on the fact that after a cold * reset all cpus will read the same WK field * ----------------------------------------------------- */ func platform_get_entrypoint mov x9, x30 // lr mov x2, x0 ldr x1, =PWRC_BASE str w2, [x1, #PSYSR_OFF] ldr w2, [x1, #PSYSR_OFF] ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_MASK cmp w2, #WKUP_PPONR beq warm_reset cmp w2, #WKUP_GICREQ beq warm_reset mov x0, #0 b exit warm_reset: /* --------------------------------------------- * A per-cpu mailbox is maintained in the tru- * sted DRAM. Its flushed out of the caches * after every update using normal memory so * its safe to read it here with SO attributes * --------------------------------------------- */ ldr x10, =MBOX_BASE bl platform_get_core_pos lsl x0, x0, #CACHE_WRITEBACK_SHIFT ldr x0, [x10, x0] cbz x0, _panic exit: ret x9 _panic: b _panic /* ----------------------------------------------------- * void platform_mem_init (void); * * Zero out the mailbox registers in the shared memory. * The mmu is turned off right now and only the primary can * ever execute this code. Secondaries will read the * mailboxes using SO accesses. In short, BL31 will * update the mailboxes after mapping the tzdram as * normal memory. It will flush its copy after update. * BL1 will always read the mailboxes with the MMU off * ----------------------------------------------------- */ func platform_mem_init ldr x0, =MBOX_BASE mov w1, #PLATFORM_CORE_COUNT loop: str xzr, [x0], #CACHE_WRITEBACK_GRANULE subs w1, w1, #1 b.gt loop ret /* --------------------------------------------- * void plat_report_exception(unsigned int type) * Function to report an unhandled exception * with platform-specific means. * On FVP platform, it updates the LEDs * to indicate where we are * --------------------------------------------- */ func plat_report_exception mrs x1, CurrentEl lsr x1, x1, #MODE_EL_SHIFT lsl x1, x1, #SYS_LED_EL_SHIFT lsl x0, x0, #SYS_LED_EC_SHIFT mov x2, #(SECURE << SYS_LED_SS_SHIFT) orr x0, x0, x2 orr x0, x0, x1 mov x1, #VE_SYSREGS_BASE add x1, x1, #V2M_SYS_LED str w0, [x1] ret func platform_is_primary_cpu and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) cmp x0, #FVP_PRIMARY_CPU cset x0, eq ret /* Define a crash console for the plaform */ #define FVP_CRASH_CONSOLE_BASE PL011_UART0_BASE /* --------------------------------------------- * int plat_crash_console_init(void) * Function to initialize the crash console * without a C Runtime to print crash report. * Clobber list : x0, x1, x2 * --------------------------------------------- */ func plat_crash_console_init mov_imm x0, FVP_CRASH_CONSOLE_BASE mov_imm x1, PL011_UART0_CLK_IN_HZ mov_imm x2, PL011_BAUDRATE b console_core_init /* --------------------------------------------- * int plat_crash_console_putc(int c) * Function to print a character on the crash * console without a C Runtime. * Clobber list : x1, x2 * --------------------------------------------- */ func plat_crash_console_putc mov_imm x1, FVP_CRASH_CONSOLE_BASE b console_core_putc arm-trusted-firmware-1.0-aw-6/plat/fvp/bl1_fvp_setup.c000066400000000000000000000127201322600646200226560ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include "../../bl1/bl1_private.h" #include "fvp_def.h" #include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to * page-aligned addresses. */ #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /* Data structure which holds the extents of the trusted SRAM for BL1*/ static meminfo_t bl1_tzram_layout; meminfo_t *bl1_plat_sec_mem_layout(void) { return &bl1_tzram_layout; } /******************************************************************************* * Perform any BL1 specific platform actions. ******************************************************************************/ void bl1_early_platform_setup(void) { const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; /* Initialize the console to provide early debug support */ console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE; bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE; /* Calculate how much RAM BL1 is using and how much remains free */ bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE; bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE; reserve_mem(&bl1_tzram_layout.free_base, &bl1_tzram_layout.free_size, BL1_RAM_BASE, bl1_size); /* Initialize the platform config for future decision making */ fvp_config_setup(); } /******************************************************************************* * Function which will evaluate how much of the trusted ram has been gobbled * up by BL1 and return the base and size of whats available for loading BL2. * Its called after coherency and the MMU have been turned on. ******************************************************************************/ void bl1_platform_setup(void) { /* Initialise the IO layer and register platform IO devices */ fvp_io_setup(); } /******************************************************************************* * Perform the very early platform specific architecture setup here. At the * moment this only does basic initialization. Later architectural setup * (bl1_arch_setup()) does not do anything platform specific. ******************************************************************************/ void bl1_plat_arch_setup(void) { fvp_cci_init(); fvp_cci_enable(); fvp_configure_mmu_el3(bl1_tzram_layout.total_base, bl1_tzram_layout.total_size, BL1_RO_BASE, BL1_RO_LIMIT, BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT); } /******************************************************************************* * Before calling this function BL2 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL2 and set SPSR and security state. * On FVP we are only setting the security state, entrypoint ******************************************************************************/ void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, entry_point_info_t *bl2_ep) { SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } arm-trusted-firmware-1.0-aw-6/plat/fvp/bl2_fvp_setup.c000066400000000000000000000265351322600646200226700ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include "fvp_def.h" #include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __RO_END__; extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ #define BL2_RO_BASE (unsigned long)(&__RO_START__) #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to * page-aligned addresses. */ #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /* Data structure which holds the extents of the trusted SRAM for BL2 */ static meminfo_t bl2_tzram_layout __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), section("tzfw_coherent_mem"))); /* Assert that BL3-1 parameters fit in shared memory */ CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) < (FVP_SHARED_RAM_BASE + FVP_SHARED_RAM_SIZE), assert_bl31_params_do_not_fit_in_shared_memory); /******************************************************************************* * Reference to structures which holds the arguments which need to be passed * to BL31 ******************************************************************************/ static bl31_params_t *bl2_to_bl31_params; static entry_point_info_t *bl31_ep_info; meminfo_t *bl2_plat_sec_mem_layout(void) { return &bl2_tzram_layout; } /******************************************************************************* * This function assigns a pointer to the memory that the platform has kept * aside to pass platform specific and trusted firmware related information * to BL31. This memory is allocated by allocating memory to * bl2_to_bl31_params_mem_t structure which is a superset of all the * structure whose information is passed to BL31 * NOTE: This function should be called only once and should be done * before generating params to BL31 ******************************************************************************/ bl31_params_t *bl2_plat_get_bl31_params(void) { bl2_to_bl31_params_mem_t *bl31_params_mem; /* * Allocate the memory for all the arguments that needs to * be passed to BL31 */ bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t)); /* Assign memory for TF related information */ bl2_to_bl31_params = &bl31_params_mem->bl31_params; SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); /* Fill BL31 related information */ bl31_ep_info = &bl31_params_mem->bl31_ep_info; bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); /* Fill BL32 related information if it exists */ if (BL32_BASE) { bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem->bl32_ep_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, VERSION_1, 0); bl2_to_bl31_params->bl32_image_info = &bl31_params_mem->bl32_image_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); } /* Fill BL33 related information */ bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, PARAM_EP, VERSION_1, 0); bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); return bl2_to_bl31_params; } /******************************************************************************* * This function returns a pointer to the shared memory that the platform * has kept to point to entry point information of BL31 to BL2 ******************************************************************************/ struct entry_point_info *bl2_plat_get_bl31_ep_info(void) { #if DEBUG bl31_ep_info->args.arg1 = FVP_BL31_PLAT_PARAM_VAL; #endif return bl31_ep_info; } /******************************************************************************* * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 * in x0. This memory layout is sitting at the base of the free trusted SRAM. * Copy it to a safe loaction before its reclaimed by later BL2 functionality. ******************************************************************************/ void bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; /* Initialize the platform config for future decision making */ fvp_config_setup(); } /******************************************************************************* * Perform platform specific setup. For now just initialize the memory location * to use for passing arguments to BL31. ******************************************************************************/ void bl2_platform_setup(void) { /* * Do initial security configuration to allow DRAM/device access. On * Base FVP only DRAM security is programmable (via TrustZone), but * other platforms might have more programmable security devices * present. */ fvp_security_setup(); /* Initialise the IO layer and register platform IO devices */ fvp_io_setup(); } /* Flush the TF params and the TF plat params */ void bl2_plat_flush_bl31_params(void) { flush_dcache_range((unsigned long)PARAMS_BASE, \ sizeof(bl2_to_bl31_params_mem_t)); } /******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void bl2_plat_arch_setup(void) { fvp_configure_mmu_el1(bl2_tzram_layout.total_base, bl2_tzram_layout.total_size, BL2_RO_BASE, BL2_RO_LIMIT, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT); } /******************************************************************************* * Before calling this function BL31 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL31 and set SPSR and security state. * On FVP we are only setting the security state, entrypoint ******************************************************************************/ void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, entry_point_info_t *bl31_ep_info) { SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } /******************************************************************************* * Before calling this function BL32 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL32 and set SPSR and security state. * On FVP we are only setting the security state, entrypoint ******************************************************************************/ void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, entry_point_info_t *bl32_ep_info) { SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); bl32_ep_info->spsr = fvp_get_spsr_for_bl32_entry(); } /******************************************************************************* * Before calling this function BL33 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL33 and set SPSR and security state. * On FVP we are only setting the security state, entrypoint ******************************************************************************/ void bl2_plat_set_bl33_ep_info(image_info_t *image, entry_point_info_t *bl33_ep_info) { SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); bl33_ep_info->spsr = fvp_get_spsr_for_bl33_entry(); } /******************************************************************************* * Populate the extents of memory available for loading BL32 ******************************************************************************/ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) { /* * Populate the extents of memory available for loading BL32. */ bl32_meminfo->total_base = BL32_BASE; bl32_meminfo->free_base = BL32_BASE; bl32_meminfo->total_size = (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; bl32_meminfo->free_size = (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; } /******************************************************************************* * Populate the extents of memory available for loading BL33 ******************************************************************************/ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) { bl33_meminfo->total_base = DRAM_BASE; bl33_meminfo->total_size = DRAM_SIZE - DRAM1_SEC_SIZE; bl33_meminfo->free_base = DRAM_BASE; bl33_meminfo->free_size = DRAM_SIZE - DRAM1_SEC_SIZE; } arm-trusted-firmware-1.0-aw-6/plat/fvp/bl31_fvp_setup.c000066400000000000000000000220111322600646200227330ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include "drivers/pwrc/fvp_pwrc.h" #include "fvp_def.h" #include "fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __RO_END__; extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ #define BL31_RO_BASE (unsigned long)(&__RO_START__) #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols * refer to page-aligned addresses. */ #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) #if RESET_TO_BL31 static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; #else /******************************************************************************* * Reference to structure which holds the arguments that have been passed to * BL31 from BL2. ******************************************************************************/ static bl31_params_t *bl2_to_bl31_params; #endif /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for the * security state specified. BL33 corresponds to the non-secure image type * while BL32 corresponds to the secure image type. A NULL pointer is returned * if the image does not exist. ******************************************************************************/ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) { #if RESET_TO_BL31 assert(sec_state_is_valid(type)); if (type == NON_SECURE) return &bl33_image_ep_info; else return &bl32_image_ep_info; #else entry_point_info_t *next_image_info; assert(sec_state_is_valid(type)); next_image_info = (type == NON_SECURE) ? bl2_to_bl31_params->bl33_ep_info : bl2_to_bl31_params->bl32_ep_info; /* None of the images on this platform can have 0x0 as the entrypoint */ if (next_image_info->pc) return next_image_info; else return NULL; #endif } /******************************************************************************* * Perform any BL31 specific platform actions. Here is an opportunity to copy * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they * are lost (potentially). This needs to be done before the MMU is initialized * so that the memory layout can be used while creating page tables. On the FVP * we know that BL2 has populated the parameters in secure DRAM. So we just use * the reference passed in 'from_bl2' instead of copying. The 'data' parameter * is not used since all the information is contained in 'from_bl2'. Also, BL2 * has flushed this information to memory, so we are guaranteed to pick up good * data ******************************************************************************/ void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { /* Initialize the console to provide early debug support */ console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); /* Initialize the platform config for future decision making */ fvp_config_setup(); #if RESET_TO_BL31 /* There are no parameters from BL2 if BL31 is a reset vector */ assert(from_bl2 == NULL); assert(plat_params_from_bl2 == NULL); /* * Do initial security configuration to allow DRAM/device access. On * Base FVP only DRAM security is programmable (via TrustZone), but * other platforms might have more programmable security devices * present. */ fvp_security_setup(); /* Populate entry point information for BL3-2 and BL3-3 */ SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); bl32_image_ep_info.pc = BL32_BASE; bl32_image_ep_info.spsr = fvp_get_spsr_for_bl32_entry(); SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); /* * Tell BL31 where the non-trusted software image * is located and the entry state information */ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); bl33_image_ep_info.spsr = fvp_get_spsr_for_bl33_entry(); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); #else /* Check params passed from BL2 should not be NULL, * We are not checking plat_params_from_bl2 as NULL as we are not * using it on FVP */ assert(from_bl2 != NULL); assert(from_bl2->h.type == PARAM_BL31); assert(from_bl2->h.version >= VERSION_1); bl2_to_bl31_params = from_bl2; assert(((unsigned long)plat_params_from_bl2) == FVP_BL31_PLAT_PARAM_VAL); #endif } /******************************************************************************* * Initialize the gic, configure the CLCD and zero out variables needed by the * secondaries to boot up correctly. ******************************************************************************/ void bl31_platform_setup(void) { unsigned int reg_val; /* Initialize the gic cpu and distributor interfaces */ fvp_gic_init(); arm_gic_setup(); /* * TODO: Configure the CLCD before handing control to * linux. Need to see if a separate driver is needed * instead. */ mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0); mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL, (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16)); /* Enable and initialize the System level generic timer */ mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); /* Allow access to the System counter timer module */ reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val); mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1)); mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); /* Intialize the power controller */ fvp_pwrc_setup(); /* Topologies are best known to the platform. */ fvp_setup_topology(); } /******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { fvp_cci_init(); #if RESET_TO_BL31 fvp_cci_enable(); #endif fvp_configure_mmu_el3(BL31_RO_BASE, (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), BL31_RO_BASE, BL31_RO_LIMIT, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT); } arm-trusted-firmware-1.0-aw-6/plat/fvp/drivers/000077500000000000000000000000001322600646200214155ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/fvp/drivers/pwrc/000077500000000000000000000000001322600646200223705ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/fvp/drivers/pwrc/fvp_pwrc.c000066400000000000000000000063511322600646200243670ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include "../../fvp_def.h" #include "fvp_pwrc.h" /* * TODO: Someday there will be a generic power controller api. At the moment * each platform has its own pwrc so just exporting functions is fine. */ static bakery_lock_t pwrc_lock __attribute__ ((section("tzfw_coherent_mem"))); unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr) { return PSYSR_WK(fvp_pwrc_read_psysr(mpidr)); } unsigned int fvp_pwrc_read_psysr(unsigned long mpidr) { unsigned int rc; bakery_lock_get(&pwrc_lock); mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr); rc = mmio_read_32(PWRC_BASE + PSYSR_OFF); bakery_lock_release(&pwrc_lock); return rc; } void fvp_pwrc_write_pponr(unsigned long mpidr) { bakery_lock_get(&pwrc_lock); mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr); bakery_lock_release(&pwrc_lock); } void fvp_pwrc_write_ppoffr(unsigned long mpidr) { bakery_lock_get(&pwrc_lock); mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr); bakery_lock_release(&pwrc_lock); } void fvp_pwrc_set_wen(unsigned long mpidr) { bakery_lock_get(&pwrc_lock); mmio_write_32(PWRC_BASE + PWKUPR_OFF, (unsigned int) (PWKUPR_WEN | mpidr)); bakery_lock_release(&pwrc_lock); } void fvp_pwrc_clr_wen(unsigned long mpidr) { bakery_lock_get(&pwrc_lock); mmio_write_32(PWRC_BASE + PWKUPR_OFF, (unsigned int) mpidr); bakery_lock_release(&pwrc_lock); } void fvp_pwrc_write_pcoffr(unsigned long mpidr) { bakery_lock_get(&pwrc_lock); mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr); bakery_lock_release(&pwrc_lock); } /* Nothing else to do here apart from initializing the lock */ int fvp_pwrc_setup(void) { bakery_lock_init(&pwrc_lock); return 0; } arm-trusted-firmware-1.0-aw-6/plat/fvp/drivers/pwrc/fvp_pwrc.h000066400000000000000000000054301322600646200243710ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __FVP_PWRC_H__ #define __FVP_PWRC_H__ /* FVP Power controller register offset etc */ #define PPOFFR_OFF 0x0 #define PPONR_OFF 0x4 #define PCOFFR_OFF 0x8 #define PWKUPR_OFF 0xc #define PSYSR_OFF 0x10 #define PWKUPR_WEN (1ull << 31) #define PSYSR_AFF_L2 (1 << 31) #define PSYSR_AFF_L1 (1 << 30) #define PSYSR_AFF_L0 (1 << 29) #define PSYSR_WEN (1 << 28) #define PSYSR_PC (1 << 27) #define PSYSR_PP (1 << 26) #define PSYSR_WK_SHIFT 24 #define PSYSR_WK_MASK 0x3 #define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK #define WKUP_COLD 0x0 #define WKUP_RESET 0x1 #define WKUP_PPONR 0x2 #define WKUP_GICREQ 0x3 #define PSYSR_INVALID 0xffffffff #ifndef __ASSEMBLY__ /******************************************************************************* * Function & variable prototypes ******************************************************************************/ int fvp_pwrc_setup(void); void fvp_pwrc_write_pcoffr(unsigned long); void fvp_pwrc_write_ppoffr(unsigned long); void fvp_pwrc_write_pponr(unsigned long); void fvp_pwrc_set_wen(unsigned long); void fvp_pwrc_clr_wen(unsigned long); unsigned int fvp_pwrc_read_psysr(unsigned long); unsigned int fvp_pwrc_get_cpu_wkr(unsigned long); #endif /*__ASSEMBLY__*/ #endif /* __FVP_PWRC_H__ */ arm-trusted-firmware-1.0-aw-6/plat/fvp/fvp_def.h000066400000000000000000000215361322600646200215300ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __FVP_DEF_H__ #define __FVP_DEF_H__ /* Firmware Image Package */ #define FIP_IMAGE_NAME "fip.bin" #define FVP_PRIMARY_CPU 0x0 /* Memory location options for Shared data and TSP in FVP */ #define FVP_IN_TRUSTED_SRAM 0 #define FVP_IN_TRUSTED_DRAM 1 /******************************************************************************* * FVP memory map related constants ******************************************************************************/ #define FVP_TRUSTED_ROM_BASE 0x00000000 #define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ #define FVP_TRUSTED_SRAM_BASE 0x04000000 #define FVP_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ #define FVP_TRUSTED_DRAM_BASE 0x06000000 #define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ #define FLASH0_BASE 0x08000000 #define FLASH0_SIZE 0x04000000 #define FLASH1_BASE 0x0c000000 #define FLASH1_SIZE 0x04000000 #define PSRAM_BASE 0x14000000 #define PSRAM_SIZE 0x04000000 #define VRAM_BASE 0x18000000 #define VRAM_SIZE 0x02000000 /* Aggregate of all devices in the first GB */ #define DEVICE0_BASE 0x1a000000 #define DEVICE0_SIZE 0x12200000 #define DEVICE1_BASE 0x2f000000 #define DEVICE1_SIZE 0x200000 #define NSRAM_BASE 0x2e000000 #define NSRAM_SIZE 0x10000 /* 4KB shared memory */ #define FVP_SHARED_RAM_SIZE 0x1000 /* Location of shared memory */ #if (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_DRAM) /* Shared memory at the base of Trusted DRAM */ # define FVP_SHARED_RAM_BASE FVP_TRUSTED_DRAM_BASE # define FVP_TRUSTED_SRAM_LIMIT (FVP_TRUSTED_SRAM_BASE \ + FVP_TRUSTED_SRAM_SIZE) #elif (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_SRAM) # if (FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM) # error "Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported" # endif /* Shared memory at the top of the Trusted SRAM */ # define FVP_SHARED_RAM_BASE (FVP_TRUSTED_SRAM_BASE \ + FVP_TRUSTED_SRAM_SIZE \ - FVP_SHARED_RAM_SIZE) # define FVP_TRUSTED_SRAM_LIMIT FVP_SHARED_RAM_BASE #else # error "Unsupported FVP_SHARED_DATA_LOCATION_ID value" #endif #define DRAM1_BASE 0x80000000ull #define DRAM1_SIZE 0x80000000ull #define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1) #define DRAM1_SEC_SIZE 0x01000000ull #define DRAM_BASE DRAM1_BASE #define DRAM_SIZE DRAM1_SIZE #define DRAM2_BASE 0x880000000ull #define DRAM2_SIZE 0x780000000ull #define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1) #define PCIE_EXP_BASE 0x40000000 #define TZRNG_BASE 0x7fe60000 #define TZNVCTR_BASE 0x7fe70000 #define TZROOTKEY_BASE 0x7fe80000 /* Memory mapped Generic timer interfaces */ #define SYS_CNTCTL_BASE 0x2a430000 #define SYS_CNTREAD_BASE 0x2a800000 #define SYS_TIMCTL_BASE 0x2a810000 /* V2M motherboard system registers & offsets */ #define VE_SYSREGS_BASE 0x1c010000 #define V2M_SYS_ID 0x0 #define V2M_SYS_SWITCH 0x4 #define V2M_SYS_LED 0x8 #define V2M_SYS_CFGDATA 0xa0 #define V2M_SYS_CFGCTRL 0xa4 #define V2M_SYS_CFGSTATUS 0xa8 #define CFGCTRL_START (1 << 31) #define CFGCTRL_RW (1 << 30) #define CFGCTRL_FUNC_SHIFT 20 #define CFGCTRL_FUNC(fn) (fn << CFGCTRL_FUNC_SHIFT) #define FUNC_CLK_GEN 0x01 #define FUNC_TEMP 0x04 #define FUNC_DB_RESET 0x05 #define FUNC_SCC_CFG 0x06 #define FUNC_SHUTDOWN 0x08 #define FUNC_REBOOT 0x09 /* Load address of BL33 in the FVP port */ #define NS_IMAGE_OFFSET (DRAM1_BASE + 0x8000000) /* DRAM + 128MB */ /* Special value used to verify platform parameters from BL2 to BL3-1 */ #define FVP_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL /* * V2M sysled bit definitions. The values written to this * register are defined in arch.h & runtime_svc.h. Only * used by the primary cpu to diagnose any cold boot issues. * * SYS_LED[0] - Security state (S=0/NS=1) * SYS_LED[2:1] - Exception Level (EL3-EL0) * SYS_LED[7:3] - Exception Class (Sync/Async & origin) * */ #define SYS_LED_SS_SHIFT 0x0 #define SYS_LED_EL_SHIFT 0x1 #define SYS_LED_EC_SHIFT 0x3 #define SYS_LED_SS_MASK 0x1 #define SYS_LED_EL_MASK 0x3 #define SYS_LED_EC_MASK 0x1f /* V2M sysid register bits */ #define SYS_ID_REV_SHIFT 28 #define SYS_ID_HBI_SHIFT 16 #define SYS_ID_BLD_SHIFT 12 #define SYS_ID_ARCH_SHIFT 8 #define SYS_ID_FPGA_SHIFT 0 #define SYS_ID_REV_MASK 0xf #define SYS_ID_HBI_MASK 0xfff #define SYS_ID_BLD_MASK 0xf #define SYS_ID_ARCH_MASK 0xf #define SYS_ID_FPGA_MASK 0xff #define SYS_ID_BLD_LENGTH 4 #define HBI_FVP_BASE 0x020 #define REV_FVP_BASE_V0 0x0 #define HBI_FOUNDATION 0x010 #define REV_FOUNDATION_V2_0 0x0 #define REV_FOUNDATION_V2_1 0x1 #define BLD_GIC_VE_MMAP 0x0 #define BLD_GIC_A53A57_MMAP 0x1 #define ARCH_MODEL 0x1 /* FVP Power controller base address*/ #define PWRC_BASE 0x1c100000 /******************************************************************************* * CCI-400 related constants ******************************************************************************/ #define CCI400_BASE 0x2c090000 #define CCI400_SL_IFACE3_CLUSTER_IX 0 #define CCI400_SL_IFACE4_CLUSTER_IX 1 /******************************************************************************* * GIC-400 & interrupt handling related constants ******************************************************************************/ /* VE compatible GIC memory map */ #define VE_GICD_BASE 0x2c001000 #define VE_GICC_BASE 0x2c002000 #define VE_GICH_BASE 0x2c004000 #define VE_GICV_BASE 0x2c006000 /* Base FVP compatible GIC memory map */ #define BASE_GICD_BASE 0x2f000000 #define BASE_GICR_BASE 0x2f100000 #define BASE_GICC_BASE 0x2c000000 #define BASE_GICH_BASE 0x2c010000 #define BASE_GICV_BASE 0x2c02f000 #define IRQ_TZ_WDOG 56 #define IRQ_SEC_PHY_TIMER 29 #define IRQ_SEC_SGI_0 8 #define IRQ_SEC_SGI_1 9 #define IRQ_SEC_SGI_2 10 #define IRQ_SEC_SGI_3 11 #define IRQ_SEC_SGI_4 12 #define IRQ_SEC_SGI_5 13 #define IRQ_SEC_SGI_6 14 #define IRQ_SEC_SGI_7 15 #define IRQ_SEC_SGI_8 16 /******************************************************************************* * PL011 related constants ******************************************************************************/ #define PL011_UART0_BASE 0x1c090000 #define PL011_UART1_BASE 0x1c0a0000 #define PL011_UART2_BASE 0x1c0b0000 #define PL011_UART3_BASE 0x1c0c0000 #define PL011_BAUDRATE 115200 #define PL011_UART0_CLK_IN_HZ 24000000 #define PL011_UART1_CLK_IN_HZ 24000000 #define PL011_UART2_CLK_IN_HZ 24000000 #define PL011_UART3_CLK_IN_HZ 24000000 /******************************************************************************* * TrustZone address space controller related constants ******************************************************************************/ #define TZC400_BASE 0x2a4a0000 /* * The NSAIDs for this platform as used to program the TZC400. */ /* NSAIDs used by devices in TZC filter 0 on FVP */ #define FVP_NSAID_DEFAULT 0 #define FVP_NSAID_PCI 1 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ #define FVP_NSAID_AP 9 /* Application Processors */ #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ /* NSAIDs used by devices in TZC filter 2 on FVP */ #define FVP_NSAID_HDLCD0 2 #define FVP_NSAID_CLCD 7 /******************************************************************************* * Shared Data ******************************************************************************/ /* Entrypoint mailboxes */ #define MBOX_BASE FVP_SHARED_RAM_BASE #define MBOX_SIZE 0x200 /* Base address where parameters to BL31 are stored */ #define PARAMS_BASE (MBOX_BASE + MBOX_SIZE) #endif /* __FVP_DEF_H__ */ arm-trusted-firmware-1.0-aw-6/plat/fvp/fvp_io_storage.c000066400000000000000000000142771322600646200231240ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include /* For FOPEN_MODE_... */ #include /* IO devices */ static const io_dev_connector_t *sh_dev_con; static uintptr_t sh_dev_spec; static uintptr_t sh_init_params; static uintptr_t sh_dev_handle; static const io_dev_connector_t *fip_dev_con; static uintptr_t fip_dev_spec; static uintptr_t fip_dev_handle; static const io_dev_connector_t *memmap_dev_con; static uintptr_t memmap_dev_spec; static uintptr_t memmap_init_params; static uintptr_t memmap_dev_handle; static const io_block_spec_t fip_block_spec = { .offset = FLASH0_BASE, .length = FLASH0_SIZE }; static const io_file_spec_t bl2_file_spec = { .path = BL2_IMAGE_NAME, .mode = FOPEN_MODE_RB }; static const io_file_spec_t bl31_file_spec = { .path = BL31_IMAGE_NAME, .mode = FOPEN_MODE_RB }; static const io_file_spec_t bl32_file_spec = { .path = BL32_IMAGE_NAME, .mode = FOPEN_MODE_RB }; static const io_file_spec_t bl33_file_spec = { .path = BL33_IMAGE_NAME, .mode = FOPEN_MODE_RB }; static int open_fip(const uintptr_t spec); static int open_memmap(const uintptr_t spec); struct plat_io_policy { char *image_name; uintptr_t *dev_handle; uintptr_t image_spec; int (*check)(const uintptr_t spec); }; static const struct plat_io_policy policies[] = { { FIP_IMAGE_NAME, &memmap_dev_handle, (uintptr_t)&fip_block_spec, open_memmap }, { BL2_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl2_file_spec, open_fip }, { BL31_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl31_file_spec, open_fip }, { BL32_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl32_file_spec, open_fip }, { BL33_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl33_file_spec, open_fip }, { 0, 0, 0 } }; static int open_fip(const uintptr_t spec) { int result = IO_FAIL; /* See if a Firmware Image Package is available */ result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_NAME); if (result == IO_SUCCESS) { VERBOSE("Using FIP\n"); /*TODO: Check image defined in spec is present in FIP. */ } return result; } static int open_memmap(const uintptr_t spec) { int result = IO_FAIL; uintptr_t local_image_handle; result = io_dev_init(memmap_dev_handle, memmap_init_params); if (result == IO_SUCCESS) { result = io_open(memmap_dev_handle, spec, &local_image_handle); if (result == IO_SUCCESS) { VERBOSE("Using Memmap IO\n"); io_close(local_image_handle); } } return result; } static int open_semihosting(const uintptr_t spec) { int result = IO_FAIL; uintptr_t local_image_handle; /* See if the file exists on semi-hosting.*/ result = io_dev_init(sh_dev_handle, sh_init_params); if (result == IO_SUCCESS) { result = io_open(sh_dev_handle, spec, &local_image_handle); if (result == IO_SUCCESS) { VERBOSE("Using Semi-hosting IO\n"); io_close(local_image_handle); } } return result; } void fvp_io_setup (void) { int io_result = IO_FAIL; /* Register the IO devices on this platform */ io_result = register_io_dev_sh(&sh_dev_con); assert(io_result == IO_SUCCESS); io_result = register_io_dev_fip(&fip_dev_con); assert(io_result == IO_SUCCESS); io_result = register_io_dev_memmap(&memmap_dev_con); assert(io_result == IO_SUCCESS); /* Open connections to devices and cache the handles */ io_result = io_dev_open(sh_dev_con, sh_dev_spec, &sh_dev_handle); assert(io_result == IO_SUCCESS); io_result = io_dev_open(fip_dev_con, fip_dev_spec, &fip_dev_handle); assert(io_result == IO_SUCCESS); io_result = io_dev_open(memmap_dev_con, memmap_dev_spec, &memmap_dev_handle); assert(io_result == IO_SUCCESS); /* Ignore improbable errors in release builds */ (void)io_result; } /* Return an IO device handle and specification which can be used to access * an image. Use this to enforce platform load policy */ int plat_get_image_source(const char *image_name, uintptr_t *dev_handle, uintptr_t *image_spec) { int result = IO_FAIL; const struct plat_io_policy *policy; if ((image_name != NULL) && (dev_handle != NULL) && (image_spec != NULL)) { policy = policies; while (policy->image_name != NULL) { if (strcmp(policy->image_name, image_name) == 0) { result = policy->check(policy->image_spec); if (result == IO_SUCCESS) { *image_spec = policy->image_spec; *dev_handle = *(policy->dev_handle); break; } else { result = open_semihosting( policy->image_spec); if (result == IO_SUCCESS) { *dev_handle = sh_dev_handle; *image_spec = policy->image_spec; } } } policy++; } } else { result = IO_FAIL; } return result; } arm-trusted-firmware-1.0-aw-6/plat/fvp/fvp_pm.c000066400000000000000000000316371322600646200214040ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include "drivers/pwrc/fvp_pwrc.h" #include "fvp_def.h" #include "fvp_private.h" /******************************************************************************* * Private FVP function to program the mailbox for a cpu before it is released * from reset. ******************************************************************************/ static void fvp_program_mailbox(uint64_t mpidr, uint64_t address) { uint64_t linear_id; mailbox_t *fvp_mboxes; linear_id = platform_get_core_pos(mpidr); fvp_mboxes = (mailbox_t *)MBOX_BASE; fvp_mboxes[linear_id].value = address; flush_dcache_range((unsigned long) &fvp_mboxes[linear_id], sizeof(unsigned long)); } /******************************************************************************* * Function which implements the common FVP specific operations to power down a * cpu in response to a CPU_OFF or CPU_SUSPEND request. ******************************************************************************/ static void fvp_cpu_pwrdwn_common() { /* Prevent interrupts from spuriously waking up this cpu */ arm_gic_cpuif_deactivate(); /* Program the power controller to power off this cpu. */ fvp_pwrc_write_ppoffr(read_mpidr_el1()); } /******************************************************************************* * Function which implements the common FVP specific operations to power down a * cluster in response to a CPU_OFF or CPU_SUSPEND request. ******************************************************************************/ static void fvp_cluster_pwrdwn_common() { uint64_t mpidr = read_mpidr_el1(); /* Disable coherency if this cluster is to be turned off */ if (get_plat_config()->flags & CONFIG_HAS_CCI) cci_disable_cluster_coherency(mpidr); /* Program the power controller to turn the cluster off */ fvp_pwrc_write_pcoffr(mpidr); } /******************************************************************************* * Private FVP function which is used to determine if any platform actions * should be performed for the specified affinity instance given its * state. Nothing needs to be done if the 'state' is not off or if this is not * the highest affinity level which will enter the 'state'. ******************************************************************************/ static int32_t fvp_do_plat_actions(unsigned int afflvl, unsigned int state) { unsigned int max_phys_off_afflvl; assert(afflvl <= MPIDR_AFFLVL1); if (state != PSCI_STATE_OFF) return -EAGAIN; /* * Find the highest affinity level which will be suspended and postpone * all the platform specific actions until that level is hit. */ max_phys_off_afflvl = psci_get_max_phys_off_afflvl(); assert(max_phys_off_afflvl != PSCI_INVALID_DATA); if (afflvl != max_phys_off_afflvl) return -EAGAIN; return 0; } /******************************************************************************* * FVP handler called when an affinity instance is about to enter standby. ******************************************************************************/ int fvp_affinst_standby(unsigned int power_state) { unsigned int target_afflvl; /* Sanity check the requested state */ target_afflvl = psci_get_pstate_afflvl(power_state); /* * It's possible to enter standby only on affinity level 0 i.e. a cpu * on the FVP. Ignore any other affinity level. */ if (target_afflvl != MPIDR_AFFLVL0) return PSCI_E_INVALID_PARAMS; /* * Enter standby state * dsb is good practice before using wfi to enter low power states */ dsb(); wfi(); return PSCI_E_SUCCESS; } /******************************************************************************* * FVP handler called when an affinity instance is about to be turned on. The * level and mpidr determine the affinity instance. ******************************************************************************/ int fvp_affinst_on(unsigned long mpidr, unsigned long sec_entrypoint, unsigned long ns_entrypoint, unsigned int afflvl, unsigned int state) { int rc = PSCI_E_SUCCESS; unsigned int psysr; /* * It's possible to turn on only affinity level 0 i.e. a cpu * on the FVP. Ignore any other affinity level. */ if (afflvl != MPIDR_AFFLVL0) return rc; /* * Ensure that we do not cancel an inflight power off request * for the target cpu. That would leave it in a zombie wfi. * Wait for it to power off, program the jump address for the * target cpu and then program the power controller to turn * that cpu on */ do { psysr = fvp_pwrc_read_psysr(mpidr); } while (psysr & PSYSR_AFF_L0); fvp_program_mailbox(mpidr, sec_entrypoint); fvp_pwrc_write_pponr(mpidr); return rc; } /******************************************************************************* * FVP handler called when an affinity instance is about to be turned off. The * level and mpidr determine the affinity instance. The 'state' arg. allows the * platform to decide whether the cluster is being turned off and take apt * actions. * * CAUTION: There is no guarantee that caches will remain turned on across calls * to this function as each affinity level is dealt with. So do not write & read * global variables across calls. It will be wise to do flush a write to the * global to prevent unpredictable results. ******************************************************************************/ int fvp_affinst_off(unsigned long mpidr, unsigned int afflvl, unsigned int state) { /* Determine if any platform actions need to be executed */ if (fvp_do_plat_actions(afflvl, state) == -EAGAIN) return PSCI_E_SUCCESS; /* * If execution reaches this stage then this affinity level will be * suspended. Perform at least the cpu specific actions followed the * cluster specific operations if applicable. */ fvp_cpu_pwrdwn_common(); if (afflvl != MPIDR_AFFLVL0) fvp_cluster_pwrdwn_common(); return PSCI_E_SUCCESS; } /******************************************************************************* * FVP handler called when an affinity instance is about to be suspended. The * level and mpidr determine the affinity instance. The 'state' arg. allows the * platform to decide whether the cluster is being turned off and take apt * actions. * * CAUTION: There is no guarantee that caches will remain turned on across calls * to this function as each affinity level is dealt with. So do not write & read * global variables across calls. It will be wise to do flush a write to the * global to prevent unpredictable results. ******************************************************************************/ int fvp_affinst_suspend(unsigned long mpidr, unsigned long sec_entrypoint, unsigned long ns_entrypoint, unsigned int afflvl, unsigned int state) { /* Determine if any platform actions need to be executed. */ if (fvp_do_plat_actions(afflvl, state) == -EAGAIN) return PSCI_E_SUCCESS; /* Program the jump address for the target cpu */ fvp_program_mailbox(read_mpidr_el1(), sec_entrypoint); /* Program the power controller to enable wakeup interrupts. */ fvp_pwrc_set_wen(mpidr); /* Perform the common cpu specific operations */ fvp_cpu_pwrdwn_common(); /* Perform the common cluster specific operations */ if (afflvl != MPIDR_AFFLVL0) fvp_cluster_pwrdwn_common(); return PSCI_E_SUCCESS; } /******************************************************************************* * FVP handler called when an affinity instance has just been powered on after * being turned off earlier. The level and mpidr determine the affinity * instance. The 'state' arg. allows the platform to decide whether the cluster * was turned off prior to wakeup and do what's necessary to setup it up * correctly. ******************************************************************************/ int fvp_affinst_on_finish(unsigned long mpidr, unsigned int afflvl, unsigned int state) { int rc = PSCI_E_SUCCESS; /* Determine if any platform actions need to be executed. */ if (fvp_do_plat_actions(afflvl, state) == -EAGAIN) return PSCI_E_SUCCESS; /* Perform the common cluster specific operations */ if (afflvl != MPIDR_AFFLVL0) { /* * This CPU might have woken up whilst the cluster was * attempting to power down. In this case the FVP power * controller will have a pending cluster power off request * which needs to be cleared by writing to the PPONR register. * This prevents the power controller from interpreting a * subsequent entry of this cpu into a simple wfi as a power * down request. */ fvp_pwrc_write_pponr(mpidr); /* Enable coherency if this cluster was off */ fvp_cci_enable(); } /* * Clear PWKUPR.WEN bit to ensure interrupts do not interfere * with a cpu power down unless the bit is set again */ fvp_pwrc_clr_wen(mpidr); /* Zero the jump address in the mailbox for this cpu */ fvp_program_mailbox(read_mpidr_el1(), 0); /* Enable the gic cpu interface */ arm_gic_cpuif_setup(); /* TODO: This setup is needed only after a cold boot */ arm_gic_pcpu_distif_setup(); return rc; } /******************************************************************************* * FVP handler called when an affinity instance has just been powered on after * having been suspended earlier. The level and mpidr determine the affinity * instance. * TODO: At the moment we reuse the on finisher and reinitialize the secure * context. Need to implement a separate suspend finisher. ******************************************************************************/ int fvp_affinst_suspend_finish(unsigned long mpidr, unsigned int afflvl, unsigned int state) { return fvp_affinst_on_finish(mpidr, afflvl, state); } /******************************************************************************* * FVP handlers to shutdown/reboot the system ******************************************************************************/ static void __dead2 fvp_system_off(void) { /* Write the System Configuration Control Register */ mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL, CFGCTRL_START | CFGCTRL_RW | CFGCTRL_FUNC(FUNC_SHUTDOWN)); wfi(); ERROR("FVP System Off: operation not handled.\n"); panic(); } static void __dead2 fvp_system_reset(void) { /* Write the System Configuration Control Register */ mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL, CFGCTRL_START | CFGCTRL_RW | CFGCTRL_FUNC(FUNC_REBOOT)); wfi(); ERROR("FVP System Reset: operation not handled.\n"); panic(); } /******************************************************************************* * Export the platform handlers to enable psci to invoke them ******************************************************************************/ static const plat_pm_ops_t fvp_plat_pm_ops = { .affinst_standby = fvp_affinst_standby, .affinst_on = fvp_affinst_on, .affinst_off = fvp_affinst_off, .affinst_suspend = fvp_affinst_suspend, .affinst_on_finish = fvp_affinst_on_finish, .affinst_suspend_finish = fvp_affinst_suspend_finish, .system_off = fvp_system_off, .system_reset = fvp_system_reset }; /******************************************************************************* * Export the platform specific power ops & initialize the fvp power controller ******************************************************************************/ int platform_setup_pm(const plat_pm_ops_t **plat_ops) { *plat_ops = &fvp_plat_pm_ops; return 0; } arm-trusted-firmware-1.0-aw-6/plat/fvp/fvp_private.h000066400000000000000000000071311322600646200224370ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __FVP_PRIVATE_H__ #define __FVP_PRIVATE_H__ #include #include typedef volatile struct mailbox { unsigned long value __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE))); } mailbox_t; /******************************************************************************* * This structure represents the superset of information that is passed to * BL31 e.g. while passing control to it from BL2 which is bl31_params * and bl31_plat_params and its elements ******************************************************************************/ typedef struct bl2_to_bl31_params_mem { bl31_params_t bl31_params; image_info_t bl31_image_info; image_info_t bl32_image_info; image_info_t bl33_image_info; entry_point_info_t bl33_ep_info; entry_point_info_t bl32_ep_info; entry_point_info_t bl31_ep_info; } bl2_to_bl31_params_mem_t; /******************************************************************************* * Forward declarations ******************************************************************************/ struct meminfo; /******************************************************************************* * Function and variable prototypes ******************************************************************************/ void fvp_configure_mmu_el1(unsigned long total_base, unsigned long total_size, unsigned long, unsigned long, unsigned long, unsigned long); void fvp_configure_mmu_el3(unsigned long total_base, unsigned long total_size, unsigned long, unsigned long, unsigned long, unsigned long); int fvp_config_setup(void); void fvp_cci_init(void); void fvp_cci_enable(void); void fvp_gic_init(void); /* Declarations for fvp_topology.c */ int fvp_setup_topology(void); /* Declarations for fvp_io_storage.c */ void fvp_io_setup(void); /* Declarations for fvp_security.c */ void fvp_security_setup(void); /* Gets the SPR for BL32 entry */ uint32_t fvp_get_spsr_for_bl32_entry(void); /* Gets the SPSR for BL33 entry */ uint32_t fvp_get_spsr_for_bl33_entry(void); #endif /* __FVP_PRIVATE_H__ */ arm-trusted-firmware-1.0-aw-6/plat/fvp/fvp_security.c000066400000000000000000000113601322600646200226260ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include "fvp_def.h" #include "fvp_private.h" /* Used to improve readability for configuring regions. */ #define FILTER_SHIFT(filter) (1 << filter) /* * For the moment we assume that all security programming is done by the * primary core. * TODO: * Might want to enable interrupt on violations when supported? */ void fvp_security_setup(void) { /* * The Base FVP has a TrustZone address space controller, the Foundation * FVP does not. Trying to program the device on the foundation FVP will * cause an abort. * * If the platform had additional peripheral specific security * configurations, those would be configured here. */ if (!(get_plat_config()->flags & CONFIG_HAS_TZC)) return; /* * The TrustZone controller controls access to main DRAM. Give * full NS access for the moment to use with OS. */ INFO("Configuring TrustZone Controller\n"); /* * The driver does some error checking and will assert. * - Provide base address of device on platform. * - Provide width of ACE-Lite IDs on platform. */ tzc_init(TZC400_BASE); /* * Currently only filters 0 and 2 are connected on Base FVP. * Filter 0 : CPU clusters (no access to DRAM by default) * Filter 1 : not connected * Filter 2 : LCDs (access to VRAM allowed by default) * Filter 3 : not connected * Programming unconnected filters will have no effect at the * moment. These filter could, however, be connected in future. * So care should be taken not to configure the unused filters. */ /* Disable all filters before programming. */ tzc_disable_filters(); /* * Allow only non-secure access to all DRAM to supported devices. * Give access to the CPUs and Virtio. Some devices * would normally use the default ID so allow that too. We use * two regions to cover the blocks of physical memory in the FVPs. * * Software executing in the secure state, such as a secure * boot-loader, can access the DRAM by using the NS attributes in * the MMU translation tables and descriptors. */ /* Set to cover the first block of DRAM */ tzc_configure_region(FILTER_SHIFT(0), 1, DRAM1_BASE, DRAM1_END - DRAM1_SEC_SIZE, TZC_REGION_S_NONE, TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)); /* Set to cover the secure reserved region */ tzc_configure_region(FILTER_SHIFT(0), 3, (DRAM1_END - DRAM1_SEC_SIZE) + 1 , DRAM1_END, TZC_REGION_S_RDWR, 0x0); /* Set to cover the second block of DRAM */ tzc_configure_region(FILTER_SHIFT(0), 2, DRAM2_BASE, DRAM2_END, TZC_REGION_S_NONE, TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)); /* * TODO: Interrupts are not currently supported. The only * options we have are for access errors to occur quietly or to * cause an exception. We choose to cause an exception. */ tzc_set_action(TZC_ACTION_ERR); /* Enable filters. */ tzc_enable_filters(); } arm-trusted-firmware-1.0-aw-6/plat/fvp/fvp_topology.c000066400000000000000000000222641322600646200226400ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include /* TODO: Reusing psci error codes & state information. Get our own! */ #include #include "drivers/pwrc/fvp_pwrc.h" /* We treat '255' as an invalid affinity instance */ #define AFFINST_INVAL 0xff /******************************************************************************* * We support 3 flavours of the FVP: Foundation, Base AEM & Base Cortex. Each * flavour has a different topology. The common bit is that there can be a max. * of 2 clusters (affinity 1) and 4 cpus (affinity 0) per cluster. So we define * a tree like data structure which caters to these maximum bounds. It simply * marks the absent affinity level instances as PSCI_AFF_ABSENT e.g. there is no * cluster 1 on the Foundation FVP. The 'data' field is currently unused. ******************************************************************************/ typedef struct affinity_info { unsigned char sibling; unsigned char child; unsigned char state; unsigned int data; } affinity_info_t; /******************************************************************************* * The following two data structures store the topology tree for the fvp. There * is a separate array for each affinity level i.e. cpus and clusters. The child * and sibling references allow traversal inside and in between the two arrays. ******************************************************************************/ static affinity_info_t fvp_aff1_topology_map[PLATFORM_CLUSTER_COUNT]; static affinity_info_t fvp_aff0_topology_map[PLATFORM_CORE_COUNT]; /* Simple global variable to safeguard us from stupidity */ static unsigned int topology_setup_done; /******************************************************************************* * This function implements a part of the critical interface between the psci * generic layer and the platform to allow the former to detect the platform * topology. psci queries the platform to determine how many affinity instances * are present at a particular level for a given mpidr e.g. consider a dual * cluster platform where each cluster has 4 cpus. A call to this function with * (0, 0x100) will return the number of cpus implemented under cluster 1 i.e. 4. * Similarly a call with (1, 0x100) will return 2 i.e. the number of clusters. * This is 'cause we are effectively asking how many affinity level 1 instances * are implemented under affinity level 2 instance 0. ******************************************************************************/ unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr) { unsigned int aff_count = 1, ctr; unsigned char parent_aff_id; assert(topology_setup_done == 1); switch (aff_lvl) { case 3: case 2: /* * Assert if the parent affinity instance is not 0. * This also takes care of level 3 in an obfuscated way */ parent_aff_id = (mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK; assert(parent_aff_id == 0); /* * Report that we implement a single instance of * affinity levels 2 & 3 which are AFF_ABSENT */ break; case 1: /* Assert if the parent affinity instance is not 0. */ parent_aff_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; assert(parent_aff_id == 0); /* Fetch the starting index in the aff1 array */ for (ctr = 0; fvp_aff1_topology_map[ctr].sibling != AFFINST_INVAL; ctr = fvp_aff1_topology_map[ctr].sibling) { aff_count++; } break; case 0: /* Assert if the cluster id is anything apart from 0 or 1 */ parent_aff_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; assert(parent_aff_id < PLATFORM_CLUSTER_COUNT); /* Fetch the starting index in the aff0 array */ for (ctr = fvp_aff1_topology_map[parent_aff_id].child; fvp_aff0_topology_map[ctr].sibling != AFFINST_INVAL; ctr = fvp_aff0_topology_map[ctr].sibling) { aff_count++; } break; default: assert(0); } return aff_count; } /******************************************************************************* * This function implements a part of the critical interface between the psci * generic layer and the platform to allow the former to detect the state of a * affinity instance in the platform topology. psci queries the platform to * determine whether an affinity instance is present or absent. This caters for * topologies where an intermediate affinity level instance is missing e.g. * consider a platform which implements a single cluster with 4 cpus and there * is another cpu sitting directly on the interconnect along with the cluster. * The mpidrs of the cluster would range from 0x0-0x3. The mpidr of the single * cpu would be 0x100 to highlight that it does not belong to cluster 0. Cluster * 1 is however missing but needs to be accounted to reach this single cpu in * the topology tree. Hence it will be marked as PSCI_AFF_ABSENT. This is not * applicable to the FVP but depicted as an example. ******************************************************************************/ unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr) { unsigned int aff_state = PSCI_AFF_ABSENT, idx; idx = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; assert(topology_setup_done == 1); switch (aff_lvl) { case 3: case 2: /* Report affinity levels 2 & 3 as absent */ break; case 1: aff_state = fvp_aff1_topology_map[idx].state; break; case 0: /* * First get start index of the aff0 in its array & then add * to it the affinity id that we want the state of */ idx = fvp_aff1_topology_map[idx].child; idx += (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; aff_state = fvp_aff0_topology_map[idx].state; break; default: assert(0); } return aff_state; } /******************************************************************************* * Handy optimization to prevent the psci implementation from traversing through * affinity levels which are not present while detecting the platform topology. ******************************************************************************/ int plat_get_max_afflvl(void) { return MPIDR_AFFLVL1; } /******************************************************************************* * This function populates the FVP specific topology information depending upon * the FVP flavour its running on. We construct all the mpidrs we can handle * and rely on the PWRC.PSYSR to flag absent cpus when their status is queried. ******************************************************************************/ int fvp_setup_topology(void) { unsigned char aff0, aff1, aff_state, aff0_offset = 0; unsigned long mpidr; topology_setup_done = 0; for (aff1 = 0; aff1 < PLATFORM_CLUSTER_COUNT; aff1++) { fvp_aff1_topology_map[aff1].child = aff0_offset; fvp_aff1_topology_map[aff1].sibling = aff1 + 1; for (aff0 = 0; aff0 < PLATFORM_MAX_CPUS_PER_CLUSTER; aff0++) { mpidr = aff1 << MPIDR_AFF1_SHIFT; mpidr |= aff0 << MPIDR_AFF0_SHIFT; if (fvp_pwrc_read_psysr(mpidr) != PSYSR_INVALID) { /* * Presence of even a single aff0 indicates * presence of parent aff1 on the FVP. */ aff_state = PSCI_AFF_PRESENT; fvp_aff1_topology_map[aff1].state = PSCI_AFF_PRESENT; } else { aff_state = PSCI_AFF_ABSENT; } fvp_aff0_topology_map[aff0_offset].child = AFFINST_INVAL; fvp_aff0_topology_map[aff0_offset].state = aff_state; fvp_aff0_topology_map[aff0_offset].sibling = aff0_offset + 1; /* Increment the absolute number of aff0s traversed */ aff0_offset++; } /* Tie-off the last aff0 sibling to -1 to avoid overflow */ fvp_aff0_topology_map[aff0_offset - 1].sibling = AFFINST_INVAL; } /* Tie-off the last aff1 sibling to AFFINST_INVAL to avoid overflow */ fvp_aff1_topology_map[aff1 - 1].sibling = AFFINST_INVAL; topology_setup_done = 1; return 0; } arm-trusted-firmware-1.0-aw-6/plat/fvp/include/000077500000000000000000000000001322600646200213625ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/fvp/include/plat_macros.S000066400000000000000000000072231322600646200240160ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "../fvp_def.h" .section .rodata.gic_reg_name, "aS" gic_regs: .asciz "gic_hppir", "gic_ahppir", "gic_ctlr", "" gicd_pend_reg: .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" newline: .asciz "\n" spacer: .asciz ":\t\t0x" /* --------------------------------------------- * The below macro prints out relevant GIC * registers whenever an unhandled exception is * taken in BL3-1. * Clobbers: x0 - x10, x16, sp * --------------------------------------------- */ .macro plat_print_gic_regs adr x0, plat_config ldr w16, [x0, #CONFIG_GICC_BASE_OFFSET] cbz x16, exit_print_gic_regs /* gic base address is now in x16 */ adr x6, gic_regs /* Load the gic reg list to x6 */ /* Load the gic regs to gp regs used by str_in_crash_buf_print */ ldr w8, [x16, #GICC_HPPIR] ldr w9, [x16, #GICC_AHPPIR] ldr w10, [x16, #GICC_CTLR] /* Store to the crash buf and print to console */ bl str_in_crash_buf_print /* Print the GICD_ISPENDR regs */ add x7, x16, #GICD_ISPENDR adr x4, gicd_pend_reg bl asm_print_str gicd_ispendr_loop: sub x4, x7, x16 cmp x4, #0x280 b.eq exit_print_gic_regs bl asm_print_hex adr x4, spacer bl asm_print_str ldr x4, [x7], #8 bl asm_print_hex adr x4, newline bl asm_print_str b gicd_ispendr_loop exit_print_gic_regs: .endm .section .rodata.cci_reg_name, "aS" cci_iface_regs: .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" /* ------------------------------------------------ * The below macro prints out relevant interconnect * registers whenever an unhandled exception is * taken in BL3-1. * Clobbers: x0 - x9, sp * ------------------------------------------------ */ .macro plat_print_interconnect_regs adr x6, cci_iface_regs /* Store in x7 the base address of the first interface */ mov_imm x7, (CCI400_BASE + SLAVE_IFACE3_OFFSET) ldr w8, [x7, #SNOOP_CTRL_REG] /* Store in x7 the base address of the second interface */ mov_imm x7, (CCI400_BASE + SLAVE_IFACE4_OFFSET) ldr w9, [x7, #SNOOP_CTRL_REG] /* Store to the crash buf and print to console */ bl str_in_crash_buf_print .endm arm-trusted-firmware-1.0-aw-6/plat/fvp/include/platform_def.h000066400000000000000000000154501322600646200242020ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PLATFORM_DEF_H__ #define __PLATFORM_DEF_H__ #include #include "../fvp_def.h" /******************************************************************************* * Platform binary types for linking ******************************************************************************/ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 /******************************************************************************* * Generic platform constants ******************************************************************************/ /* Size of cacheable stacks */ #if DEBUG_XLAT_TABLE #define PLATFORM_STACK_SIZE 0x800 #elif IMAGE_BL1 #define PLATFORM_STACK_SIZE 0x440 #elif IMAGE_BL2 #define PLATFORM_STACK_SIZE 0x400 #elif IMAGE_BL31 #define PLATFORM_STACK_SIZE 0x400 #elif IMAGE_BL32 #define PLATFORM_STACK_SIZE 0x440 #endif #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" /* Trusted Boot Firmware BL2 */ #define BL2_IMAGE_NAME "bl2.bin" /* EL3 Runtime Firmware BL31 */ #define BL31_IMAGE_NAME "bl31.bin" /* Secure Payload BL32 (Trusted OS) */ #define BL32_IMAGE_NAME "bl32.bin" /* Non-Trusted Firmware BL33 */ #define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ #define PLATFORM_CACHE_LINE_SIZE 64 #define PLATFORM_CLUSTER_COUNT 2ull #define PLATFORM_CLUSTER0_CORE_COUNT 4 #define PLATFORM_CLUSTER1_CORE_COUNT 4 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ PLATFORM_CLUSTER0_CORE_COUNT) #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 #define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 /******************************************************************************* * BL1 specific defines. * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of * addresses. ******************************************************************************/ #define BL1_RO_BASE FVP_TRUSTED_ROM_BASE #define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \ + FVP_TRUSTED_ROM_SIZE) /* * Put BL1 RW at the top of the Trusted SRAM (just below the shared memory, if * present). BL1_RW_BASE is calculated using the current BL1 RW debug size plus * a little space for growth. */ #define BL1_RW_BASE (FVP_TRUSTED_SRAM_LIMIT - 0x6000) #define BL1_RW_LIMIT FVP_TRUSTED_SRAM_LIMIT /******************************************************************************* * BL2 specific defines. ******************************************************************************/ /* * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug * size plus a little space for growth. */ #define BL2_BASE (BL31_BASE - 0xC000) #define BL2_LIMIT BL31_BASE /******************************************************************************* * BL31 specific defines. ******************************************************************************/ /* * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if * present). BL31_BASE is calculated using the current BL3-1 debug size plus a * little space for growth. */ #define BL31_BASE (FVP_TRUSTED_SRAM_LIMIT - 0x1D000) #define BL31_PROGBITS_LIMIT BL1_RW_BASE #define BL31_LIMIT FVP_TRUSTED_SRAM_LIMIT /******************************************************************************* * BL32 specific defines. ******************************************************************************/ /* * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM. */ #if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_SRAM # define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE # define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE # define TSP_PROGBITS_LIMIT BL2_BASE # define BL32_BASE FVP_TRUSTED_SRAM_BASE # define BL32_LIMIT BL31_BASE #elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM # define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE # define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE # define BL32_BASE (FVP_TRUSTED_DRAM_BASE \ + FVP_SHARED_RAM_SIZE) # define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21)) #else # error "Unsupported FVP_TSP_RAM_LOCATION_ID value" #endif /* * ID of the secure physical generic timer interrupt used by the TSP. */ #define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ #define ADDR_SPACE_SIZE (1ull << 32) #define MAX_XLAT_TABLES 2 #define MAX_MMAP_REGIONS 16 /******************************************************************************* * Declarations and constants to access the mailboxes safely. Each mailbox is * aligned on the biggest cache line size in the platform. This is known only * to the platform as it might have a combination of integrated and external * caches. Such alignment ensures that two maiboxes do not sit on the same cache * line at any cache level. They could belong to different cpus/clusters & * get written while being protected by different locks causing corruption of * a valid mailbox address. ******************************************************************************/ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) #endif /* __PLATFORM_DEF_H__ */ arm-trusted-firmware-1.0-aw-6/plat/fvp/platform.mk000066400000000000000000000101251322600646200221130ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # Shared memory may be allocated at the top of Trusted SRAM (tsram) or at the # base of Trusted SRAM (tdram) FVP_SHARED_DATA_LOCATION := tsram ifeq (${FVP_SHARED_DATA_LOCATION}, tsram) FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_SRAM else ifeq (${FVP_SHARED_DATA_LOCATION}, tdram) FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_DRAM else $(error "Unsupported FVP_SHARED_DATA_LOCATION value") endif # On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM. # Trusted SRAM is the default. FVP_TSP_RAM_LOCATION := tsram ifeq (${FVP_TSP_RAM_LOCATION}, tsram) FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_SRAM else ifeq (${FVP_TSP_RAM_LOCATION}, tdram) FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_DRAM else $(error "Unsupported FVP_TSP_RAM_LOCATION value") endif ifeq (${FVP_SHARED_DATA_LOCATION}, tsram) ifeq (${FVP_TSP_RAM_LOCATION}, tdram) $(error Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported) endif endif # Process flags $(eval $(call add_define,FVP_SHARED_DATA_LOCATION_ID)) $(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID)) PLAT_INCLUDES := -Iplat/fvp/include/ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \ drivers/io/io_fip.c \ drivers/io/io_memmap.c \ drivers/io/io_semihosting.c \ drivers/io/io_storage.c \ lib/aarch64/xlat_tables.c \ lib/semihosting/semihosting.c \ lib/semihosting/aarch64/semihosting_call.S \ plat/common/aarch64/plat_common.c \ plat/fvp/fvp_io_storage.c BL1_SOURCES += drivers/arm/cci400/cci400.c \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ plat/common/aarch64/platform_up_stack.S \ plat/fvp/bl1_fvp_setup.c \ plat/fvp/aarch64/fvp_common.c \ plat/fvp/aarch64/fvp_helpers.S BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ plat/common/aarch64/platform_up_stack.S \ plat/fvp/bl2_fvp_setup.c \ plat/fvp/fvp_security.c \ plat/fvp/aarch64/fvp_common.c BL31_SOURCES += drivers/arm/cci400/cci400.c \ drivers/arm/gic/arm_gic.c \ drivers/arm/gic/gic_v2.c \ drivers/arm/gic/gic_v3.c \ drivers/arm/tzc400/tzc400.c \ lib/cpus/aarch64/aem_generic.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ plat/common/plat_gic.c \ plat/common/aarch64/platform_mp_stack.S \ plat/fvp/bl31_fvp_setup.c \ plat/fvp/fvp_pm.c \ plat/fvp/fvp_security.c \ plat/fvp/fvp_topology.c \ plat/fvp/aarch64/fvp_helpers.S \ plat/fvp/aarch64/fvp_common.c \ plat/fvp/drivers/pwrc/fvp_pwrc.c arm-trusted-firmware-1.0-aw-6/plat/fvp/tsp/000077500000000000000000000000001322600646200205455ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/fvp/tsp/tsp-fvp.mk000066400000000000000000000034661322600646200225060ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # TSP source files specific to FVP platform BL32_SOURCES += drivers/arm/gic/arm_gic.c \ drivers/arm/gic/gic_v2.c \ plat/common/aarch64/platform_mp_stack.S \ plat/common/plat_gic.c \ plat/fvp/aarch64/fvp_common.c \ plat/fvp/aarch64/fvp_helpers.S \ plat/fvp/tsp/tsp_fvp_setup.c arm-trusted-firmware-1.0-aw-6/plat/fvp/tsp/tsp_fvp_setup.c000066400000000000000000000102561322600646200236160ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "../fvp_def.h" #include "../fvp_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __RO_END__; extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ #define BL32_RO_BASE (unsigned long)(&__RO_START__) #define BL32_RO_LIMIT (unsigned long)(&__RO_END__) /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to * page-aligned addresses. */ #define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /******************************************************************************* * Initialize the UART ******************************************************************************/ void tsp_early_platform_setup(void) { /* * Initialize a different console than already in use to display * messages from TSP */ console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); /* Initialize the platform config for future decision making */ fvp_config_setup(); } /******************************************************************************* * Perform platform specific setup placeholder ******************************************************************************/ void tsp_platform_setup(void) { fvp_gic_init(); } /******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { fvp_configure_mmu_el1(BL32_RO_BASE, (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE), BL32_RO_BASE, BL32_RO_LIMIT, BL32_COHERENT_RAM_BASE, BL32_COHERENT_RAM_LIMIT); } arm-trusted-firmware-1.0-aw-6/plat/juno/000077500000000000000000000000001322600646200201175ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/juno/aarch64/000077500000000000000000000000001322600646200213475ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/juno/aarch64/bl1_plat_helpers.S000066400000000000000000000114371322600646200247210ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include "../juno_def.h" .globl platform_is_primary_cpu .globl platform_get_entrypoint .globl platform_cold_boot_init .globl plat_secondary_cold_boot_setup /* ----------------------------------------------------- * unsigned int platform_is_primary_cpu (unsigned int mpid); * * Given the mpidr say whether this cpu is the primary * cpu (applicable ony after a cold boot) * ----------------------------------------------------- */ func platform_is_primary_cpu mov x9, x30 bl platform_get_core_pos ldr x1, =SCP_BOOT_CFG_ADDR ldr x1, [x1] ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_MASK cmp x0, x1 cset x0, eq ret x9 /* ----------------------------------------------------- * void plat_secondary_cold_boot_setup (void); * * This function performs any platform specific actions * needed for a secondary cpu after a cold reset e.g * mark the cpu's presence, mechanism to place it in a * holding pen etc. * ----------------------------------------------------- */ func plat_secondary_cold_boot_setup /* Juno todo: Implement secondary CPU cold boot setup on Juno */ cb_panic: b cb_panic /* ----------------------------------------------------- * void platform_get_entrypoint (unsigned int mpid); * * Main job of this routine is to distinguish between * a cold and warm boot. * On a cold boot the secondaries first wait for the * platform to be initialized after which they are * hotplugged in. The primary proceeds to perform the * platform initialization. * On a warm boot, each cpu jumps to the address in its * mailbox. * * TODO: Not a good idea to save lr in a temp reg * ----------------------------------------------------- */ func platform_get_entrypoint mov x9, x30 // lr bl platform_get_core_pos ldr x1, =TRUSTED_MAILBOXES_BASE lsl x0, x0, #TRUSTED_MAILBOX_SHIFT ldr x0, [x1, x0] ret x9 /* ----------------------------------------------------- * void platform_cold_boot_init (bl1_main function); * * Routine called only by the primary cpu after a cold * boot to perform early platform initialization * ----------------------------------------------------- */ func platform_cold_boot_init mov x20, x0 /* --------------------------------------------- * Give ourselves a small coherent stack to * ease the pain of initializing the MMU and * CCI in assembler * --------------------------------------------- */ mrs x0, mpidr_el1 bl platform_set_coherent_stack /* --------------------------------------------- * Architectural init. can be generic e.g. * enabling stack alignment and platform spec- * ific e.g. MMU & page table setup as per the * platform memory map. Perform the latter here * and the former in bl1_main. * --------------------------------------------- */ bl bl1_early_platform_setup bl bl1_plat_arch_setup /* --------------------------------------------- * Give ourselves a stack allocated in Normal * -IS-WBWA memory * --------------------------------------------- */ mrs x0, mpidr_el1 bl platform_set_stack /* --------------------------------------------- * Jump to the main function. Returning from it * is a terminal error. * --------------------------------------------- */ blr x20 cb_init_panic: b cb_init_panic arm-trusted-firmware-1.0-aw-6/plat/juno/aarch64/juno_common.c000066400000000000000000000104501322600646200240360ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include "../juno_def.h" /* * Table of regions to map using the MMU. * This doesn't include Trusted RAM as the 'mem_layout' argument passed to * configure_mmu_elx() will give the available subset of that, */ static const mmap_region_t juno_mmap[] = { { TZROM_BASE, TZROM_BASE, TZROM_SIZE, MT_MEMORY | MT_RO | MT_SECURE }, { MHU_SECURE_BASE, MHU_SECURE_BASE, MHU_SECURE_SIZE, (MHU_PAYLOAD_CACHED ? MT_MEMORY : MT_DEVICE) | MT_RW | MT_SECURE }, { FLASH_BASE, FLASH_BASE, FLASH_SIZE, MT_MEMORY | MT_RO | MT_SECURE }, { EMMC_BASE, EMMC_BASE, EMMC_SIZE, MT_MEMORY | MT_RO | MT_SECURE }, { PSRAM_BASE, PSRAM_BASE, PSRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE }, /* Used for 'TZDRAM' */ { IOFPGA_BASE, IOFPGA_BASE, IOFPGA_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, { DRAM_BASE, DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS }, {0} }; /******************************************************************************* * Macro generating the code for the function setting up the pagetables as per * the platform memory map & initialize the mmu, for the given exception level ******************************************************************************/ #define DEFINE_CONFIGURE_MMU_EL(_el) \ void configure_mmu_el##_el(unsigned long total_base, \ unsigned long total_size, \ unsigned long ro_start, \ unsigned long ro_limit, \ unsigned long coh_start, \ unsigned long coh_limit) \ { \ mmap_add_region(total_base, total_base, \ total_size, \ MT_MEMORY | MT_RW | MT_SECURE); \ mmap_add_region(ro_start, ro_start, \ ro_limit - ro_start, \ MT_MEMORY | MT_RO | MT_SECURE); \ mmap_add_region(coh_start, coh_start, \ coh_limit - coh_start, \ MT_DEVICE | MT_RW | MT_SECURE); \ mmap_add(juno_mmap); \ init_xlat_tables(); \ \ enable_mmu_el##_el(0); \ } /* Define EL1 and EL3 variants of the function initialising the MMU */ DEFINE_CONFIGURE_MMU_EL(1) DEFINE_CONFIGURE_MMU_EL(3) unsigned long plat_get_ns_image_entrypoint(void) { return NS_IMAGE_OFFSET; } uint64_t plat_get_syscnt_freq(void) { uint64_t counter_base_frequency; /* Read the frequency from Frequency modes table */ counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF); /* The first entry of the frequency modes table must not be 0 */ if (counter_base_frequency == 0) panic(); return counter_base_frequency; } arm-trusted-firmware-1.0-aw-6/plat/juno/aarch64/plat_helpers.S000066400000000000000000000113361322600646200241610ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include "../juno_def.h" .globl plat_crash_console_init .globl plat_crash_console_putc .globl plat_report_exception .globl plat_reset_handler .globl platform_get_core_pos .globl platform_mem_init /* Define a crash console for the plaform */ #define JUNO_CRASH_CONSOLE_BASE PL011_UART0_BASE /* --------------------------------------------- * int plat_crash_console_init(void) * Function to initialize the crash console * without a C Runtime to print crash report. * Clobber list : x0, x1, x2 * --------------------------------------------- */ func plat_crash_console_init mov_imm x0, JUNO_CRASH_CONSOLE_BASE mov_imm x1, PL011_UART0_CLK_IN_HZ mov_imm x2, PL011_BAUDRATE b console_core_init /* --------------------------------------------- * int plat_crash_console_putc(int c) * Function to print a character on the crash * console without a C Runtime. * Clobber list : x1, x2 * --------------------------------------------- */ func plat_crash_console_putc mov_imm x1, JUNO_CRASH_CONSOLE_BASE b console_core_putc /* --------------------------------------------- * void plat_report_exception(unsigned int type) * Function to report an unhandled exception * with platform-specific means. * On Juno platform, it updates the LEDs * to indicate where we are * --------------------------------------------- */ func plat_report_exception mrs x1, CurrentEl lsr x1, x1, #MODE_EL_SHIFT lsl x1, x1, #SYS_LED_EL_SHIFT lsl x0, x0, #SYS_LED_EC_SHIFT mov x2, #(SECURE << SYS_LED_SS_SHIFT) orr x0, x0, x2 orr x0, x0, x1 mov x1, #VE_SYSREGS_BASE add x1, x1, #V2M_SYS_LED str w0, [x1] ret /* * Return 0 to 3 for the A53s and 4 or 5 for the A57s */ func platform_get_core_pos and x1, x0, #MPIDR_CPU_MASK and x0, x0, #MPIDR_CLUSTER_MASK eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap A53/A57 order add x0, x1, x0, LSR #6 ret /* ----------------------------------------------------- * void platform_mem_init(void); * * We don't need to carry out any memory initialization * on Juno. The Secure RAM is accessible straight away. * ----------------------------------------------------- */ func platform_mem_init ret /* ----------------------------------------------------- * void plat_reset_handler(void); * * Implement workaround for defect id 831273 by enabling * an event stream every 65536 cycles and set the L2 RAM * latencies for Cortex-A57. * ----------------------------------------------------- */ func plat_reset_handler /* Read the MIDR_EL1 */ mrs x0, midr_el1 ubfx x1, x0, MIDR_PN_SHIFT, #12 cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) b.ne 1f /* Change the L2 Data and Tag Ram latency to 3 cycles */ mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES | \ (L2_TAG_RAM_LATENCY_3_CYCLES << \ L2CTLR_TAG_RAM_LATENCY_SHIFT)) msr L2CTLR_EL1, x0 1: /* --------------------------------------------- * Enable the event stream every 65536 cycles * --------------------------------------------- */ mov x0, #(0xf << EVNTI_SHIFT) orr x0, x0, #EVNTEN_BIT msr CNTKCTL_EL1, x0 isb ret arm-trusted-firmware-1.0-aw-6/plat/juno/bl1_plat_setup.c000066400000000000000000000210511322600646200232000ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include "../../bl1/bl1_private.h" #include "juno_def.h" #include "juno_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted RAM ******************************************************************************/ extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to * page-aligned addresses. */ #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /* Data structure which holds the extents of the trusted RAM for BL1 */ static meminfo_t bl1_tzram_layout; meminfo_t *bl1_plat_sec_mem_layout(void) { return &bl1_tzram_layout; } /******************************************************************************* * Perform any BL1 specific platform actions. ******************************************************************************/ void bl1_early_platform_setup(void) { const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; /* Initialize the console to provide early debug support */ console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); /* * Enable CCI-400 for this cluster. No need for locks as no other cpu is * active at the moment */ cci_init(CCI400_BASE, CCI400_SL_IFACE3_CLUSTER_IX, CCI400_SL_IFACE4_CLUSTER_IX); cci_enable_cluster_coherency(read_mpidr()); /* Allow BL1 to see the whole Trusted RAM */ bl1_tzram_layout.total_base = TZRAM_BASE; bl1_tzram_layout.total_size = TZRAM_SIZE; /* Calculate how much RAM BL1 is using and how much remains free */ bl1_tzram_layout.free_base = TZRAM_BASE; bl1_tzram_layout.free_size = TZRAM_SIZE; reserve_mem(&bl1_tzram_layout.free_base, &bl1_tzram_layout.free_size, BL1_RAM_BASE, bl1_size); INFO("BL1: 0x%lx - 0x%lx [size = %u]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, bl1_size); } /* * Address of slave 'n' security setting in the NIC-400 address region * control * TODO: Ideally this macro should be moved in a "nic-400.h" header file but * it would be the only thing in there so it's not worth it at the moment. */ #define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4) static void init_nic400(void) { /* * NIC-400 Access Control Initialization * * Define access privileges by setting each corresponding bit to: * 0 = Secure access only * 1 = Non-secure access allowed */ /* * Allow non-secure access to some SOC regions, excluding UART1, which * remains secure. * Note: This is the NIC-400 device on the SOC */ mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_EHCI), ~0); mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_TLX_MASTER), ~0); mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_OHCI), ~0); mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_PL354_SMC), ~0); mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_APB4_BRIDGE), ~0); mmio_write_32(SOC_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_BOOTSEC_BRIDGE), ~SOC_NIC400_BOOTSEC_BRIDGE_UART1); /* * Allow non-secure access to some CSS regions. * Note: This is the NIC-400 device on the CSS */ mmio_write_32(CSS_NIC400_BASE + NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE), ~0); } static void init_tzc400(void) { /* Enable all filter units available */ mmio_write_32(TZC400_BASE + GATE_KEEPER_OFF, 0x0000000f); /* * Secure read and write are enabled for region 0, and the background * region (region 0) is enabled for all four filter units */ mmio_write_32(TZC400_BASE + REGION_ATTRIBUTES_OFF, 0xc0000000); /* * Enable Non-secure read/write accesses for the Soc Devices from the * Non-Secure World */ mmio_write_32(TZC400_BASE + REGION_ID_ACCESS_OFF, TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP) | TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT) ); } #define PCIE_SECURE_REG 0x3000 #define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */ static void init_pcie(void) { /* * PCIE Root Complex Security settings to enable non-secure * access to config registers. */ mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK); } /******************************************************************************* * Function which will perform any remaining platform-specific setup that can * occur after the MMU and data cache have been enabled. ******************************************************************************/ void bl1_platform_setup(void) { init_nic400(); init_tzc400(); init_pcie(); /* Initialise the IO layer and register platform IO devices */ io_setup(); /* Enable and initialize the System level generic timer */ mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); } /******************************************************************************* * Perform the very early platform specific architecture setup here. At the * moment this only does basic initialization. Later architectural setup * (bl1_arch_setup()) does not do anything platform specific. ******************************************************************************/ void bl1_plat_arch_setup(void) { configure_mmu_el3(bl1_tzram_layout.total_base, bl1_tzram_layout.total_size, TZROM_BASE, TZROM_BASE + TZROM_SIZE, BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT); } /******************************************************************************* * Before calling this function BL2 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL2 and set SPSR and security state. * On Juno we are only setting the security state, entrypoint ******************************************************************************/ void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, entry_point_info_t *bl2_ep) { SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } arm-trusted-firmware-1.0-aw-6/plat/juno/bl2_plat_setup.c000066400000000000000000000304501322600646200232040ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include "juno_def.h" #include "juno_private.h" #include "scp_bootloader.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted RAM ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __RO_END__; extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ #define BL2_RO_BASE (unsigned long)(&__RO_START__) #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to * page-aligned addresses. */ #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /* Data structure which holds the extents of the trusted RAM for BL2 */ static meminfo_t bl2_tzram_layout __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE), section("tzfw_coherent_mem"))); /******************************************************************************* * Structure which holds the arguments which need to be passed to BL3-1 ******************************************************************************/ static bl2_to_bl31_params_mem_t bl31_params_mem; meminfo_t *bl2_plat_sec_mem_layout(void) { return &bl2_tzram_layout; } /******************************************************************************* * This function assigns a pointer to the memory that the platform has kept * aside to pass platform specific and trusted firmware related information * to BL31. This memory is allocated by allocating memory to * bl2_to_bl31_params_mem_t structure which is a superset of all the * structure whose information is passed to BL31 * NOTE: This function should be called only once and should be done * before generating params to BL31 ******************************************************************************/ bl31_params_t *bl2_plat_get_bl31_params(void) { bl31_params_t *bl2_to_bl31_params; /* * Initialise the memory for all the arguments that needs to * be passed to BL3-1 */ memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); /* Assign memory for TF related information */ bl2_to_bl31_params = &bl31_params_mem.bl31_params; SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); /* Fill BL3-1 related information */ bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); /* Fill BL3-2 related information if it exists */ #if BL32_BASE bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, VERSION_1, 0); bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); #endif /* Fill BL3-3 related information */ bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, PARAM_EP, VERSION_1, 0); /* BL3-3 expects to receive the primary CPU MPID (through x0) */ bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); return bl2_to_bl31_params; } /******************************************************************************* * This function returns a pointer to the shared memory that the platform * has kept to point to entry point information of BL31 to BL2 ******************************************************************************/ struct entry_point_info *bl2_plat_get_bl31_ep_info(void) { #if DEBUG bl31_params_mem.bl31_ep_info.args.arg1 = JUNO_BL31_PLAT_PARAM_VAL; #endif return &bl31_params_mem.bl31_ep_info; } /******************************************************************************* * BL1 has passed the extents of the trusted RAM that should be visible to BL2 * in x0. This memory layout is sitting at the base of the free trusted RAM. * Copy it to a safe loaction before its reclaimed by later BL2 functionality. ******************************************************************************/ void bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); /* Setup the BL2 memory layout */ bl2_tzram_layout = *mem_layout; } /******************************************************************************* * Perform platform specific setup, i.e. initialize the IO layer, load BL3-0 * image and initialise the memory location to use for passing arguments to * BL3-1. ******************************************************************************/ void bl2_platform_setup(void) { /* Initialise the IO layer and register platform IO devices */ io_setup(); } /* Flush the TF params and the TF plat params */ void bl2_plat_flush_bl31_params(void) { flush_dcache_range((unsigned long)&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t)); } /******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void bl2_plat_arch_setup(void) { configure_mmu_el1(bl2_tzram_layout.total_base, bl2_tzram_layout.total_size, BL2_RO_BASE, BL2_RO_LIMIT, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT); } /******************************************************************************* * Populate the extents of memory available for loading BL3-0, i.e. anywhere * in trusted RAM as long as it doesn't overwrite BL2. ******************************************************************************/ void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo) { *bl30_meminfo = bl2_tzram_layout; } /******************************************************************************* * Transfer BL3-0 from Trusted RAM using the SCP Download protocol. * Return 0 on success, -1 otherwise. ******************************************************************************/ int bl2_plat_handle_bl30(image_info_t *bl30_image_info) { int ret; ret = scp_bootloader_transfer((void *)bl30_image_info->image_base, bl30_image_info->image_size); if (ret == 0) INFO("BL2: BL3-0 transferred to SCP\n\r"); else ERROR("BL2: BL3-0 transfer failure\n\r"); return ret; } /******************************************************************************* * Before calling this function BL31 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL31 and set SPSR and security state. * On Juno we are only setting the security state, entrypoint ******************************************************************************/ void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, entry_point_info_t *bl31_ep_info) { SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } /******************************************************************************* * Before calling this function BL32 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL32 and set SPSR and security state. * On Juno we are only setting the security state, entrypoint ******************************************************************************/ void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, entry_point_info_t *bl32_ep_info) { SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); /* * The Secure Payload Dispatcher service is responsible for * setting the SPSR prior to entry into the BL32 image. */ bl32_ep_info->spsr = 0; } /******************************************************************************* * Before calling this function BL33 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL33 and set SPSR and security state. * On Juno we are only setting the security state, entrypoint ******************************************************************************/ void bl2_plat_set_bl33_ep_info(image_info_t *image, entry_point_info_t *bl33_ep_info) { unsigned long el_status; unsigned int mode; /* Figure out what mode we enter the non-secure world in */ el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; el_status &= ID_AA64PFR0_ELX_MASK; if (el_status) mode = MODE_EL2; else mode = MODE_EL1; /* * TODO: Consider the possibility of specifying the SPSR in * the FIP ToC and allowing the platform to have a say as * well. */ bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); } /******************************************************************************* * Populate the extents of memory available for loading BL3-2 ******************************************************************************/ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) { /* * Populate the extents of memory available for loading BL3-2. */ bl32_meminfo->total_base = BL32_BASE; bl32_meminfo->free_base = BL32_BASE; bl32_meminfo->total_size = (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; bl32_meminfo->free_size = (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; } /******************************************************************************* * Populate the extents of memory available for loading BL3-3 ******************************************************************************/ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) { bl33_meminfo->total_base = DRAM_BASE; bl33_meminfo->total_size = DRAM_SIZE; bl33_meminfo->free_base = DRAM_BASE; bl33_meminfo->free_size = DRAM_SIZE; } arm-trusted-firmware-1.0-aw-6/plat/juno/bl31_plat_setup.c000066400000000000000000000163621322600646200232740ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include "juno_def.h" #include "juno_private.h" #include "mhu.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted RAM ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __RO_END__; extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ #define BL31_RO_BASE (unsigned long)(&__RO_START__) #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols * refer to page-aligned addresses. */ #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /****************************************************************************** * Placeholder variables for copying the arguments that have been passed to * BL3-1 from BL2. ******************************************************************************/ static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for * the security state specified. BL3-3 corresponds to the non-secure image type * while BL3-2 corresponds to the secure image type. A NULL pointer is returned * if the image does not exist. ******************************************************************************/ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) { entry_point_info_t *next_image_info; next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; /* None of the images on this platform can have 0x0 as the entrypoint */ if (next_image_info->pc) return next_image_info; else return NULL; } /******************************************************************************* * Perform any BL3-1 specific platform actions. Here is an opportunity to copy * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they * are lost (potentially). This needs to be done before the MMU is initialized * so that the memory layout can be used while creating page tables. Also, BL2 * has flushed this information to memory, so we are guaranteed to pick up good * data ******************************************************************************/ void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { /* Initialize the console to provide early debug support */ console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); /* * Initialise the CCI-400 driver for BL31 so that it is accessible after * a warm boot. BL1 should have already enabled CCI coherency for this * cluster during cold boot. */ cci_init(CCI400_BASE, CCI400_SL_IFACE3_CLUSTER_IX, CCI400_SL_IFACE4_CLUSTER_IX); /* * Check params passed from BL2 should not be NULL, */ assert(from_bl2 != NULL); assert(from_bl2->h.type == PARAM_BL31); assert(from_bl2->h.version >= VERSION_1); /* * In debug builds, we pass a special value in 'plat_params_from_bl2' * to verify platform parameters from BL2 to BL3-1. * In release builds, it's not used. */ assert(((unsigned long long)plat_params_from_bl2) == JUNO_BL31_PLAT_PARAM_VAL); /* * Copy BL3-2 and BL3-3 entry point information. * They are stored in Secure RAM, in BL2's address space. */ bl32_ep_info = *from_bl2->bl32_ep_info; bl33_ep_info = *from_bl2->bl33_ep_info; } /******************************************************************************* * Initialize the MHU and the GIC. ******************************************************************************/ void bl31_platform_setup(void) { unsigned int reg_val; mhu_secure_init(); /* Initialize the gic cpu and distributor interfaces */ gic_setup(); /* Enable and initialize the System level generic timer */ mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); /* Allow access to the System counter timer module */ reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); reg_val = (1 << CNTNSAR_NS_SHIFT(1)); mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); /* Topologies are best known to the platform. */ plat_setup_topology(); } /******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup() { configure_mmu_el3(BL31_RO_BASE, BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE, BL31_RO_BASE, BL31_RO_LIMIT, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT); } arm-trusted-firmware-1.0-aw-6/plat/juno/include/000077500000000000000000000000001322600646200215425ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/juno/include/plat_macros.S000066400000000000000000000070561322600646200242020ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include "platform_def.h" #include "../juno_def.h" .section .rodata.gic_reg_name, "aS" gic_regs: .asciz "gic_hppir", "gic_ahppir", "gic_ctlr", "" gicd_pend_reg: .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" newline: .asciz "\n" spacer: .asciz ":\t\t0x" /* --------------------------------------------- * The below macro prints out relevant GIC * registers whenever an unhandled exception is * taken in BL3-1. * Clobbers: x0 - x10, x16, sp * --------------------------------------------- */ .macro plat_print_gic_regs ldr x16, =GICC_BASE /* Load the gic reg list to x6 */ adr x6, gic_regs /* Load the gic regs to gp regs used by str_in_crash_buf_print */ ldr w8, [x16, #GICC_HPPIR] ldr w9, [x16, #GICC_AHPPIR] ldr w10, [x16, #GICC_CTLR] /* Store to the crash buf and print to console */ bl str_in_crash_buf_print /* Print the GICD_ISPENDR regs */ add x7, x16, #GICD_ISPENDR adr x4, gicd_pend_reg bl asm_print_str gicd_ispendr_loop: sub x4, x7, x16 cmp x4, #0x280 b.eq exit_print_gic_regs bl asm_print_hex adr x4, spacer bl asm_print_str ldr x4, [x7], #8 bl asm_print_hex adr x4, newline bl asm_print_str b gicd_ispendr_loop exit_print_gic_regs: .endm .section .rodata.cci_reg_name, "aS" cci_iface_regs: .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" /* ------------------------------------------------ * The below macro prints out relevant interconnect * registers whenever an unhandled exception is * taken in BL3-1. * Clobbers: x0 - x9, sp * ------------------------------------------------ */ .macro plat_print_interconnect_regs adr x6, cci_iface_regs /* Store in x7 the base address of the first interface */ mov_imm x7, (CCI400_BASE + SLAVE_IFACE3_OFFSET) ldr w8, [x7, #SNOOP_CTRL_REG] /* Store in x7 the base address of the second interface */ mov_imm x7, (CCI400_BASE + SLAVE_IFACE4_OFFSET) ldr w9, [x7, #SNOOP_CTRL_REG] /* Store to the crash buf and print to console */ bl str_in_crash_buf_print .endm arm-trusted-firmware-1.0-aw-6/plat/juno/include/platform_def.h000066400000000000000000000153001322600646200243540ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PLATFORM_DEF_H__ #define __PLATFORM_DEF_H__ #include #include "../juno_def.h" /******************************************************************************* * Platform binary types for linking ******************************************************************************/ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 /******************************************************************************* * Generic platform constants ******************************************************************************/ /* Size of cacheable stacks */ #define PLATFORM_STACK_SIZE 0x800 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" /* Trusted Boot Firmware BL2 */ #define BL2_IMAGE_NAME "bl2.bin" /* EL3 Runtime Firmware BL3-1 */ #define BL31_IMAGE_NAME "bl31.bin" /* SCP Firmware BL3-0 */ #define BL30_IMAGE_NAME "bl30.bin" /* Secure Payload BL3-2 (Trusted OS) */ #define BL32_IMAGE_NAME "bl32.bin" /* Non-Trusted Firmware BL3-3 */ #define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ /* Firmware Image Package */ #define FIP_IMAGE_NAME "fip.bin" #define PLATFORM_CACHE_LINE_SIZE 64 #define PLATFORM_CLUSTER_COUNT 2 #define PLATFORM_CORE_COUNT 6 #define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ PLATFORM_CORE_COUNT) #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 /******************************************************************************* * Platform memory map related constants ******************************************************************************/ #define FLASH_BASE 0x08000000 #define FLASH_SIZE 0x04000000 /* Bypass offset from start of NOR flash */ #define BL1_ROM_BYPASS_OFFSET 0x03EC0000 #ifndef TZROM_BASE /* Use the bypass address */ #define TZROM_BASE FLASH_BASE + BL1_ROM_BYPASS_OFFSET #endif #define TZROM_SIZE 0x00010000 #define TZRAM_BASE 0x04001000 #define TZRAM_SIZE 0x0003F000 /******************************************************************************* * BL1 specific defines. * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base * addresses. ******************************************************************************/ #define BL1_RO_BASE TZROM_BASE #define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) #define BL1_RW_BASE TZRAM_BASE #define BL1_RW_LIMIT BL31_BASE /******************************************************************************* * BL2 specific defines. ******************************************************************************/ #define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xd000) #define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE) /******************************************************************************* * Load address of BL3-0 in the Juno port * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the * SCP, it is discarded and BL3-1 is loaded over the top. ******************************************************************************/ #define BL30_BASE BL31_BASE /******************************************************************************* * BL3-1 specific defines. ******************************************************************************/ #define BL31_BASE (TZRAM_BASE + 0x8000) #define BL31_LIMIT BL32_BASE /******************************************************************************* * BL3-2 specific defines. ******************************************************************************/ #define TSP_SEC_MEM_BASE TZRAM_BASE #define TSP_SEC_MEM_SIZE TZRAM_SIZE #define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000) #define BL32_LIMIT BL2_BASE /******************************************************************************* * Load address of BL3-3 in the Juno port ******************************************************************************/ #define NS_IMAGE_OFFSET 0xE0000000 /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ #define ADDR_SPACE_SIZE (1ull << 32) #define MAX_XLAT_TABLES 2 #define MAX_MMAP_REGIONS 16 /******************************************************************************* * ID of the secure physical generic timer interrupt used by the TSP ******************************************************************************/ #define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER /******************************************************************************* * Declarations and constants to access the mailboxes safely. Each mailbox is * aligned on the biggest cache line size in the platform. This is known only * to the platform as it might have a combination of integrated and external * caches. Such alignment ensures that two maiboxes do not sit on the same cache * line at any cache level. They could belong to different cpus/clusters & * get written while being protected by different locks causing corruption of * a valid mailbox address. ******************************************************************************/ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) #endif /* __PLATFORM_DEF_H__ */ arm-trusted-firmware-1.0-aw-6/plat/juno/juno_def.h000066400000000000000000000155421322600646200220700ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __JUNO_DEF_H__ #define __JUNO_DEF_H__ /* Special value used to verify platform parameters from BL2 to BL3-1 */ #define JUNO_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL /******************************************************************************* * Juno memory map related constants ******************************************************************************/ #define MHU_SECURE_BASE 0x04000000 #define MHU_SECURE_SIZE 0x00001000 #define MHU_PAYLOAD_CACHED 0 #define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE #define TRUSTED_MAILBOX_SHIFT 4 #define EMMC_BASE 0x0c000000 #define EMMC_SIZE 0x04000000 #define PSRAM_BASE 0x14000000 #define PSRAM_SIZE 0x02000000 #define IOFPGA_BASE 0x1c000000 #define IOFPGA_SIZE 0x03000000 #define NSROM_BASE 0x1f000000 #define NSROM_SIZE 0x00001000 /* Following covers Columbus Peripherals excluding NSROM and NSRAM */ #define DEVICE0_BASE 0x20000000 #define DEVICE0_SIZE 0x0e000000 #define MHU_BASE 0x2b1f0000 #define NSRAM_BASE 0x2e000000 #define NSRAM_SIZE 0x00008000 /* Following covers Juno Peripherals and PCIe expansion area */ #define DEVICE1_BASE 0x40000000 #define DEVICE1_SIZE 0x40000000 #define PCIE_CONTROL_BASE 0x7ff20000 #define DRAM_BASE 0x80000000 #define DRAM_SIZE 0x80000000 /* Memory mapped Generic timer interfaces */ #define SYS_CNTCTL_BASE 0x2a430000 #define SYS_CNTREAD_BASE 0x2a800000 #define SYS_TIMCTL_BASE 0x2a810000 /* V2M motherboard system registers & offsets */ #define VE_SYSREGS_BASE 0x1c010000 #define V2M_SYS_LED 0x8 /* * V2M sysled bit definitions. The values written to this * register are defined in arch.h & runtime_svc.h. Only * used by the primary cpu to diagnose any cold boot issues. * * SYS_LED[0] - Security state (S=0/NS=1) * SYS_LED[2:1] - Exception Level (EL3-EL0) * SYS_LED[7:3] - Exception Class (Sync/Async & origin) * */ #define SYS_LED_SS_SHIFT 0x0 #define SYS_LED_EL_SHIFT 0x1 #define SYS_LED_EC_SHIFT 0x3 /******************************************************************************* * GIC-400 & interrupt handling related constants ******************************************************************************/ #define GICD_BASE 0x2c010000 #define GICC_BASE 0x2c02f000 #define GICH_BASE 0x2c04f000 #define GICV_BASE 0x2c06f000 #define IRQ_MHU 69 #define IRQ_GPU_SMMU_0 71 #define IRQ_GPU_SMMU_1 73 #define IRQ_ETR_SMMU 75 #define IRQ_TZC400 80 #define IRQ_TZ_WDOG 86 #define IRQ_SEC_PHY_TIMER 29 #define IRQ_SEC_SGI_0 8 #define IRQ_SEC_SGI_1 9 #define IRQ_SEC_SGI_2 10 #define IRQ_SEC_SGI_3 11 #define IRQ_SEC_SGI_4 12 #define IRQ_SEC_SGI_5 13 #define IRQ_SEC_SGI_6 14 #define IRQ_SEC_SGI_7 15 #define IRQ_SEC_SGI_8 16 /******************************************************************************* * PL011 related constants ******************************************************************************/ /* FPGA UART0 */ #define PL011_UART0_BASE 0x1c090000 /* FPGA UART1 */ #define PL011_UART1_BASE 0x1c0a0000 /* SoC UART0 */ #define PL011_UART2_BASE 0x7ff80000 /* SoC UART1 */ #define PL011_UART3_BASE 0x7ff70000 #define PL011_BAUDRATE 115200 #define PL011_UART0_CLK_IN_HZ 24000000 #define PL011_UART1_CLK_IN_HZ 24000000 #define PL011_UART2_CLK_IN_HZ 7273800 #define PL011_UART3_CLK_IN_HZ 7273800 /******************************************************************************* * NIC-400 related constants ******************************************************************************/ /* CSS NIC-400 Global Programmers View (GPV) */ #define CSS_NIC400_BASE 0x2a000000 /* The slave_bootsecure controls access to GPU, DMC and CS. */ #define CSS_NIC400_SLAVE_BOOTSECURE 8 /* SoC NIC-400 Global Programmers View (GPV) */ #define SOC_NIC400_BASE 0x7fd00000 #define SOC_NIC400_USB_EHCI 0 #define SOC_NIC400_TLX_MASTER 1 #define SOC_NIC400_USB_OHCI 2 #define SOC_NIC400_PL354_SMC 3 /* * The apb4_bridge controls access to: * - the PCIe configuration registers * - the MMU units for USB, HDLCD and DMA */ #define SOC_NIC400_APB4_BRIDGE 4 /* * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. */ #define SOC_NIC400_BOOTSEC_BRIDGE 5 #define SOC_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) /******************************************************************************* * TZC-400 related constants ******************************************************************************/ #define TZC400_BASE 0x2a4a0000 #define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ #define TZC400_NSAID_PCIE 1 #define TZC400_NSAID_HDLCD0 2 #define TZC400_NSAID_HDLCD1 3 #define TZC400_NSAID_USB 4 #define TZC400_NSAID_DMA330 5 #define TZC400_NSAID_THINLINKS 6 #define TZC400_NSAID_AP 9 #define TZC400_NSAID_GPU 10 #define TZC400_NSAID_SCP 11 #define TZC400_NSAID_CORESIGHT 12 /******************************************************************************* * CCI-400 related constants ******************************************************************************/ #define CCI400_BASE 0x2c090000 #define CCI400_SL_IFACE3_CLUSTER_IX 1 #define CCI400_SL_IFACE4_CLUSTER_IX 0 /******************************************************************************* * SCP <=> AP boot configuration ******************************************************************************/ #define SCP_BOOT_CFG_ADDR 0x04000080 #define PRIMARY_CPU_SHIFT 8 #define PRIMARY_CPU_MASK 0xf #endif /* __JUNO_DEF_H__ */ arm-trusted-firmware-1.0-aw-6/plat/juno/juno_private.h000066400000000000000000000143061322600646200230010ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __JUNO_PRIVATE_H__ #define __JUNO_PRIVATE_H__ #include #include #include /******************************************************************************* * Forward declarations ******************************************************************************/ struct plat_pm_ops; struct meminfo; struct bl31_params; struct image_info; struct entry_point_info; /******************************************************************************* * This structure represents the superset of information that is passed to * BL3-1 e.g. while passing control to it from BL2 which is bl31_params * and other platform specific params ******************************************************************************/ typedef struct bl2_to_bl31_params_mem { struct bl31_params bl31_params; struct image_info bl31_image_info; struct image_info bl32_image_info; struct image_info bl33_image_info; struct entry_point_info bl33_ep_info; struct entry_point_info bl32_ep_info; struct entry_point_info bl31_ep_info; } bl2_to_bl31_params_mem_t; /******************************************************************************* * Function and variable prototypes ******************************************************************************/ void bl1_plat_arch_setup(void); void bl2_plat_arch_setup(void); void bl31_plat_arch_setup(void); int platform_setup_pm(const struct plat_pm_ops **plat_ops); unsigned int platform_get_core_pos(unsigned long mpidr); void configure_mmu_el1(unsigned long total_base, unsigned long total_size, unsigned long ro_start, unsigned long ro_limit, unsigned long coh_start, unsigned long coh_limit); void configure_mmu_el3(unsigned long total_base, unsigned long total_size, unsigned long ro_start, unsigned long ro_limit, unsigned long coh_start, unsigned long coh_limit); void plat_report_exception(unsigned long type); unsigned long plat_get_ns_image_entrypoint(void); unsigned long platform_get_stack(unsigned long mpidr); uint64_t plat_get_syscnt_freq(void); /* Declarations for plat_gic.c */ uint32_t ic_get_pending_interrupt_id(void); uint32_t ic_get_pending_interrupt_type(void); uint32_t ic_acknowledge_interrupt(void); uint32_t ic_get_interrupt_type(uint32_t id); void ic_end_of_interrupt(uint32_t id); void gic_cpuif_deactivate(unsigned int gicc_base); void gic_cpuif_setup(unsigned int gicc_base); void gic_pcpu_distif_setup(unsigned int gicd_base); void gic_setup(void); uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state); /* Declarations for plat_topology.c */ int plat_setup_topology(void); int plat_get_max_afflvl(void); unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr); unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr); /* Declarations for plat_io_storage.c */ void io_setup(void); int plat_get_image_source(const char *image_name, uintptr_t *dev_handle, uintptr_t *image_spec); /* * Before calling this function BL2 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL2 and set SPSR and security state. * On Juno we are only setting the security state, entrypoint */ void bl1_plat_set_bl2_ep_info(struct image_info *image, struct entry_point_info *ep); /* * Before calling this function BL3-1 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL3-1 and set SPSR and security state. * On Juno we are only setting the security state, entrypoint */ void bl2_plat_set_bl31_ep_info(struct image_info *image, struct entry_point_info *ep); /* * Before calling this function BL3-2 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL3-2 and set SPSR and security state. * On Juno we are only setting the security state, entrypoint */ void bl2_plat_set_bl32_ep_info(struct image_info *image, struct entry_point_info *ep); /* * Before calling this function BL3-3 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL3-3 and set SPSR and security state. * On Juno we are only setting the security state, entrypoint */ void bl2_plat_set_bl33_ep_info(struct image_info *image, struct entry_point_info *ep); /* Gets the memory layout for BL3-2 */ void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); /* Gets the memory layout for BL3-3 */ void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); #endif /* __JUNO_PRIVATE_H__ */ arm-trusted-firmware-1.0-aw-6/plat/juno/mhu.c000066400000000000000000000060271322600646200210610ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "juno_def.h" #include "mhu.h" /* SCP MHU secure channel registers */ #define SCP_INTR_S_STAT 0x200 #define SCP_INTR_S_SET 0x208 #define SCP_INTR_S_CLEAR 0x210 /* CPU MHU secure channel registers */ #define CPU_INTR_S_STAT 0x300 #define CPU_INTR_S_SET 0x308 #define CPU_INTR_S_CLEAR 0x310 static bakery_lock_t mhu_secure_lock __attribute__ ((section("tzfw_coherent_mem"))); void mhu_secure_message_start(void) { bakery_lock_get(&mhu_secure_lock); /* Make sure any previous command has finished */ while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) != 0) ; } void mhu_secure_message_send(uint32_t command) { /* Send command to SCP and wait for it to pick it up */ mmio_write_32(MHU_BASE + CPU_INTR_S_SET, command); while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) != 0) ; } uint32_t mhu_secure_message_wait(void) { /* Wait for response from SCP */ uint32_t response; while (!(response = mmio_read_32(MHU_BASE + SCP_INTR_S_STAT))) ; return response; } void mhu_secure_message_end(void) { /* Clear any response we got by writing all ones to the CLEAR register */ mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 0xffffffffu); bakery_lock_release(&mhu_secure_lock); } void mhu_secure_init(void) { bakery_lock_init(&mhu_secure_lock); /* * Clear the CPU's INTR register to make sure we don't see a stale * or garbage value and think it's a message we've already sent. */ mmio_write_32(MHU_BASE + CPU_INTR_S_CLEAR, 0xffffffffu); } arm-trusted-firmware-1.0-aw-6/plat/juno/mhu.h000066400000000000000000000035101322600646200210600ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __MHU_H__ #define __MHU_H__ #include extern void mhu_secure_message_start(void); extern void mhu_secure_message_send(uint32_t command); extern uint32_t mhu_secure_message_wait(void); extern void mhu_secure_message_end(void); extern void mhu_secure_init(void); #endif /* __MHU_H__ */ arm-trusted-firmware-1.0-aw-6/plat/juno/plat-tsp.ld.S000066400000000000000000000031361322600646200224100ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ ASSERT(__BL32_END__ <= BL2_BASE, "BL3-2 image overlaps BL2 image.") arm-trusted-firmware-1.0-aw-6/plat/juno/plat_gic.c000066400000000000000000000237721322600646200220600ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include "juno_def.h" #include "juno_private.h" /* Value used to initialise Non-Secure irq priorities four at a time */ #define DEFAULT_NS_PRIORITY_X4 \ (GIC_HIGHEST_NS_PRIORITY | \ (GIC_HIGHEST_NS_PRIORITY << 8) | \ (GIC_HIGHEST_NS_PRIORITY << 16) | \ (GIC_HIGHEST_NS_PRIORITY << 24)) /******************************************************************************* * Enable secure interrupts and use FIQs to route them. Disable legacy bypass * and set the priority mask register to allow all interrupts to trickle in. ******************************************************************************/ void gic_cpuif_setup(unsigned int gicc_base) { unsigned int val; gicc_write_pmr(gicc_base, GIC_PRI_MASK); val = ENABLE_GRP0 | FIQ_EN; val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0; val |= FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; gicc_write_ctlr(gicc_base, val); } /******************************************************************************* * Place the cpu interface in a state where it can never make a cpu exit wfi as * as result of an asserted interrupt. This is critical for powering down a cpu ******************************************************************************/ void gic_cpuif_deactivate(unsigned int gicc_base) { unsigned int val; /* Disable secure, non-secure interrupts and disable their bypass */ val = gicc_read_ctlr(gicc_base); val &= ~(ENABLE_GRP0 | ENABLE_GRP1); val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; gicc_write_ctlr(gicc_base, val); } static void gic_set_secure(unsigned int gicd_base, unsigned id) { /* Set interrupt as Group 0 */ gicd_clr_igroupr(gicd_base, id); /* Set priority to max */ gicd_set_ipriorityr(gicd_base, id, GIC_HIGHEST_SEC_PRIORITY); } /******************************************************************************* * Per cpu gic distributor setup which will be done by all cpus after a cold * boot/hotplug. This marks out the secure interrupts & enables them. ******************************************************************************/ void gic_pcpu_distif_setup(unsigned int gicd_base) { unsigned i; /* Mark all 32 PPI interrupts as Group 1 (non-secure) */ mmio_write_32(gicd_base + GICD_IGROUPR, 0xffffffffu); /* Setup PPI priorities doing four at a time */ for (i = 0; i < 32; i += 4) mmio_write_32(gicd_base + GICD_IPRIORITYR + i, DEFAULT_NS_PRIORITY_X4); /* Configure those PPIs we want as secure, and enable them. */ static const char sec_irq[] = { IRQ_SEC_PHY_TIMER, IRQ_SEC_SGI_0, IRQ_SEC_SGI_1, IRQ_SEC_SGI_2, IRQ_SEC_SGI_3, IRQ_SEC_SGI_4, IRQ_SEC_SGI_5, IRQ_SEC_SGI_6, IRQ_SEC_SGI_7 }; for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++) { gic_set_secure(gicd_base, sec_irq[i]); gicd_set_isenabler(gicd_base, sec_irq[i]); } } /******************************************************************************* * Global gic distributor setup which will be done by the primary cpu after a * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It * then enables the secure GIC distributor interface. ******************************************************************************/ static void gic_distif_setup(unsigned int gicd_base) { unsigned int i, ctlr; const unsigned int ITLinesNumber = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; /* Disable the distributor before going further */ ctlr = gicd_read_ctlr(gicd_base); ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1); gicd_write_ctlr(gicd_base, ctlr); /* Mark all lines of SPIs as Group 1 (non-secure) */ for (i = 0; i < ITLinesNumber; i++) mmio_write_32(gicd_base + GICD_IGROUPR + 4 + i * 4, 0xffffffffu); /* Setup SPI priorities doing four at a time */ for (i = 0; i < ITLinesNumber * 32; i += 4) mmio_write_32(gicd_base + GICD_IPRIORITYR + 32 + i, DEFAULT_NS_PRIORITY_X4); /* Configure the SPIs we want as secure */ static const char sec_irq[] = { IRQ_MHU, IRQ_GPU_SMMU_0, IRQ_GPU_SMMU_1, IRQ_ETR_SMMU, IRQ_TZC400, IRQ_TZ_WDOG }; for (i = 0; i < sizeof(sec_irq) / sizeof(sec_irq[0]); i++) gic_set_secure(gicd_base, sec_irq[i]); /* Route watchdog interrupt to this CPU and enable it. */ gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG, platform_get_core_pos(read_mpidr())); gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG); /* Now setup the PPIs */ gic_pcpu_distif_setup(gicd_base); /* Enable Group 0 (secure) interrupts */ gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0); } void gic_setup(void) { gic_cpuif_setup(GICC_BASE); gic_distif_setup(GICD_BASE); } /******************************************************************************* * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. * The interrupt controller knows which pin/line it uses to signal a type of * interrupt. The platform knows which interrupt controller type is being used * in a particular security state e.g. with an ARM GIC, normal world could use * the GICv2 features while the secure world could use GICv3 features and vice * versa. * This function is exported by the platform to let the interrupt management * framework determine for a type of interrupt and security state, which line * should be used in the SCR_EL3 to control its routing to EL3. The interrupt * line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3. ******************************************************************************/ uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) { assert(type == INTR_TYPE_S_EL1 || type == INTR_TYPE_EL3 || type == INTR_TYPE_NS); assert(sec_state_is_valid(security_state)); /* * We ignore the security state parameter because Juno is GICv2 only * so both normal and secure worlds are using ARM GICv2. */ return gicv2_interrupt_type_to_line(GICC_BASE, type); } /******************************************************************************* * This function returns the type of the highest priority pending interrupt at * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no * interrupt pending. ******************************************************************************/ uint32_t plat_ic_get_pending_interrupt_type(void) { uint32_t id; id = gicc_read_hppir(GICC_BASE); /* Assume that all secure interrupts are S-EL1 interrupts */ if (id < 1022) return INTR_TYPE_S_EL1; if (id == GIC_SPURIOUS_INTERRUPT) return INTR_TYPE_INVAL; return INTR_TYPE_NS; } /******************************************************************************* * This function returns the id of the highest priority pending interrupt at * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no * interrupt pending. ******************************************************************************/ uint32_t plat_ic_get_pending_interrupt_id(void) { uint32_t id; id = gicc_read_hppir(GICC_BASE); if (id < 1022) return id; if (id == 1023) return INTR_ID_UNAVAILABLE; /* * Find out which non-secure interrupt it is under the assumption that * the GICC_CTLR.AckCtl bit is 0. */ return gicc_read_ahppir(GICC_BASE); } /******************************************************************************* * This functions reads the GIC cpu interface Interrupt Acknowledge register * to start handling the pending interrupt. It returns the contents of the IAR. ******************************************************************************/ uint32_t plat_ic_acknowledge_interrupt(void) { return gicc_read_IAR(GICC_BASE); } /******************************************************************************* * This functions writes the GIC cpu interface End Of Interrupt register with * the passed value to finish handling the active interrupt ******************************************************************************/ void plat_ic_end_of_interrupt(uint32_t id) { gicc_write_EOIR(GICC_BASE, id); } /******************************************************************************* * This function returns the type of the interrupt id depending upon the group * this interrupt has been configured under by the interrupt controller i.e. * group0 or group1. ******************************************************************************/ uint32_t plat_ic_get_interrupt_type(uint32_t id) { uint32_t group; group = gicd_get_igroupr(GICD_BASE, id); /* Assume that all secure interrupts are S-EL1 interrupts */ if (group == GRP0) return INTR_TYPE_S_EL1; else return INTR_TYPE_NS; } arm-trusted-firmware-1.0-aw-6/plat/juno/plat_io_storage.c000066400000000000000000000126521322600646200234440ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include /* For FOPEN_MODE_... */ #include /* IO devices */ static const io_dev_connector_t *fip_dev_con; static uintptr_t fip_dev_spec; static uintptr_t fip_dev_handle; static const io_dev_connector_t *memmap_dev_con; static uintptr_t memmap_dev_spec; static uintptr_t memmap_init_params; static uintptr_t memmap_dev_handle; static const io_block_spec_t fip_block_spec = { .offset = FLASH_BASE, .length = FLASH_SIZE }; static const io_file_spec_t bl2_file_spec = { .path = BL2_IMAGE_NAME, .mode = FOPEN_MODE_RB }; static const io_file_spec_t bl30_file_spec = { .path = BL30_IMAGE_NAME, .mode = FOPEN_MODE_RB }; static const io_file_spec_t bl31_file_spec = { .path = BL31_IMAGE_NAME, .mode = FOPEN_MODE_RB }; static const io_file_spec_t bl32_file_spec = { .path = BL32_IMAGE_NAME, .mode = FOPEN_MODE_RB }; static const io_file_spec_t bl33_file_spec = { .path = BL33_IMAGE_NAME, .mode = FOPEN_MODE_RB }; static int open_fip(const uintptr_t spec); static int open_memmap(const uintptr_t spec); struct plat_io_policy { const char *image_name; uintptr_t *dev_handle; uintptr_t image_spec; int (*check)(const uintptr_t spec); }; static const struct plat_io_policy policies[] = { { FIP_IMAGE_NAME, &memmap_dev_handle, (uintptr_t)&fip_block_spec, open_memmap }, { BL2_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl2_file_spec, open_fip }, { BL30_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl30_file_spec, open_fip }, { BL31_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl31_file_spec, open_fip }, { BL32_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl32_file_spec, open_fip }, { BL33_IMAGE_NAME, &fip_dev_handle, (uintptr_t)&bl33_file_spec, open_fip }, { 0, 0, 0 } }; static int open_fip(const uintptr_t spec) { int result = IO_FAIL; /* See if a Firmware Image Package is available */ result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_NAME); if (result == IO_SUCCESS) { INFO("Using FIP\n"); /*TODO: Check image defined in spec is present in FIP. */ } return result; } static int open_memmap(const uintptr_t spec) { int result = IO_FAIL; uintptr_t local_image_handle; result = io_dev_init(memmap_dev_handle, memmap_init_params); if (result == IO_SUCCESS) { result = io_open(memmap_dev_handle, spec, &local_image_handle); if (result == IO_SUCCESS) { /* INFO("Using Memmap IO\n"); */ io_close(local_image_handle); } } return result; } void io_setup(void) { int io_result = IO_FAIL; /* Register the IO devices on this platform */ io_result = register_io_dev_fip(&fip_dev_con); assert(io_result == IO_SUCCESS); io_result = register_io_dev_memmap(&memmap_dev_con); assert(io_result == IO_SUCCESS); /* Open connections to devices and cache the handles */ io_result = io_dev_open(fip_dev_con, fip_dev_spec, &fip_dev_handle); assert(io_result == IO_SUCCESS); io_result = io_dev_open(memmap_dev_con, memmap_dev_spec, &memmap_dev_handle); assert(io_result == IO_SUCCESS); /* Ignore improbable errors in release builds */ (void)io_result; } /* Return an IO device handle and specification which can be used to access * an image. Use this to enforce platform load policy */ int plat_get_image_source(const char *image_name, uintptr_t *dev_handle, uintptr_t *image_spec) { int result = IO_FAIL; const struct plat_io_policy *policy; if ((image_name != NULL) && (dev_handle != NULL) && (image_spec != NULL)) { policy = policies; while (policy->image_name != NULL) { if (strcmp(policy->image_name, image_name) == 0) { result = policy->check(policy->image_spec); if (result == IO_SUCCESS) { *image_spec = policy->image_spec; *dev_handle = *(policy->dev_handle); break; } } policy++; } } else { result = IO_FAIL; } return result; } arm-trusted-firmware-1.0-aw-6/plat/juno/plat_pm.c000066400000000000000000000253661322600646200217330ustar00rootroot00000000000000/* * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include "juno_def.h" #include "juno_private.h" #include "scpi.h" /******************************************************************************* * Private Juno function to program the mailbox for a cpu before it is released * from reset. ******************************************************************************/ static void juno_program_mailbox(uint64_t mpidr, uint64_t address) { uint64_t linear_id; uint64_t mbox; linear_id = platform_get_core_pos(mpidr); mbox = TRUSTED_MAILBOXES_BASE + (linear_id << TRUSTED_MAILBOX_SHIFT); *((uint64_t *) mbox) = address; flush_dcache_range(mbox, sizeof(mbox)); } /******************************************************************************* * Private Juno function which is used to determine if any platform actions * should be performed for the specified affinity instance given its * state. Nothing needs to be done if the 'state' is not off or if this is not * the highest affinity level which will enter the 'state'. ******************************************************************************/ static int32_t juno_do_plat_actions(uint32_t afflvl, uint32_t state) { uint32_t max_phys_off_afflvl; assert(afflvl <= MPIDR_AFFLVL1); if (state != PSCI_STATE_OFF) return -EAGAIN; /* * Find the highest affinity level which will be suspended and postpone * all the platform specific actions until that level is hit. */ max_phys_off_afflvl = psci_get_max_phys_off_afflvl(); assert(max_phys_off_afflvl != PSCI_INVALID_DATA); assert(psci_get_suspend_afflvl() >= max_phys_off_afflvl); if (afflvl != max_phys_off_afflvl) return -EAGAIN; return 0; } /******************************************************************************* * Juno handler called when an affinity instance is about to be turned on. The * level and mpidr determine the affinity instance. ******************************************************************************/ int32_t juno_affinst_on(uint64_t mpidr, uint64_t sec_entrypoint, uint64_t ns_entrypoint, uint32_t afflvl, uint32_t state) { /* * SCP takes care of powering up higher affinity levels so we * only need to care about level 0 */ if (afflvl != MPIDR_AFFLVL0) return PSCI_E_SUCCESS; /* * Setup mailbox with address for CPU entrypoint when it next powers up */ juno_program_mailbox(mpidr, sec_entrypoint); scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on, scpi_power_on); return PSCI_E_SUCCESS; } /******************************************************************************* * Juno handler called when an affinity instance has just been powered on after * being turned off earlier. The level and mpidr determine the affinity * instance. The 'state' arg. allows the platform to decide whether the cluster * was turned off prior to wakeup and do what's necessary to setup it up * correctly. ******************************************************************************/ int32_t juno_affinst_on_finish(uint64_t mpidr, uint32_t afflvl, uint32_t state) { /* Determine if any platform actions need to be executed. */ if (juno_do_plat_actions(afflvl, state) == -EAGAIN) return PSCI_E_SUCCESS; /* * Perform the common cluster specific operations i.e enable coherency * if this cluster was off. */ if (afflvl != MPIDR_AFFLVL0) cci_enable_cluster_coherency(mpidr); /* Enable the gic cpu interface */ gic_cpuif_setup(GICC_BASE); /* Juno todo: Is this setup only needed after a cold boot? */ gic_pcpu_distif_setup(GICD_BASE); /* Clear the mailbox for this cpu. */ juno_program_mailbox(mpidr, 0); return PSCI_E_SUCCESS; } /******************************************************************************* * Common function called while turning a cpu off or suspending it. It is called * from juno_off() or juno_suspend() when these functions in turn are called for * the highest affinity level which will be powered down. It performs the * actions common to the OFF and SUSPEND calls. ******************************************************************************/ static int32_t juno_power_down_common(uint32_t afflvl) { uint32_t cluster_state = scpi_power_on; /* Prevent interrupts from spuriously waking up this cpu */ gic_cpuif_deactivate(GICC_BASE); /* Cluster is to be turned off, so disable coherency */ if (afflvl > MPIDR_AFFLVL0) { cci_disable_cluster_coherency(read_mpidr_el1()); cluster_state = scpi_power_off; } /* * Ask the SCP to power down the appropriate components depending upon * their state. */ scpi_set_css_power_state(read_mpidr_el1(), scpi_power_off, cluster_state, scpi_power_on); return PSCI_E_SUCCESS; } /******************************************************************************* * Handler called when an affinity instance is about to be turned off. The * level and mpidr determine the affinity instance. The 'state' arg. allows the * platform to decide whether the cluster is being turned off and take * appropriate actions. * * CAUTION: There is no guarantee that caches will remain turned on across calls * to this function as each affinity level is dealt with. So do not write & read * global variables across calls. It will be wise to do flush a write to the * global to prevent unpredictable results. ******************************************************************************/ static int32_t juno_affinst_off(uint64_t mpidr, uint32_t afflvl, uint32_t state) { /* Determine if any platform actions need to be executed */ if (juno_do_plat_actions(afflvl, state) == -EAGAIN) return PSCI_E_SUCCESS; return juno_power_down_common(afflvl); } /******************************************************************************* * Handler called when an affinity instance is about to be suspended. The * level and mpidr determine the affinity instance. The 'state' arg. allows the * platform to decide whether the cluster is being turned off and take apt * actions. The 'sec_entrypoint' determines the address in BL3-1 from where * execution should resume. * * CAUTION: There is no guarantee that caches will remain turned on across calls * to this function as each affinity level is dealt with. So do not write & read * global variables across calls. It will be wise to do flush a write to the * global to prevent unpredictable results. ******************************************************************************/ static int32_t juno_affinst_suspend(uint64_t mpidr, uint64_t sec_entrypoint, uint64_t ns_entrypoint, uint32_t afflvl, uint32_t state) { /* Determine if any platform actions need to be executed */ if (juno_do_plat_actions(afflvl, state) == -EAGAIN) return PSCI_E_SUCCESS; /* * Setup mailbox with address for CPU entrypoint when it next powers up. */ juno_program_mailbox(mpidr, sec_entrypoint); return juno_power_down_common(afflvl); } /******************************************************************************* * Juno handler called when an affinity instance has just been powered on after * having been suspended earlier. The level and mpidr determine the affinity * instance. * TODO: At the moment we reuse the on finisher and reinitialize the secure * context. Need to implement a separate suspend finisher. ******************************************************************************/ static int32_t juno_affinst_suspend_finish(uint64_t mpidr, uint32_t afflvl, uint32_t state) { return juno_affinst_on_finish(mpidr, afflvl, state); } /******************************************************************************* * Juno handlers to shutdown/reboot the system ******************************************************************************/ static void __dead2 juno_system_off(void) { uint32_t response; /* Send the power down request to the SCP */ response = scpi_sys_power_state(scpi_system_shutdown); if (response != SCP_OK) { ERROR("Juno System Off: SCP error %u.\n", response); panic(); } wfi(); ERROR("Juno System Off: operation not handled.\n"); panic(); } static void __dead2 juno_system_reset(void) { uint32_t response; /* Send the system reset request to the SCP */ response = scpi_sys_power_state(scpi_system_reboot); if (response != SCP_OK) { ERROR("Juno System Reset: SCP error %u.\n", response); panic(); } wfi(); ERROR("Juno System Reset: operation not handled.\n"); panic(); } /******************************************************************************* * Export the platform handlers to enable psci to invoke them ******************************************************************************/ static const plat_pm_ops_t juno_ops = { .affinst_on = juno_affinst_on, .affinst_on_finish = juno_affinst_on_finish, .affinst_off = juno_affinst_off, .affinst_suspend = juno_affinst_suspend, .affinst_suspend_finish = juno_affinst_suspend_finish, .system_off = juno_system_off, .system_reset = juno_system_reset }; /******************************************************************************* * Export the platform specific power ops. ******************************************************************************/ int32_t platform_setup_pm(const plat_pm_ops_t **plat_ops) { *plat_ops = &juno_ops; return 0; } arm-trusted-firmware-1.0-aw-6/plat/juno/plat_topology.c000066400000000000000000000043031322600646200231570ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr) { /* Report 1 (absent) instance at levels higher that the cluster level */ if (aff_lvl > MPIDR_AFFLVL1) return 1; if (aff_lvl == MPIDR_AFFLVL1) return 2; /* We have two clusters */ return mpidr & 0x100 ? 4 : 2; /* 4 cpus in cluster 1, 2 in cluster 0 */ } unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr) { return aff_lvl <= MPIDR_AFFLVL1 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; } int plat_get_max_afflvl() { return MPIDR_AFFLVL1; } int plat_setup_topology() { /* Juno todo: Make topology configurable via SCC */ return 0; } arm-trusted-firmware-1.0-aw-6/plat/juno/platform.mk000066400000000000000000000061161322600646200223000ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # PLAT_INCLUDES := -Iplat/juno/include/ PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/pl011_console.S \ drivers/io/io_fip.c \ drivers/io/io_memmap.c \ drivers/io/io_storage.c \ lib/aarch64/xlat_tables.c \ plat/common/aarch64/plat_common.c \ plat/juno/plat_io_storage.c BL1_SOURCES += drivers/arm/cci400/cci400.c \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ plat/common/aarch64/platform_up_stack.S \ plat/juno/bl1_plat_setup.c \ plat/juno/aarch64/bl1_plat_helpers.S \ plat/juno/aarch64/plat_helpers.S \ plat/juno/aarch64/juno_common.c BL2_SOURCES += lib/locks/bakery/bakery_lock.c \ plat/common/aarch64/platform_up_stack.S \ plat/juno/bl2_plat_setup.c \ plat/juno/mhu.c \ plat/juno/aarch64/plat_helpers.S \ plat/juno/aarch64/juno_common.c \ plat/juno/scp_bootloader.c \ plat/juno/scpi.c BL31_SOURCES += drivers/arm/cci400/cci400.c \ drivers/arm/gic/gic_v2.c \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ plat/common/aarch64/platform_mp_stack.S \ plat/juno/bl31_plat_setup.c \ plat/juno/mhu.c \ plat/juno/aarch64/plat_helpers.S \ plat/juno/aarch64/juno_common.c \ plat/juno/plat_pm.c \ plat/juno/plat_topology.c \ plat/juno/plat_gic.c \ plat/juno/scpi.c ifneq (${RESET_TO_BL31},0) $(error "Using BL3-1 as the reset vector is not supported on Juno. \ Please set RESET_TO_BL31 to 0.") endif NEED_BL30 := yes # Enable workarounds for selected Cortex-A57 erratas. ERRATA_A57_806969 := 1 ERRATA_A57_813420 := 1 arm-trusted-firmware-1.0-aw-6/plat/juno/scp_bootloader.c000066400000000000000000000105651322600646200232710ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include "juno_def.h" #include "mhu.h" #include "scp_bootloader.h" #include "scpi.h" /* Boot commands sent from AP -> SCP */ #define BOOT_CMD_START 0x01 #define BOOT_CMD_DATA 0x02 typedef struct { uint32_t image_size; } cmd_start_payload; typedef struct { uint32_t sequence_num; uint32_t offset; uint32_t size; } cmd_data_payload; #define BOOT_DATA_MAX_SIZE 0x1000 /* Boot commands sent from SCP -> AP */ #define BOOT_CMD_ACK 0x03 #define BOOT_CMD_NACK 0x04 typedef struct { uint32_t sequence_num; } cmd_ack_payload; /* * Unlike the runtime protocol, the boot protocol uses the same memory region * for both AP -> SCP and SCP -> AP transfers; define the address of this... */ static void * const cmd_payload = (void *)(MHU_SECURE_BASE + 0x0080); static void *scp_boot_message_start(void) { mhu_secure_message_start(); return cmd_payload; } static void scp_boot_message_send(unsigned command, size_t size) { /* Make sure payload can be seen by SCP */ if (MHU_PAYLOAD_CACHED) flush_dcache_range((unsigned long)cmd_payload, size); /* Send command to SCP */ mhu_secure_message_send(command | (size << 8)); } static uint32_t scp_boot_message_wait(size_t size) { uint32_t response = mhu_secure_message_wait(); /* Make sure we see the reply from the SCP and not any stale data */ if (MHU_PAYLOAD_CACHED) inv_dcache_range((unsigned long)cmd_payload, size); return response & 0xff; } static void scp_boot_message_end(void) { mhu_secure_message_end(); } static int transfer_block(uint32_t sequence_num, uint32_t offset, uint32_t size) { cmd_data_payload *cmd_data = scp_boot_message_start(); cmd_data->sequence_num = sequence_num; cmd_data->offset = offset; cmd_data->size = size; scp_boot_message_send(BOOT_CMD_DATA, sizeof(*cmd_data)); cmd_ack_payload *cmd_ack = cmd_payload; int ok = scp_boot_message_wait(sizeof(*cmd_ack)) == BOOT_CMD_ACK && cmd_ack->sequence_num == sequence_num; scp_boot_message_end(); return ok; } int scp_bootloader_transfer(void *image, unsigned int image_size) { uintptr_t offset = (uintptr_t)image - MHU_SECURE_BASE; uintptr_t end = offset + image_size; uint32_t response; mhu_secure_init(); /* Initiate communications with SCP */ do { cmd_start_payload *cmd_start = scp_boot_message_start(); cmd_start->image_size = image_size; scp_boot_message_send(BOOT_CMD_START, sizeof(*cmd_start)); response = scp_boot_message_wait(0); scp_boot_message_end(); } while (response != BOOT_CMD_ACK); /* Transfer image to SCP a block at a time */ uint32_t sequence_num = 1; size_t size; while ((size = end - offset) != 0) { if (size > BOOT_DATA_MAX_SIZE) size = BOOT_DATA_MAX_SIZE; while (!transfer_block(sequence_num, offset, size)) ; /* Retry forever */ offset += size; sequence_num++; } /* Wait for SCP to signal it's ready */ return scpi_wait_ready(); } arm-trusted-firmware-1.0-aw-6/plat/juno/scp_bootloader.h000066400000000000000000000032341322600646200232710ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SCP_BOOTLOADER_H__ #define __SCP_BOOTLOADER_H__ int scp_bootloader_transfer(void *image, unsigned int image_size); #endif arm-trusted-firmware-1.0-aw-6/plat/juno/scpi.c000066400000000000000000000105711322600646200212250ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include "juno_def.h" #include "mhu.h" #include "scpi.h" #define MHU_SECURE_SCP_TO_AP_PAYLOAD (MHU_SECURE_BASE+0x0080) #define MHU_SECURE_AP_TO_SCP_PAYLOAD (MHU_SECURE_BASE+0x0280) #define SIZE_SHIFT 20 /* Bit position for size value in MHU header */ #define SIZE_MASK 0x1ff /* Mask to extract size value in MHU header*/ void *scpi_secure_message_start(void) { mhu_secure_message_start(); /* Return address of payload area. */ return (void *)MHU_SECURE_AP_TO_SCP_PAYLOAD; } void scpi_secure_message_send(unsigned command, size_t size) { /* Make sure payload can be seen by SCP */ if (MHU_PAYLOAD_CACHED) flush_dcache_range(MHU_SECURE_AP_TO_SCP_PAYLOAD, size); mhu_secure_message_send(command | (size << SIZE_SHIFT)); } unsigned scpi_secure_message_receive(void **message_out, size_t *size_out) { uint32_t response = mhu_secure_message_wait(); /* Get size of payload */ size_t size = (response >> SIZE_SHIFT) & SIZE_MASK; /* Clear size from response */ response &= ~(SIZE_MASK << SIZE_SHIFT); /* Make sure we don't read stale data */ if (MHU_PAYLOAD_CACHED) inv_dcache_range(MHU_SECURE_SCP_TO_AP_PAYLOAD, size); if (size_out) *size_out = size; if (message_out) *message_out = (void *)MHU_SECURE_SCP_TO_AP_PAYLOAD; return response; } void scpi_secure_message_end(void) { mhu_secure_message_end(); } static void scpi_secure_send32(unsigned command, uint32_t message) { *(__typeof__(message) *)scpi_secure_message_start() = message; scpi_secure_message_send(command, sizeof(message)); scpi_secure_message_end(); } int scpi_wait_ready(void) { /* Get a message from the SCP */ scpi_secure_message_start(); size_t size; unsigned command = scpi_secure_message_receive(NULL, &size); scpi_secure_message_end(); /* We are expecting 'SCP Ready', produce correct error if it's not */ scpi_status_t response = SCP_OK; if (command != SCPI_CMD_SCP_READY) response = SCP_E_SUPPORT; else if (size != 0) response = SCP_E_SIZE; /* Send our response back to SCP */ scpi_secure_send32(command, response); return response == SCP_OK ? 0 : -1; } void scpi_set_css_power_state(unsigned mpidr, scpi_power_state_t cpu_state, scpi_power_state_t cluster_state, scpi_power_state_t css_state) { uint32_t state = mpidr & 0x0f; /* CPU ID */ state |= (mpidr & 0xf00) >> 4; /* Cluster ID */ state |= cpu_state << 8; state |= cluster_state << 12; state |= css_state << 16; scpi_secure_send32(SCPI_CMD_SET_CSS_POWER_STATE, state); } uint32_t scpi_sys_power_state(scpi_system_state_t system_state) { uint32_t *response; size_t size; uint8_t state = system_state & 0xff; /* Send the command */ *(__typeof__(state) *)scpi_secure_message_start() = state; scpi_secure_message_send(SCPI_CMD_SYS_POWER_STATE, sizeof(state)); scpi_secure_message_receive((void *)&response, &size); scpi_secure_message_end(); return *response; } arm-trusted-firmware-1.0-aw-6/plat/juno/scpi.h000066400000000000000000000057251322600646200212370ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SCPI_H__ #define __SCPI_H__ #include #include extern void *scpi_secure_message_start(void); extern void scpi_secure_message_send(unsigned command, size_t size); extern unsigned scpi_secure_message_receive(void **message_out, size_t *size_out); extern void scpi_secure_message_end(void); enum { SCP_OK = 0, /* Success */ SCP_E_PARAM, /* Invalid parameter(s) */ SCP_E_ALIGN, /* Invalid alignment */ SCP_E_SIZE, /* Invalid size */ SCP_E_HANDLER, /* Invalid handler or callback */ SCP_E_ACCESS, /* Invalid access or permission denied */ SCP_E_RANGE, /* Value out of range */ SCP_E_TIMEOUT, /* Time out has ocurred */ SCP_E_NOMEM, /* Invalid memory area or pointer */ SCP_E_PWRSTATE, /* Invalid power state */ SCP_E_SUPPORT, /* Feature not supported or disabled */ }; typedef uint32_t scpi_status_t; typedef enum { SCPI_CMD_SCP_READY = 0x01, SCPI_CMD_SET_CSS_POWER_STATE = 0x04, SCPI_CMD_SYS_POWER_STATE = 0x08 } scpi_command_t; typedef enum { scpi_power_on = 0, scpi_power_retention = 1, scpi_power_off = 3, } scpi_power_state_t; typedef enum { scpi_system_shutdown = 0, scpi_system_reboot = 1, scpi_system_reset = 2 } scpi_system_state_t; extern int scpi_wait_ready(void); extern void scpi_set_css_power_state(unsigned mpidr, scpi_power_state_t cpu_state, scpi_power_state_t cluster_state, scpi_power_state_t css_state); uint32_t scpi_sys_power_state(scpi_system_state_t system_state); #endif /* __SCPI_H__ */ arm-trusted-firmware-1.0-aw-6/plat/juno/tsp/000077500000000000000000000000001322600646200207255ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/juno/tsp/tsp-juno.mk000066400000000000000000000034151322600646200230400ustar00rootroot00000000000000# # Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # # TSP source files specific to Juno platform BL32_SOURCES += drivers/arm/gic/gic_v2.c \ plat/common/aarch64/platform_mp_stack.S \ plat/juno/aarch64/juno_common.c \ plat/juno/aarch64/plat_helpers.S \ plat/juno/tsp/tsp_plat_setup.c \ plat/juno/plat_gic.c arm-trusted-firmware-1.0-aw-6/plat/juno/tsp/tsp_plat_setup.c000066400000000000000000000100461322600646200241400ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "../juno_def.h" #include "../juno_private.h" /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __RO_END__; extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ #define BL32_RO_BASE (unsigned long)(&__RO_START__) #define BL32_RO_LIMIT (unsigned long)(&__RO_END__) /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to * page-aligned addresses. */ #define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) /******************************************************************************* * Initialize the UART ******************************************************************************/ void tsp_early_platform_setup(void) { /* * Initialize a different console than already in use to display * messages from TSP */ console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); } /******************************************************************************* * Perform platform specific setup placeholder ******************************************************************************/ void tsp_platform_setup(void) { } /******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this only intializes the MMU ******************************************************************************/ void tsp_plat_arch_setup(void) { configure_mmu_el1(BL32_RO_BASE, BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE, BL32_RO_BASE, BL32_RO_LIMIT, BL32_COHERENT_RAM_BASE, BL32_COHERENT_RAM_LIMIT); } arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/000077500000000000000000000000001322600646200210005ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/aarch64/000077500000000000000000000000001322600646200222305ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/aarch64/plat_helpers.S000066400000000000000000000055131322600646200250420ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include "../sunxi_def.h" .globl plat_crash_console_init .globl plat_crash_console_putc .globl platform_mem_init .globl platform_smp_init /* ----------------------------------------------------- * void platform_mem_init(void); * * We don't need to carry out any memory initialization. * ----------------------------------------------------- */ func platform_mem_init ret func platform_smp_init mrs x0, ACTLR_EL3 orr x0, x0, #(1 << 1) // Set CPUECTLR_EL1 access control bit msr ACTLR_EL3, x0 mrs x0, ACTLR_EL2 orr x0, x0, #(1 << 1) // Set CPUECTLR_EL1 access control bit msr ACTLR_EL2, x0 mrs x0, S3_1_c15_c2_1 // Read CPUECTLR_EL1 orr x0, x0, #(1 << 6) // Set the SMPEN bit msr S3_1_c15_c2_1, x0 // Write CPUECTLR_EL1 mov x0, #0x0 msr cntvoff_el2, x0 ret #define UART_TX 0 /* Out: Transmit buffer */ #define UART_LSR 5 /* In: Line Status Register */ #define UART_LSR_TEMT_BIT 6 /* Transmitter empty */ /* Use UART0 both for the normal console and for the crash console as well. */ plat_crash_console_putc: func console_core_putc ldr x1, =SUNXI_UART0_BASE 1: ldr w2, [x1, #(UART_LSR * 4)] tbz w2, #UART_LSR_TEMT_BIT, 1b str w0, [x1, #0] ret /* nothing to do here, just return 1 to indicate success */ func plat_crash_console_init mov w0, #1 ret arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/aarch64/sunxi_common.c000066400000000000000000000132211322600646200251110ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include "../sunxi_def.h" #include "../sunxi_private.h" /******************************************************************************* * plat_config holds the characteristics of the differences between the three * FVP platforms (Base, A53_A57 & Foundation). It will be populated during cold * boot at each boot stage by the primary before enabling the MMU (to allow cci * configuration) & used thereafter. Each BL will have its own copy to allow * independent operation. ******************************************************************************/ plat_config_t plat_config; /* * Table of regions to map using the MMU. * This doesn't include TZRAM as the 'mem_layout' argument passed to * configure_mmu_elx() will give the available subset of that, */ const mmap_region_t sunxi_mmap[] = { // SRAM regions { 0x0010000, 0x0010000, 0x0030000, MT_DEVICE | MT_RW | MT_NS }, // MMI/O region used by peripherals from 0x100.0000 to 0x200.0000 { 0x1000000, 0x1000000, 0x1000000, MT_DEVICE | MT_RW | MT_SECURE }, //2G { DRAM1_BASE, DRAM1_BASE, SUNXI_MAX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS}, {0} }; void sunxi_configure_mmu_el3(unsigned long total_base, unsigned long total_size, unsigned long ro_start, unsigned long ro_limit, unsigned long coh_start, unsigned long coh_limit) { mmap_add_region(total_base, total_base, total_size, MT_MEMORY | MT_RW | MT_SECURE); mmap_add_region(ro_start, ro_start, ro_limit - ro_start, MT_MEMORY | MT_RO | MT_SECURE); mmap_add_region(coh_start, coh_start, coh_limit - coh_start, MT_DEVICE | MT_RW | MT_SECURE); mmap_add(sunxi_mmap); init_xlat_tables(); enable_mmu_el3(0); } unsigned long plat_get_ns_image_entrypoint(void) { return NS_IMAGE_OFFSET; } uint64_t plat_get_syscnt_freq(void) { return 24 * 1000 * 1000; } static unsigned int get_highest_el(int aarch) { unsigned int el_status; /* Figure out whether we have the HYP/EL2 mode implemented */ if (aarch == 32) { el_status = (read_id_pfr1_el1() >> ID_PFR1_VIRTEXT_SHIFT); el_status &= ID_PFR1_VIRTEXT_MASK; return el_status ? MODE32_hyp : MODE32_svc; } else if (aarch == 64) { el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; el_status &= ID_AA64PFR0_ELX_MASK; return el_status ? MODE_EL2 : MODE_EL1; } else { return -1; } } /******************************************************************************* * Gets SPSR for BL33 entry ******************************************************************************/ uint32_t sunxi_get_spsr_for_bl33_entry(int aarch) { unsigned int mode; uint32_t spsr; mode = get_highest_el(aarch); switch (aarch) { case 32: spsr = SPSR_MODE32(mode, SPSR_T_ARM, SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); break; case 64: default: spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); break; } return spsr; } #define SRAM_VER_REG 0x01c00024 uint16_t sunxi_get_socid(void) { uint32_t reg; reg = mmio_read_32(SRAM_VER_REG); mmio_write_32(SRAM_VER_REG, reg | (1 << 15)); reg = mmio_read_32(SRAM_VER_REG); mmio_write_32(0x01c00024, reg & ~(1 << 15)); return reg >> 16; } struct spl_boot_file_head { uint32_t jump_instruction; uint32_t magic[2]; uint32_t check_sum; uint32_t length; uint8_t spl_signature[4]; uint32_t fel_script_address; uint32_t fel_uEnv_length; uint32_t offset_dt_name; uint32_t reserved1; uint32_t boot_media; uint32_t string_pool[13]; }; #define MAGIC_eGON 0x4e4f4765 /* "eGON" */ #define MAGIC_BT0 0x3054422e /* ".BT0" */ #define MAGIC_FEL 0x4c45462e /* ".FEL" */ const char *get_dt_name(void) { const struct spl_boot_file_head *spl_head = (void *)0x10000; if (spl_head->magic[0] != MAGIC_eGON) return NULL; if (spl_head->magic[1] != MAGIC_BT0 && spl_head->magic[1] != MAGIC_FEL) return NULL; /* We need at least U-Boot SPL version 2 for the DT name feature. */ if (spl_head->spl_signature[3] < 2) return NULL; return (const char *)spl_head + spl_head->offset_dt_name; } arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/bl31_sunxi_setup.c000066400000000000000000000226721322600646200243640ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include "sunxi_def.h" #include "sunxi_private.h" #include /******************************************************************************* * Declarations of linker defined symbols which will help us find the layout * of trusted SRAM ******************************************************************************/ extern unsigned long __RO_START__; extern unsigned long __RO_END__; extern unsigned long __COHERENT_RAM_START__; extern unsigned long __COHERENT_RAM_END__; /* * The next 2 constants identify the extents of the code & RO data region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. */ #define BL31_RO_BASE (unsigned long)(&__RO_START__) #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) /* * The next 2 constants identify the extents of the coherent memory region. * These addresses are used by the MMU setup code and therefore they must be * page-aligned. It is the responsibility of the linker script to ensure that * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols * refer to page-aligned addresses. */ #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) #if 0 #if RESET_TO_BL31 static entry_point_info_t bl33_image_ep_info; #else /******************************************************************************* * Reference to structure which holds the arguments that have been passed to * BL31 from BL2. ******************************************************************************/ static bl31_params_t *bl2_to_bl31_params; #endif #else static entry_point_info_t bl33_image_ep_info; #endif /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for the * security state specified. BL33 corresponds to the non-secure image type * while BL32 corresponds to the secure image type. A NULL pointer is returned * if the image does not exist. ******************************************************************************/ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) { //#if RESET_TO_BL31 #if 1 assert(sec_state_is_valid(type)); assert(type == NON_SECURE); return &bl33_image_ep_info; #else entry_point_info_t *next_image_info; assert(sec_state_is_valid(type)); next_image_info = (type == NON_SECURE) ? bl2_to_bl31_params->bl33_ep_info : bl2_to_bl31_params->bl32_ep_info; /* None of the images on this platform can have 0x0 as the entrypoint */ if (next_image_info->pc) return next_image_info; else return NULL; #endif } static unsigned long get_pc(void) { unsigned long pc; __asm__ volatile ("adr %0, .\n" : "=r" (pc)); return pc; } /******************************************************************************* * Perform any BL31 specific platform actions. Here is an opportunity to copy * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they * are lost (potentially). This needs to be done before the MMU is initialized * so that the memory layout can be used while creating page tables. On the FVP * we know that BL2 has populated the parameters in secure DRAM. So we just use * the reference passed in 'from_bl2' instead of copying. The 'data' parameter * is not used since all the information is contained in 'from_bl2'. Also, BL2 * has flushed this information to memory, so we are guaranteed to pick up good * data ******************************************************************************/ void bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { unsigned long load_addr; const char *mem_name = "unknown memory region"; const char *soc_name = "unknown SoC"; uint16_t soc_id; /* Initialize the console to provide early debug support */ console_init(SUNXI_UART0_BASE, UART0_CLK_IN_HZ, UART0_BAUDRATE); load_addr = get_pc() & ~0xfff; if (load_addr >= 0x44000 && load_addr < 0x54000) { mem_name = "SRAM A2"; } else if (load_addr >= 0x10000 && load_addr < 0x18000) { mem_name = "SRAM A1"; } else if (load_addr >= 0x18000 && load_addr < 0x40000) { mem_name = "SRAM C"; } else if (load_addr >= 0x40000000) mem_name = "DRAM"; soc_id = sunxi_get_socid(); switch (soc_id) { case 0x1689: soc_name = "A64/H64"; break; case 0x1718: soc_name = "H5"; break; } NOTICE("BL3-1: Running on %s (%x) in %s (@0x%lx)\n", soc_name, soc_id, mem_name, load_addr); #if 0 #if RESET_TO_BL31 /* There are no parameters from BL2 if BL31 is a reset vector */ assert(from_bl2 == NULL); assert(plat_params_from_bl2 == NULL); /* * Do initial security configuration to allow DRAM/device access. On * Base FVP only DRAM security is programmable (via TrustZone), but * other platforms might have more programmable security devices * present. */ sunxi_security_setup(); SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); /* * Tell BL31 where the non-trusted software image * is located and the entry state information */ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); bl33_image_ep_info.spsr = sunxi_get_spsr_for_bl33_entry(64); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); #else /* Check params passed from BL2 should not be NULL, * We are not checking plat_params_from_bl2 as NULL as we are not * using it on FVP */ assert(from_bl2 != NULL); assert(from_bl2->h.type == PARAM_BL31); assert(from_bl2->h.version >= VERSION_1); sunxi_security_setup(); bl2_to_bl31_params = from_bl2; assert(((unsigned long)plat_params_from_bl2) == SUNXI_BL31_PLAT_PARAM_VAL); #endif #endif /* * Do initial security configuration to allow DRAM/device access. On * Base FVP only DRAM security is programmable (via TrustZone), but * other platforms might have more programmable security devices * present. */ sunxi_security_setup(); /* * Tell BL31 where the non-trusted software image * is located and the entry state information */ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); bl33_image_ep_info.spsr = sunxi_get_spsr_for_bl33_entry(64); SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); } /******************************************************************************* * Initialize the gic, configure the CLCD and zero out variables needed by the * secondaries to boot up correctly. ******************************************************************************/ void bl31_platform_setup(void) { uint16_t socid; const char *dt_name; /* Initialize the gic cpu and distributor interfaces */ arm_gic_init(GICC_BASE, GICD_BASE, 0, NULL, 0); arm_gic_setup(); socid = sunxi_get_socid(); dt_name = get_dt_name(); if (dt_name) NOTICE("DT: %s\n", dt_name); else NOTICE("No DT name found, skipping board specific setup.\n"); /* Detect if this SoC is a multi-cluster one. */ plat_setup_topology(); switch (socid) { case 0x1689: sunxi_pmic_setup(dt_name); break; case 0x1718: break; } sunxi_setup_clocks(socid, dt_name); NOTICE("SCPI: dummy stub handler, implementation level: 000000\n"); } /******************************************************************************* * Perform the very early platform specific architectural setup here. At the * moment this is only intializes the mmu in a quick and dirty way. ******************************************************************************/ void bl31_plat_arch_setup(void) { //set smp bit before cache enable platform_smp_init(); sunxi_configure_mmu_el3(BL31_RO_BASE, (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), BL31_RO_BASE, BL31_RO_LIMIT, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT); } arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/drivers/000077500000000000000000000000001322600646200224565ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/drivers/uart/000077500000000000000000000000001322600646200234315ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/drivers/uart/uart.c000066400000000000000000000075261322600646200245620ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #if DEBUG uintptr_t serial_ctrl_base; int uart_locked = 1; void sunxi_serial_init(int uart_port) { uint32_t reg; uint32_t uart_clk; /* assert the UART port's reset line */ reg = mmio_read_32(CCMU_BUS_SOFT_RST_REG4); reg &= ~(1 << (CCM_UART_PORT_OFFSET + uart_port)); mmio_write_32(CCMU_BUS_SOFT_RST_REG4, reg); /* release the clock gate */ reg = mmio_read_32(CCMU_BUS_CLK_GATING_REG3); reg |= (1 << (CCM_UART_PORT_OFFSET + uart_port)); mmio_write_32(CCMU_BUS_CLK_GATING_REG3, reg); /* de-assert the UART port's reset line */ reg = mmio_read_32(CCMU_BUS_SOFT_RST_REG4); reg |= (1 << (CCM_UART_PORT_OFFSET + uart_port)); mmio_write_32(CCMU_BUS_SOFT_RST_REG4, reg); /* The GPIO pins are already configured */ serial_ctrl_base = SUNXI_UART0_BASE + uart_port * CCM_UART_ADDR_OFFSET; mmio_write_32(serial_ctrl_base + DW_UART_MCR, 0x3); uart_clk = (24000000 + 8 * UART_BAUD) / (16 * UART_BAUD); mmio_write_32(serial_ctrl_base + DW_UART_LCR, mmio_read_32(serial_ctrl_base + DW_UART_LCR) | 0x80); mmio_write_32(serial_ctrl_base + DW_UART_DLH, uart_clk >> 8); mmio_write_32(serial_ctrl_base + DW_UART_DLL, uart_clk & 0xff); mmio_write_32(serial_ctrl_base + DW_UART_LCR, mmio_read_32(serial_ctrl_base + DW_UART_LCR) & ~0x80); mmio_write_32(serial_ctrl_base + DW_UART_LCR, (PARITY << 3) | (STOP << 2) | DLEN); mmio_write_32(serial_ctrl_base + DW_UART_FCR, 0x7); uart_locked = 0; return; } void sunxi_serial_exit(void) { uart_locked = 1; } void sunxi_serial_putc (char c) { if (uart_locked) return; while (!(mmio_read_32(serial_ctrl_base + DW_UART_LSR) & 0x40)) ; mmio_write_32(serial_ctrl_base + DW_UART_THR, c); } char sunxi_serial_getc (void) { if (uart_locked) return 0; while (!(mmio_read_32(serial_ctrl_base + DW_UART_LSR) & 0x01)) ; return mmio_read_32(serial_ctrl_base + DW_UART_RBR); } int sunxi_serial_tstc (void) { return mmio_read_32(serial_ctrl_base + DW_UART_LSR) & 0x01; } #endif /* DEBUG */ int console_init(unsigned long base_addr, unsigned int uart_clk, unsigned int baud_rate) { sunxi_serial_init(0); return 0; } int console_exit() { sunxi_serial_exit(); return 0; } int console_putc(int c) { sunxi_serial_putc(c); return 0; } int console_getc(void) { return sunxi_serial_getc(); } arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/include/000077500000000000000000000000001322600646200224235ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/include/ccmu.h000066400000000000000000000100601322600646200235200ustar00rootroot00000000000000/* * (C) Copyright 2007-2015 * Allwinner Technology Co., Ltd. * Jerry Wang * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * SPDX-License-Identifier: GPL-2.0 */ #ifndef __CCMU_H #define __CCMU_H #include "../sunxi_def.h" /* pll list */ #define CCMU_PLL_CPUX_CTRL_REG (SUNXI_CCM_BASE + 0x00) #define CCMU_PLL_AUDIO_CTRL_REG (SUNXI_CCM_BASE + 0x08) #define CCMU_PLL_VIDEO0_CTRL_REG (SUNXI_CCM_BASE + 0x10) #define CCMU_PLL_VE_CTRL_REG (SUNXI_CCM_BASE + 0x18) #define CCMU_PLL_DDR0_CTRL_REG (SUNXI_CCM_BASE + 0x20) #define CCMU_PLL_PERIPH0_CTRL_REG (SUNXI_CCM_BASE + 0x28) #define CCMU_PLL_PERIPH1_CTRL_REG (SUNXI_CCM_BASE + 0x2C) #define CCMU_PLL_VIDEO1_CTRL_REG (SUNXI_CCM_BASE + 0x30) #define CCMU_PLL_GPU_CTRL_REG (SUNXI_CCM_BASE + 0x38) #define CCMU_PLL_MIPI_CTRL_REG (SUNXI_CCM_BASE + 0x40) #define CCMU_PLL_HSIC_CTRL_REG (SUNXI_CCM_BASE + 0x44) #define CCMU_PLL_DE_CTRL_REG (SUNXI_CCM_BASE + 0x48) #define CCMU_PLL_DDR1_CTRL_REG (SUNXI_CCM_BASE + 0x4C) #define PLL_ENABLE_BIT (1U << 31) #define PLL_STABLE_BIT (1U << 28) /* cfg list */ #define CCMU_CPUX_AXI_CFG_REG (SUNXI_CCM_BASE + 0x50) #define CPUX_SRCSEL_MASK (0x3 << 16) #define CPUX_SRCSEL_LOSC (0x0 << 16) #define CPUX_SRCSEL_OSC24M (0x1 << 16) #define CPUX_SRCSEL_PLLCPUX (0x2 << 16) #define AXI_CLKDIV_MASK (0x3 << 8) #define AXI_CLKDIV(n) ((n - 1) << 8) #define APB_CLKDIV_MASK (0x3 << 0) #define APB_CLKDIV(n) ((n - 1) << 0) #define CCMU_AHB1_APB1_CFG_REG (SUNXI_CCM_BASE + 0x54) #define CCMU_APB2_CFG_GREG (SUNXI_CCM_BASE + 0x58) #define CCMU_AHB2_CFG_GREG (SUNXI_CCM_BASE + 0x5C) /* gate list */ #define CCMU_BUS_CLK_GATING_REG0 (SUNXI_CCM_BASE + 0x60) #define CCMU_BUS_CLK_GATING_REG1 (SUNXI_CCM_BASE + 0x64) #define CCMU_BUS_CLK_GATING_REG2 (SUNXI_CCM_BASE + 0x68) #define CCMU_BUS_CLK_GATING_REG3 (SUNXI_CCM_BASE + 0x6C) #define CCMU_BUS_CLK_GATING_REG4 (SUNXI_CCM_BASE + 0x70) /* module list */ #define CCMU_NAND0_CLK_REG (SUNXI_CCM_BASE + 0x80) #define CCMU_SDMMC0_CLK_REG (SUNXI_CCM_BASE + 0x88) #define CCMU_SDMMC1_CLK_REG (SUNXI_CCM_BASE + 0x8C) #define CCMU_SDMMC2_CLK_REG (SUNXI_CCM_BASE + 0x90) #define CCMU_CE_CLK_REG (SUNXI_CCM_BASE + 0x9C) #define CCMU_USBPHY_CLK_REG (SUNXI_CCM_BASE + 0xCC) #define CCMU_DRAM_CLK_REG (SUNXI_CCM_BASE + 0xF4) #define CCMU_PLL_DDR_CFG_REG (SUNXI_CCM_BASE + 0xF8) #define CCMU_MBUS_RST_REG (SUNXI_CCM_BASE + 0xFC) #define CCMU_DRAM_CLK_GATING_REG (SUNXI_CCM_BASE + 0x100) #define CCMU_AVS_CLK_REG (SUNXI_CCM_BASE + 0x144) #define CCMU_MBUS_CLK_REG (SUNXI_CCM_BASE + 0x15C) /*gate rst list*/ #define CCMU_BUS_SOFT_RST_REG0 (SUNXI_CCM_BASE + 0x2C0) #define CCMU_BUS_SOFT_RST_REG1 (SUNXI_CCM_BASE + 0x2C4) #define CCMU_BUS_SOFT_RST_REG2 (SUNXI_CCM_BASE + 0x2C8) #define CCMU_BUS_SOFT_RST_REG3 (SUNXI_CCM_BASE + 0x2D0) #define CCMU_BUS_SOFT_RST_REG4 (SUNXI_CCM_BASE + 0x2D8) #define CCMU_PLL_LOCK_CTRL_REG (SUNXI_CCM_BASE + 0x320) #define LOCK_EN_PLL_CPUX (1U << 0) #endif arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/include/plat_macros.S000066400000000000000000000056361322600646200250650ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "../sunxi_def.h" .section .rodata.gic_reg_name, "aS" gic_regs: .asciz "gic_hppir", "gic_ahppir", "gic_ctlr", "" gicd_pend_reg: .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" newline: .asciz "\n" spacer: .asciz ":\t\t0x" /* --------------------------------------------- * The below macro prints out relevant GIC * registers whenever an unhandled exception is * taken in BL3-1. * Clobbers: x0 - x10, x16, sp * --------------------------------------------- */ .macro plat_print_gic_regs adr x0, plat_config ldr w16, [x0, #CONFIG_GICC_BASE_OFFSET] cbz x16, exit_print_gic_regs /* gic base address is now in x16 */ adr x6, gic_regs /* Load the gic reg list to x6 */ /* Load the gic regs to gp regs used by str_in_crash_buf_print */ ldr w8, [x16, #GICC_HPPIR] ldr w9, [x16, #GICC_AHPPIR] ldr w10, [x16, #GICC_CTLR] /* Store to the crash buf and print to console */ bl str_in_crash_buf_print /* Print the GICD_ISPENDR regs */ add x7, x16, #GICD_ISPENDR adr x4, gicd_pend_reg bl asm_print_str gicd_ispendr_loop: sub x4, x7, x16 cmp x4, #0x280 b.eq exit_print_gic_regs bl asm_print_hex adr x4, spacer bl asm_print_str ldr x4, [x7], #8 bl asm_print_hex adr x4, newline bl asm_print_str b gicd_ispendr_loop exit_print_gic_regs: .endm .macro plat_print_interconnect_regs .endm arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/include/platform_def.h000066400000000000000000000105131322600646200252360ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PLATFORM_DEF_H__ #define __PLATFORM_DEF_H__ #include #include "../sunxi_def.h" /******************************************************************************* * Platform binary types for linking ******************************************************************************/ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" #define PLATFORM_LINKER_ARCH aarch64 /******************************************************************************* * Generic platform constants ******************************************************************************/ #define DEBUG_XLAT_TABLE 0 /* Size of cacheable stacks */ #if DEBUG_XLAT_TABLE #define PLATFORM_STACK_SIZE 0x800 #elif IMAGE_BL31 #define PLATFORM_STACK_SIZE 0x400 #endif #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" /* EL3 Runtime Firmware BL31 */ #define BL31_IMAGE_NAME "bl31.bin" /* Non-Trusted Firmware BL33 */ #define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ #define PLATFORM_CACHE_LINE_SIZE 64 #define PLATFORM_CLUSTER_COUNT 1 #define PLATFORM_CORE_COUNT 4 #define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT) #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 /******************************************************************************* * BL31 specific defines. ******************************************************************************/ /* * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if * present). BL31_BASE is calculated using the current BL3-1 debug size plus a * little space for growth. */ #define BL31_BASE (SUNXI_TRUSTED_MONITOR_BASE) #define BL31_PROGBITS_LIMIT (SUNXI_TRUSTED_MONITOR_LIMIT - 0x6000) #define BL31_LIMIT SUNXI_TRUSTED_MONITOR_LIMIT /******************************************************************************* * Platform specific page table and MMU setup constants ******************************************************************************/ #define ADDR_SPACE_SIZE (1ull << 32) #define MAX_XLAT_TABLES 4 #define MAX_MMAP_REGIONS 16 /******************************************************************************* * Declarations and constants to access the mailboxes safely. Each mailbox is * aligned on the biggest cache line size in the platform. This is known only * to the platform as it might have a combination of integrated and external * caches. Such alignment ensures that two maiboxes do not sit on the same cache * line at any cache level. They could belong to different cpus/clusters & * get written while being protected by different locks causing corruption of * a valid mailbox address. ******************************************************************************/ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) #endif /* __PLATFORM_DEF_H__ */ arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/include/uart.h000066400000000000000000000024351322600646200235530ustar00rootroot00000000000000#ifndef _UART_H_ #define _UART_H_ #define CCM_UART_PORT_OFFSET 16 #define CCM_UART_ADDR_OFFSET 0x400 #define DW_UART_RBR 0x00 #define DW_UART_THR 0x00 #define DW_UART_DLL 0x00 #define DW_UART_IER 0x04 #define DW_UART_DLH 0x04 #define DW_UART_FCR 0x08 #define DW_UART_LCR 0x0c #define DW_UART_MCR 0x10 #define DW_UART_LSR 0x14 #define DW_UART_MSR 0x18 #define DW_UART_SCH 0x1c #define UART_BAUD 115200 // Baud rate for UART // Compute the divisor factor // UART Line Control Parameter #define PARITY 0 // Parity: 0,2 - no parity; 1 - odd parity; 3 - even parity #define STOP 0 // Number of Stop Bit: 0 - 1bit; 1 - 2(or 1.5)bits #define DLEN 3 // Data Length: 0 - 5bits; 1 - 6bits; 2 - 7bits; 3 - 8bits #if DEBUG void sunxi_serial_init(int uart_port); void sunxi_serial_exit(void); void sunxi_serial_putc (char c); char sunxi_serial_getc (void); int sunxi_serial_tstc (void); #else static inline void sunxi_serial_init(int uart_port) {} static inline void sunxi_serial_exit(void) {} static inline void sunxi_serial_putc(char c) {} static inline char sunxi_serial_getc(void) { return 0;} static inline int sunxi_serial_tstc(void) { return 0;} #endif #endif /* #ifndef _UART_H_ */ arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/plat_pm.c000066400000000000000000000261041322600646200226030ustar00rootroot00000000000000/* * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include "sunxi_def.h" #include "sunxi_private.h" #include "sunxi_cpu_ops.h" #include #include #include bakery_lock_t plat_console_lock __attribute__ ((section("tzfw_coherent_mem"))); /******************************************************************************* * Private Sunxi function which is used to determine if any platform actions * should be performed for the specified affinity instance given its * state. Nothing needs to be done if the 'state' is not off or if this is not * the highest affinity level which will enter the 'state'. ******************************************************************************/ static int32_t sunxi_do_plat_actions(uint32_t afflvl, uint32_t state) { uint32_t max_phys_off_afflvl; assert(afflvl <= MPIDR_MAX_AFFLVL); if (state != PSCI_STATE_OFF) return -EAGAIN; /* * Find the highest affinity level which will be suspended and postpone * all the platform specific actions until that level is hit. */ max_phys_off_afflvl = psci_get_max_phys_off_afflvl(); assert(max_phys_off_afflvl != PSCI_INVALID_DATA); assert(psci_get_suspend_afflvl() >= max_phys_off_afflvl); if (afflvl != max_phys_off_afflvl) return -EAGAIN; return 0; } /******************************************************************************* * Sunxi handler called when an affinity instance is about to be turned on. The * level and mpidr determine the affinity instance. ******************************************************************************/ int32_t sunxi_affinst_on(uint64_t mpidr, uint64_t sec_entrypoint, uint64_t ns_entrypoint, uint32_t afflvl, uint32_t state) { int cpu_nr = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; int cluster_nr = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; if (afflvl != MPIDR_AFFLVL0) return PSCI_E_SUCCESS; sun50i_set_secondary_entry(sec_entrypoint, cpu_nr); sun50i_cpu_power_up(cluster_nr, cpu_nr); return PSCI_E_SUCCESS; } /******************************************************************************* * Sunxi handler called when an affinity instance has just been powered on after * being turned off earlier. The level and mpidr determine the affinity * instance. The 'state' arg. allows the platform to decide whether the cluster * was turned off prior to wakeup and do what's necessary to setup it up * correctly. ******************************************************************************/ int32_t sunxi_affinst_on_finish(uint64_t mpidr, uint32_t afflvl, uint32_t state) { /* Determine if any platform actions need to be executed. */ if (sunxi_do_plat_actions(afflvl, state) == -EAGAIN) return PSCI_E_SUCCESS; // set smp bit before cache enable platform_smp_init(); /* Enable the gic cpu interface */ arm_gic_cpuif_setup(); arm_gic_pcpu_distif_setup(); return PSCI_E_SUCCESS; } /******************************************************************************* * sunxi handler called when an affinity instance is about to enter standby. ******************************************************************************/ int sunxi_affinst_standby(unsigned int power_state) { unsigned int target_afflvl; uint64_t scr = 0; /* Sanity check the requested state */ target_afflvl = psci_get_pstate_afflvl(power_state); /* * It's possible to enter standby only on affinity level 0 i.e. a core. * Ignore any other affinity level. */ if (target_afflvl != MPIDR_AFFLVL0) return PSCI_E_INVALID_PARAMS; scr = read_scr_el3(); /* enable physical IRQ bit for NS world to wakeup the CPU */ write_scr_el3(scr | SCR_IRQ_BIT); isb(); /* * Enter standby state * dsb is good practice before using wfi to enter low power states */ dsb(); wfi(); /* * Restore SCR to the original value, sync of scr_el3 is done * by eret while el3_exit to save some execution cycles. */ write_scr_el3(scr); return PSCI_E_SUCCESS; } /******************************************************************************* * Common function called while turning a cpu off or suspending it. It is called * from sunxi_off() or sunxi_suspend() when these functions in turn are called for * the highest affinity level which will be powered down. It performs the * actions common to the OFF and SUSPEND calls. ******************************************************************************/ static int32_t sunxi_power_down_common(uint32_t afflvl, uint64_t mpidr, uint64_t sec_entrypoint) { /* Prevent interrupts from spuriously waking up this cpu */ arm_gic_cpuif_deactivate(); /* We can't turn ourselves off at this point, do this later. */ return PSCI_E_SUCCESS; } static void sunxi_core_power_down_wfi(uint64_t mpidr) { int cpu_nr = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; int cluster_nr = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; sun50i_cpu_power_down(cluster_nr, cpu_nr); } /******************************************************************************* * Handler called when an affinity instance is about to be turned off. The * level and mpidr determine the affinity instance. The 'state' arg. allows the * platform to decide whether the cluster is being turned off and take * appropriate actions. * * CAUTION: There is no guarantee that caches will remain turned on across calls * to this function as each affinity level is dealt with. So do not write & read * global variables across calls. It will be wise to do flush a write to the * global to prevent unpredictable results. ******************************************************************************/ static int32_t sunxi_affinst_off(uint64_t mpidr, uint32_t afflvl, uint32_t state) { /* Determine if any platform actions need to be executed */ if (sunxi_do_plat_actions(afflvl, state) == -EAGAIN) return PSCI_E_SUCCESS; return sunxi_power_down_common(afflvl, mpidr, 0); } /******************************************************************************* * Handler called when an affinity instance is about to be suspended. The * level and mpidr determine the affinity instance. The 'state' arg. allows the * platform to decide whether the cluster is being turned off and take apt * actions. The 'sec_entrypoint' determines the address in BL3-1 from where * execution should resume. * * CAUTION: There is no guarantee that caches will remain turned on across calls * to this function as each affinity level is dealt with. So do not write & read * global variables across calls. It will be wise to do flush a write to the * global to prevent unpredictable results. ******************************************************************************/ static int32_t sunxi_affinst_suspend(uint64_t mpidr, uint64_t sec_entrypoint, uint64_t ns_entrypoint, uint32_t afflvl, uint32_t state) { /* Determine if any platform actions need to be executed */ if (sunxi_do_plat_actions(afflvl, state) == -EAGAIN) return PSCI_E_SUCCESS; if (afflvl == psci_get_suspend_afflvl()) console_exit(); return sunxi_power_down_common(afflvl, mpidr, sec_entrypoint); } /******************************************************************************* * Sunxi handler called when an affinity instance has just been powered on after * having been suspended earlier. The level and mpidr determine the affinity * instance. * TODO: At the moment we reuse the on finisher and reinitialize the secure * context. Need to implement a separate suspend finisher. ******************************************************************************/ static int32_t sunxi_affinst_suspend_finish(uint64_t mpidr, uint32_t afflvl, uint32_t state) { if ((afflvl == psci_get_suspend_afflvl()) && ((mpidr & 0xff) == 0x0)) { arm_gic_init(GICC_BASE, GICD_BASE, 0, NULL, 0); arm_gic_setup(); console_init(SUNXI_UART0_BASE, UART0_CLK_IN_HZ, UART0_BAUDRATE); } return sunxi_affinst_on_finish(mpidr, afflvl, state); } /******************************************************************************* * Sunxi handlers to shutdown/reboot the system ******************************************************************************/ static void __dead2 sunxi_system_off(void) { sunxi_pmic_write(0x32, sunxi_pmic_read(0x32) | 0x80); ERROR("PSCI system shutdown: still alive ...\n"); wfi(); panic(); } static void __dead2 sunxi_system_reset(void) { mmio_write_32(0x01c20cb4, 1); mmio_write_32(0x01c20cb8, 1); mmio_write_32(0x01c20cb0, (0xa57 << 1) | 0x01); wfi(); ERROR("Sunxi System Reset: operation not handled.\n"); panic(); } /******************************************************************************* * Export the platform handlers to enable psci to invoke them ******************************************************************************/ static const plat_pm_ops_t sunxi_ops = { .affinst_standby = sunxi_affinst_standby, .affinst_on = sunxi_affinst_on, .affinst_on_finish = sunxi_affinst_on_finish, .affinst_off = sunxi_affinst_off, .affinst_suspend = sunxi_affinst_suspend, .affinst_suspend_finish = sunxi_affinst_suspend_finish, .core_power_down_wfi = sunxi_core_power_down_wfi, .system_off = sunxi_system_off, .system_reset = sunxi_system_reset }; /******************************************************************************* * Export the platform specific power ops. ******************************************************************************/ int32_t platform_setup_pm(const plat_pm_ops_t **plat_ops) { *plat_ops = &sunxi_ops; bakery_lock_init(&plat_console_lock); return 0; } arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/plat_topology.c000066400000000000000000000047251322600646200240500ustar00rootroot00000000000000/* * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr) { /* Report 1 (absent) instance at levels higher that the cluster level */ if (aff_lvl > MPIDR_AFFLVL1) return 1; if (aff_lvl == MPIDR_AFFLVL1) return PLATFORM_CLUSTER_COUNT; return PLATFORM_MAX_CPUS_PER_CLUSTER; } unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr) { #if (PLATFORM_CLUSTER_COUNT == 1) return aff_lvl <= MPIDR_AFFLVL0 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; #else return aff_lvl <= MPIDR_AFFLVL1 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; #endif } int plat_get_max_afflvl(void) { #if (PLATFORM_CLUSTER_COUNT == 1) return MPIDR_AFFLVL0; #else return MPIDR_AFFLVL1; #endif } int plat_setup_topology() { /* * Once we see multiple cluster SoCs appearing, we can read some * ID register here and set the number of clusters at runtime. * For now there is nothing to do. */ return 0; } arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/platform.mk000066400000000000000000000044401322600646200231570ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # PLAT_INCLUDES := -Iplat/sun50iw1p1/include/ PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \ plat/common/aarch64/plat_common.c \ plat/sun50iw1p1/drivers/uart/uart.c BL31_SOURCES += drivers/arm/gic/arm_gic.c \ drivers/arm/gic/gic_v2.c \ drivers/arm/gic/gic_v3.c \ lib/cpus/aarch64/cortex_a53.S \ plat/common/plat_gic.c \ plat/common/aarch64/platform_mp_stack.S \ plat/sun50iw1p1/bl31_sunxi_setup.c \ plat/sun50iw1p1/plat_pm.c \ plat/sun50iw1p1/sunxi_security.c \ plat/sun50iw1p1/sunxi_power.c \ plat/sun50iw1p1/sunxi_cpu_ops.c \ plat/sun50iw1p1/plat_topology.c \ plat/sun50iw1p1/aarch64/plat_helpers.S \ plat/sun50iw1p1/sunxi_clocks.c \ plat/sun50iw1p1/sunxi_sip_svc.c \ plat/sun50iw1p1/aarch64/sunxi_common.c arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/sunxi_clocks.c000066400000000000000000000071751322600646200236620ustar00rootroot00000000000000/* * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "sunxi_private.h" #define PLL_CPUX_1008MHZ 0x1410 #define PLL_CPUX_816MHZ 0x1010 #define PLL_CPUX_408MHZ 0x1000 static void mmio_clrsetbits32(uintptr_t addr, uint32_t mask, uint32_t bits) { uint32_t regval = mmio_read_32(addr); regval &= ~mask; regval |= bits; mmio_write_32(addr, regval); } static void mmio_setbits32(uintptr_t addr, uint32_t bits) { uint32_t regval = mmio_read_32(addr); regval |= bits; mmio_write_32(addr, regval); } /* TODO (prt): we should have a timeout and return an error/success... */ static int pll_wait_until_stable(uintptr_t addr) { while ((mmio_read_32(addr) & PLL_STABLE_BIT) != PLL_STABLE_BIT) { /* spin */ } return 0; } int sunxi_setup_clocks(uint16_t socid, const char *dt_name) { uint32_t reg; /* Avoid reprogramming PERIPH0 if not necessary */ reg = mmio_read_32(CCMU_PLL_PERIPH0_CTRL_REG); if ((reg & 0x0fffffff) != 0x41811) /* is not at 600 MHz? */ mmio_write_32(CCMU_PLL_PERIPH0_CTRL_REG, 0x80041811); /* Set up dividers (suitable for the target clock frequency) and switch CPUX (and thus AXI & APB) to the LOSC24 clock */ mmio_write_32(CCMU_CPUX_AXI_CFG_REG, ( CPUX_SRCSEL_OSC24M | APB_CLKDIV(4) | AXI_CLKDIV(3) )); udelay(20); /* Set to 816MHz, but don't enable yet. */ mmio_write_32(CCMU_PLL_CPUX_CTRL_REG, PLL_CPUX_816MHZ); /* Enable PLL_CPUX again */ mmio_setbits32(CCMU_PLL_CPUX_CTRL_REG, PLL_ENABLE_BIT); /* Wait until the PLL_CPUX becomes stable */ pll_wait_until_stable(CCMU_PLL_CPUX_CTRL_REG); /* Wait another 20us, because Allwinner does so... */ udelay(20); /* Switch AXI clock back to PLL_CPUX, dividers are set up already. */ mmio_clrsetbits32(CCMU_CPUX_AXI_CFG_REG, CPUX_SRCSEL_MASK, CPUX_SRCSEL_PLLCPUX); /* Wait 1000us, because Allwiner does so... */ udelay(1000); /* AHB1 = PERIPH0 / (3 * 1) = 200MHz, APB1 = AHB1 / 2 */ mmio_write_32(CCMU_AHB1_APB1_CFG_REG, 0x00003180); mmio_write_32(CCMU_APB2_CFG_GREG, 0x01000000); /* APB2 => 24 MHz */ mmio_write_32(CCMU_AHB2_CFG_GREG, 0x00000001); /* AHB2 => 300 MHz */ return 0; } arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/sunxi_cpu_ops.c000066400000000000000000000205561322600646200240520ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include "sunxi_def.h" #include "sunxi_private.h" #define SUN50I_PRCM_PBASE (0x01F01400) #define SUN50I_CPUCFG_PBASE (0x01700000) #define SUN50I_RCPUCFG_PBASE (0x01F01C00) #define SUNXI_CPU_PWR_CLAMP(cluster, cpu) (0x140 + (cluster*4 + cpu)*0x04) #define SUNXI_CLUSTER_PWROFF_GATING(cluster) (0x100 + (cluster)*0x04) #define SUNXI_CLUSTER_PWRON_RESET(cluster) (0x30 + (cluster)*0x04) #define SUNXI_DBG_REG0 (0x20) #define SUNXI_CLUSTER_CPU_STATUS(cluster) (0x30 + (cluster)*0x4) #define SUNXI_CPU_RST_CTRL(cluster) (0x80 + (cluster)*0x4) #define SUNXI_CLUSTER_CTRL0(cluster) (0x00 + (cluster)*0x10) #define SUNXI_CPU_RVBA_L(cpu) (0xA0 + (cpu)*0x8) #define SUNXI_CPU_RVBA_H(cpu) (0xA4 + (cpu)*0x8) #define readl(x) mmio_read_32((x)) #define writel(v, a) mmio_write_32((a), (v)) typedef unsigned int bool; static unsigned int sun50i_cpucfg_base = SUN50I_CPUCFG_PBASE; static unsigned int sun50i_prcm_base = SUN50I_PRCM_PBASE; static unsigned int sun50i_r_cpucfg_base = SUN50I_RCPUCFG_PBASE; extern bakery_lock_t plat_console_lock; void udelay(unsigned int delay) { if (!delay) return; __asm__ volatile ( "1:\tsubs %0, %0, #1\n" "\tb.ne 1b" : "=r" (delay) : "0" (delay * 1000UL) : "cc" ); } #define CPU_DELAY_SHORT 10 #define CPU_DELAY_MEDIUM 20 #define CPU_DELAY_LONG 30 void sun50i_set_secondary_entry(unsigned long entry, unsigned int cpu) { mmio_write_32(sun50i_cpucfg_base + SUNXI_CPU_RVBA_L(cpu) ,entry); mmio_write_32(sun50i_cpucfg_base + SUNXI_CPU_RVBA_H(cpu), 0); } void sun50i_set_AA32nAA64(unsigned int cluster, unsigned int cpu, bool is_aa64) { volatile unsigned int value; value = readl(sun50i_cpucfg_base + SUNXI_CLUSTER_CTRL0(cluster)); value &= ~(1<<(cpu + 24)); value |= (is_aa64 <<(cpu + 24)); writel(value, sun50i_cpucfg_base + SUNXI_CLUSTER_CTRL0(cluster)); value = readl(sun50i_cpucfg_base + SUNXI_CLUSTER_CTRL0(cluster)); } int sun50i_power_switch_set(unsigned int cluster, unsigned int cpu, bool enable) { if (enable) { if (0x00 == readl(sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu))) return 0; /* de-active cpu power clamp */ writel(0xFE, sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu)); udelay(CPU_DELAY_MEDIUM); writel(0xF8, sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu)); udelay(CPU_DELAY_SHORT); writel(0xE0, sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu)); udelay(CPU_DELAY_SHORT); writel(0x80, sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu)); udelay(CPU_DELAY_SHORT); writel(0x00, sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu)); udelay(CPU_DELAY_MEDIUM); while (0x00 != readl(sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu))); } else { if (0xFF == readl(sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu))) return 0; writel(0xFF, sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu)); udelay(CPU_DELAY_LONG); while (0xFF != readl(sun50i_prcm_base + SUNXI_CPU_PWR_CLAMP(cluster, cpu))); } return 0; } void sun50i_cpu_power_up(unsigned int cluster, unsigned int cpu) { unsigned int value; /* Assert nCPUPORESET LOW */ value = readl(sun50i_cpucfg_base + SUNXI_CPU_RST_CTRL(cluster)); value &= (~(1< #include #include #include #include #include "sunxi_def.h" #include "sunxi_private.h" #define R_PRCM_BASE 0x1f01400ULL #define R_TWI_BASE 0x1f02400ULL #define R_PIO_BASE 0x1f02c00ULL #define RSB_BASE 0x1f03400ULL #define RSB_CTRL 0x00 #define RSB_CCR 0x04 #define RSB_INTE 0x08 #define RSB_STAT 0x0c #define RSB_DADDR0 0x10 #define RSB_DLEN 0x18 #define RSB_DATA0 0x1c #define RSB_LCR 0x24 #define RSB_PMCR 0x28 #define RSB_CMD 0x2c #define RSB_SADDR 0x30 #define RSBCMD_SRTA 0xE8 #define RSBCMD_RD8 0x8B #define RSBCMD_RD16 0x9C #define RSBCMD_RD32 0xA6 #define RSBCMD_WR8 0x4E #define RSBCMD_WR16 0x59 #define RSBCMD_WR32 0x63 #define BIT(n) (1U << (n)) #define RUNTIME_ADDR 0x2d #define AXP803_HW_ADDR 0x3a3 /* Initialize the RSB controller and its pins. */ static int init_rsb(void) { uint32_t reg; /* un-gate PIO clock */ reg = mmio_read_32(R_PRCM_BASE + 0x28); mmio_write_32(R_PRCM_BASE + 0x28, reg | 0x01); /* get currently configured function for pins PL0 and PL1 */ reg = mmio_read_32(R_PIO_BASE + 0x00); if ((reg & 0xff) == 0x33) { NOTICE("already configured for TWI\n"); return -EBUSY; } if ((reg & 0xff) == 0x22) { NOTICE("PMIC: already configured for RSB\n"); return -EEXIST; /* configured for RSB mode already */ } /* switch pins PL0 and PL1 to RSB */ mmio_write_32(R_PIO_BASE + 0, (reg & ~0xff) | 0x22); /* level 2 drive strength */ reg = mmio_read_32(R_PIO_BASE + 0x14); mmio_write_32(R_PIO_BASE + 0x14, (reg & ~0x0f) | 0xa); /* set both ports to pull-up */ reg = mmio_read_32(R_PIO_BASE + 0x1c); mmio_write_32(R_PIO_BASE + 0x1c, (reg & ~0x0f) | 0x5); /* assert & de-assert reset of RSB */ reg = mmio_read_32(R_PRCM_BASE + 0xb0); mmio_write_32(R_PRCM_BASE + 0xb0, reg & ~0x08); reg = mmio_read_32(R_PRCM_BASE + 0xb0); mmio_write_32(R_PRCM_BASE + 0xb0, reg | 0x08); /* un-gate RSB clock */ reg = mmio_read_32(R_PRCM_BASE + 0x28); mmio_write_32(R_PRCM_BASE + 0x28, reg | 0x08); mmio_write_32(RSB_BASE + RSB_CTRL, 0x01); /* soft reset */ mmio_write_32(RSB_BASE + RSB_CCR, 0x11d); /* clock to 400 KHz */ do { reg = mmio_read_32(RSB_BASE + RSB_CTRL); } while (reg & 1); /* transaction in progress */ return 0; } int sunxi_pmic_read(uint8_t address) { uint32_t reg; mmio_write_32(RSB_BASE + RSB_DLEN, 0x10); /* read a byte, snake oil? */ mmio_write_32(RSB_BASE + RSB_CMD, RSBCMD_RD8); /* read a byte */ mmio_write_32(RSB_BASE + RSB_DADDR0, address); mmio_write_32(RSB_BASE + RSB_CTRL, 0x80); /* start transaction */ do { reg = mmio_read_32(RSB_BASE + RSB_CTRL); } while (reg & 0x80); /* transaction in progress */ reg = mmio_read_32(RSB_BASE + RSB_STAT); if (reg == 0x01) { /* transaction complete */ reg = mmio_read_32(RSB_BASE + RSB_DATA0); /* result register */ return reg & 0xff; } return -reg; } int sunxi_pmic_write(uint8_t address, uint8_t value) { uint32_t reg; mmio_write_32(RSB_BASE + RSB_DLEN, 0x00); /* write a byte, snake oil? */ mmio_write_32(RSB_BASE + RSB_CMD, RSBCMD_WR8); /* write a byte */ mmio_write_32(RSB_BASE + RSB_DADDR0, address); mmio_write_32(RSB_BASE + RSB_DATA0, value); mmio_write_32(RSB_BASE + RSB_CTRL, 0x80); /* start transaction */ do { reg = mmio_read_32(RSB_BASE + RSB_CTRL); } while (reg & 0x80); /* transaction in progress */ reg = mmio_read_32(RSB_BASE + RSB_STAT); if (reg == 0x01) /* transaction complete */ return 0; return -reg; } static void rsb_wait(const char *desc) { uint32_t reg; int cnt = 0; do { reg = mmio_read_32(RSB_BASE + RSB_CTRL); cnt++; } while (reg & 0x80); /* transaction in progress */ reg = mmio_read_32(RSB_BASE + RSB_STAT); if (reg == 0x01) return; ERROR("%s: 0x%x\n", desc, reg); } /* Initialize the RSB PMIC connection. */ static int pmic_init(uint16_t hw_addr, uint8_t rt_addr) { int ret; /* Switch PMIC to RSB mode */ mmio_write_32(RSB_BASE + RSB_PMCR, 0x00 | (0x3e << 8) | (0x7c << 16) | BIT(31)); do { ret = mmio_read_32(RSB_BASE + RSB_PMCR); } while (ret & (1U << 31)); /* transaction in progress */ mmio_write_32(RSB_BASE + RSB_CCR, 0x103); /* 3 MHz */ mmio_write_32(RSB_BASE + RSB_SADDR, hw_addr | (rt_addr << 16)); mmio_write_32(RSB_BASE + RSB_CMD, RSBCMD_SRTA); mmio_write_32(RSB_BASE + RSB_CTRL, 0x80); rsb_wait("set run-time address"); /* Set slave runtime address */ mmio_write_32(RSB_BASE + RSB_SADDR, rt_addr << 16); ret = sunxi_pmic_read(0x03); if (ret < 0) { ERROR("PMIC: error %d reading PMIC type\n", ret); return -2; } if ((ret & 0xcf) != 0x41) { ERROR("PMIC: unknown PMIC type number 0x%x\n", ret); return -3; } return 0; } /* Setup the PMIC: DCDC1 to 3.3V, enable DC1SW and DLDO4 */ static int pmic_setup(const char *dt_name) { int ret; ret = sunxi_pmic_read(0x20); if (ret != 0x0e && ret != 0x11) { int voltage = (ret & 0x1f) * 10 + 16; NOTICE("PMIC: DCDC1 voltage is an unexpected %d.%dV\n", voltage / 10, voltage % 10); return -1; } if (ret != 0x11) { /* Set DCDC1 voltage to 3.3 Volts */ ret = sunxi_pmic_write(0x20, 0x11); if (ret < 0) { NOTICE("PMIC: error %d writing DCDC1 voltage\n", ret); return -2; } } ret = sunxi_pmic_read(0x12); if ((ret & 0x37) != 0x01) { NOTICE("PMIC: Output power control 2 is an unexpected 0x%x\n", ret); return -3; } if ((ret & 0xc9) != 0xc9) { /* Enable DC1SW to power PHY, DLDO4 for WiFi and DLDO1 for HDMI */ ret = sunxi_pmic_write(0x12, ret | 0xc8); if (ret < 0) { NOTICE("PMIC: error %d enabling DC1SW/DLDO4/DLDO1\n", ret); return -4; } } /* * On the Pine64 the AXP is wired wrongly: to reset DCDC5 to 1.24V. * However the DDR3L chips require 1.36V instead. Fix this up. Other * boards hopefully do the right thing here and don't require any * changes. This should be further confined once we are able to * reliably detect a Pine64 board. */ if (!strcmp(dt_name, "sun50i-a64-pine64-plus")) { ret = sunxi_pmic_read(0x24); /* read DCDC5 register */ if ((ret & 0x7f) == 0x26) { /* check for 1.24V value */ NOTICE("PMIC: fixing DRAM voltage from 1.24V to 1.36V\n"); sunxi_pmic_write(0x24, 0x2c); } } /* Enable the LCD power planes to get the display up early. */ if (!strcmp(dt_name, "sun50i-a64-pinebook")) { sunxi_pmic_write(0x16, 0x12); /* DLDO2 = VCC-MIPI = 2.5V */ ret = sunxi_pmic_read(0x12); sunxi_pmic_write(0x12, ret | 0x10); sunxi_pmic_write(0x1c, 0x0a); /* FLDO1 = HSIC = 1.2V */ ret = sunxi_pmic_read(0x13); sunxi_pmic_write(0x13, ret | 0x4); NOTICE("PMIC: enabled Pinebook display\n"); } sunxi_pmic_write(0x15, 0x1a); /* DLDO1 = VCC3V3_HDMI voltage = 3.3V */ return 0; } /* * Program the AXP803 via the RSB bus. */ int sunxi_pmic_setup(const char *dt_name) { int ret; NOTICE("Configuring AXP PMIC\n"); ret = init_rsb(); if (ret && ret != -EEXIST) { ERROR("Could not init RSB controller.\n"); return -1; } if (ret != -EEXIST) { ret = pmic_init(AXP803_HW_ADDR, RUNTIME_ADDR); if (ret) { ERROR("Could not connect to AXP PMIC.\n"); return -2; } } ret = pmic_setup(dt_name); if (!ret) NOTICE("PMIC: setup successful\n"); else ERROR("PMIC: setup failed: %d\n", ret); return ret; } arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/sunxi_private.h000066400000000000000000000060461322600646200240570ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __SUNXI_PRIVATE_H__ #define __SUNXI_PRIVATE_H__ #include #include /******************************************************************************* * Forward declarations ******************************************************************************/ struct meminfo; /******************************************************************************* * Function and variable prototypes ******************************************************************************/ void sunxi_configure_mmu_el1(unsigned long total_base, unsigned long total_size, unsigned long, unsigned long, unsigned long, unsigned long); void sunxi_configure_mmu_el3(unsigned long total_base, unsigned long total_size, unsigned long, unsigned long, unsigned long, unsigned long); int sunxi_config_setup(void); uint16_t sunxi_get_socid(void); const char *get_dt_name(void); /* Declarations for sunxi_topology.c */ int plat_setup_topology(void); /* Declarations for sunxi_io_storage.c */ void sunxi_io_setup(void); /* Declarations for sunxi_security.c */ void sunxi_security_setup(void); /* Declarations for sunxi_power.c */ int sunxi_pmic_setup(const char *dt_name); int sunxi_pmic_read(uint8_t address); int sunxi_pmic_write(uint8_t address, uint8_t value); void udelay(unsigned int delay); int sunxi_setup_clocks(uint16_t socid, const char *dt_name); /* Gets the SPSR for BL33 entry */ uint32_t sunxi_get_spsr_for_bl33_entry(int aarch); #endif /* __SUNXI_PRIVATE_H__ */ arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/sunxi_security.c000066400000000000000000000051371322600646200242470ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include "sunxi_def.h" #include "sunxi_private.h" #define SPC_BASE 0x1c23400ULL #define SPC_DECPORT_STA_REG(p) (SPC_BASE + ((p) * 0x0c) + 0x4) #define SPC_DECPORT_SET_REG(p) (SPC_BASE + ((p) * 0x0c) + 0x8) #define SPC_DECPORT_CLR_REG(p) (SPC_BASE + ((p) * 0x0c) + 0xc) /* * For the moment we assume that all security programming is done by the * primary core. * TODO: * Might want to enable interrupt on violations when supported? */ void sunxi_security_setup(void) { int i; NOTICE("Configuring SPC Controller\n"); /* set all devices to non-secure */ for (i = 0; i < 6; i++) mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff); /* switch RSB to secure */ mmio_write_32(SPC_DECPORT_CLR_REG(3), 0x08); /* set CCMU mbus_sec, bus_sec, pll_sec to non-secure */ mmio_write_32(0x01c20000+0x2f0, 0x7); /* set R_PRCM power_sec, pll_sec, cpus_clk to non-secure */ mmio_write_32(0x01f01400+0x1d0, 0x7); /* Set DMA channels 0-7 to non-secure */ mmio_write_32(0x01c02000+0x20, 0xff); } arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/sunxi_sip_svc.c000066400000000000000000000071201322600646200240400ustar00rootroot00000000000000/* * Copyright (c) 2016,2017 ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include "sunxi_sip_svc.h" #include "sunxi_private.h" #include #include /* SiP Service UUID */ DEFINE_SVC_UUID(sunxi_sip_svc_uid, 0x06016e09, 0xd859, 0x4c24, 0xbb, 0x9d, 0x18, 0x92, 0xb4, 0x8d, 0xa5, 0x03); #pragma weak sunxi_plat_sip_handler uint64_t sunxi_plat_sip_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags) { ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); SMC_RET1(handle, SMC_UNK); } /* * This function handles Allwinner defined SiP Calls */ uint64_t sunxi_sip_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags) { /* Determine which security state this SMC originated from */ if (!is_caller_non_secure(flags)) SMC_RET1(handle, SMC_UNK); /* SiP SMC service normal world's call */ switch (smc_fid) { case SUNXI_SIP_MBOX_TRIGGER: SMC_RET1(handle, SMC_UNK); } return sunxi_plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); } /* * This function is responsible for handling all SiP calls from the NS world */ uint64_t sip_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags) { switch (smc_fid) { case SIP_SVC_CALL_COUNT: /* Return the number of Allwinner SiP Service Calls. */ SMC_RET1(handle, SUNXI_COMMON_SIP_NUM_CALLS); case SIP_SVC_UID: /* Return UID to the caller */ SMC_UUID_RET(handle, sunxi_sip_svc_uid); case SIP_SVC_VERSION: /* Return the version of current implementation */ SMC_RET2(handle, SUNXI_SIP_SVC_VERSION_MAJOR, SUNXI_SIP_SVC_VERSION_MINOR); default: return sunxi_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); } } /* Define a runtime service descriptor for fast SMC calls */ DECLARE_RT_SVC( sunxi_sip_svc, OEN_SIP_START, OEN_SIP_END, SMC_TYPE_FAST, NULL, sip_smc_handler ); arm-trusted-firmware-1.0-aw-6/plat/sun50iw1p1/sunxi_sip_svc.h000066400000000000000000000042351322600646200240510ustar00rootroot00000000000000/* * Copyright (c) 2016,2017 ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PLAT_SIP_SVC_H__ #define __PLAT_SIP_SVC_H__ #include /* SMC function IDs for SiP Service queries */ #define SIP_SVC_CALL_COUNT 0x8200ff00 #define SIP_SVC_UID 0x8200ff01 /* 0x8200ff02 is reserved */ #define SIP_SVC_VERSION 0x8200ff03 /* Allwinner SiP Service Calls version numbers */ #define SUNXI_SIP_SVC_VERSION_MAJOR 0x0 #define SUNXI_SIP_SVC_VERSION_MINOR 0x1 #define SMC_AARCH64_BIT 0x40000000 /* Number of Allwinner SiP Calls implemented */ #define SUNXI_COMMON_SIP_NUM_CALLS 1 /* Allwinner SiP Service Calls function IDs */ #define SUNXI_SIP_MBOX_TRIGGER 0x82000001 #endif /* __PLAT_SIP_SVC_H__ */ arm-trusted-firmware-1.0-aw-6/readme.md000066400000000000000000000153671322600646200177770ustar00rootroot00000000000000ARM Trusted Firmware - version 1.0 ================================== ARM Trusted Firmware provides a reference implementation of secure world software for [ARMv8-A], including Exception Level 3 (EL3) software. This release provides initial support for the [Juno ARM Development Platform] [Juno], complementing the existing support for the Base and Foundation [Fixed Virtual Platforms (FVPs)] [FVP] from ARM. The intent is to provide a reference implementation of various ARM interface standards, such as the Power State Coordination Interface ([PSCI]), Trusted Board Boot Requirements (TBBR) and [Secure Monitor] [TEE-SMC] code. As far as possible the code is designed for reuse or porting to other ARMv8-A model and hardware platforms. ARM will continue development in collaboration with interested parties to provide a full reference implementation of PSCI, TBBR and Secure Monitor code to the benefit of all developers working with ARMv8-A TrustZone technology. License ------- The software is provided under a BSD 3-Clause [license]. Certain source files are derived from FreeBSD code: the original license is included in these source files. This Release ------------ This release is a limited functionality implementation of the Trusted Firmware. It provides a suitable starting point for productization. Future versions will contain new features, optimizations and quality improvements. ### Functionality * Initial implementation of a subset of the Trusted Board Boot Requirements Platform Design Document (PDD). This includes packaging the various firmware images into a Firmware Image Package (FIP) to be loaded from non-volatile storage. * Initializes the secure world (for example, exception vectors, control registers, GIC and interrupts for the platform), before transitioning into the normal world. * Supports both GICv2 and GICv3 initialization for use by normal world software. * Starts the normal world at the Exception Level and Register Width provided by the platform port. Typically this is AArch64 EL2 if available. * Handles SMCs (Secure Monitor Calls) conforming to the [SMC Calling Convention PDD] [SMCCC] using an EL3 runtime services framework. * Handles SMCs relating to the [Power State Coordination Interface PDD] [PSCI] for the Secondary CPU Boot, CPU Hotplug, CPU Idle and System Shutdown/Reset use-cases. * A Test Secure-EL1 Payload and Dispatcher to demonstrate Secure Monitor functionality such as world switching, EL1 context management and interrupt routing. This also demonstrates Secure-EL1 interaction with PSCI. Some of this functionality is provided in library form for re-use by other Secure-EL1 Payload Dispatchers. * Support for alternative Trusted Boot Firmware. Some platforms have their own Trusted Boot implementation and only require the Secure Monitor functionality provided by ARM Trusted Firmware. * Isolation of memory accessible by the secure world from the normal world through programming of a TrustZone controller. * Support for CPU specific reset sequences, power down sequences and register dumping during crash reporting. The CPU specific reset sequences include support for errata workarounds. For a full description of functionality and implementation details, please see the [Firmware Design] and supporting documentation. The [Change Log] provides details of changes made since the last release. ### Platforms This release of the Trusted Firmware has been tested on Revision B of the [Juno ARM Development Platform] [Juno] with Version r0p0-00rel7 of the [ARM SCP Firmware] [SCP download]. The Trusted Firmware has also been tested on the 64-bit Linux versions of the following ARM [FVP]s: * `Foundation_v8` (Version 2.1, Build 9.0.24) * `FVP_Base_AEMv8A-AEMv8A` (Version 5.8, Build 0.8.5802) * `FVP_Base_Cortex-A57x4-A53x4` (Version 5.8, Build 0.8.5802) * `FVP_Base_Cortex-A57x1-A53x1` (Version 5.8, Build 0.8.5802) * `FVP_Base_Cortex-A57x2-A53x4` (Version 5.8, Build 0.8.5802) The Foundation FVP can be downloaded free of charge. The Base FVPs can be licensed from ARM: see [www.arm.com/fvp] [FVP]. ### Still to Come * Complete Trusted Boot implementation. * Complete implementation of the [PSCI] specification. * Support for alternative types of Secure-EL1 Payloads. * Completing the currently experimental GICv3 support. * Support for new System IP devices. For a full list of detailed issues in the current code, please see the [Change Log] and the [GitHub issue tracker]. Getting Started --------------- Get the Trusted Firmware source code from [GitHub](https://www.github.com/ARM-software/arm-trusted-firmware). See the [User Guide] for instructions on how to install, build and use the Trusted Firmware with the ARM [FVP]s. See the [Firmware Design] for information on how the ARM Trusted Firmware works. See the [Porting Guide] as well for information about how to use this software on another ARMv8-A platform. See the [Contributing Guidelines] for information on how to contribute to this project and the [Acknowledgments] file for a list of contributors to the project. ### Feedback and support ARM welcomes any feedback on the Trusted Firmware. Please send feedback using the [GitHub issue tracker]. ARM licensees may contact ARM directly via their partner managers. - - - - - - - - - - - - - - - - - - - - - - - - - - _Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._ [License]: ./license.md "BSD license for ARM Trusted Firmware" [Contributing Guidelines]: ./contributing.md "Guidelines for contributors" [Acknowledgments]: ./acknowledgements.md "Contributor acknowledgments" [Change Log]: ./docs/change-log.md [User Guide]: ./docs/user-guide.md [Firmware Design]: ./docs/firmware-design.md [Porting Guide]: ./docs/porting-guide.md [ARMv8-A]: http://www.arm.com/products/processors/armv8-architecture.php "ARMv8-A Architecture" [FVP]: http://www.arm.com/fvp "ARM's Fixed Virtual Platforms" [Juno]: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php "Juno ARM Development Platform" [SCP download]: https://silver.arm.com/download/download.tm?pv=1764630 [PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022b/index.html "Power State Coordination Interface PDD (ARM DEN 0022B.b)" [SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" [TEE-SMC]: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php "Secure Monitor and TEEs" [GitHub issue tracker]: https://github.com/ARM-software/tf-issues/issues arm-trusted-firmware-1.0-aw-6/services/000077500000000000000000000000001322600646200200275ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/services/spd/000077500000000000000000000000001322600646200206155ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/services/spd/tspd/000077500000000000000000000000001322600646200215675ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/services/spd/tspd/tspd.mk000066400000000000000000000045711322600646200231010ustar00rootroot00000000000000# # Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # TSPD_DIR := services/spd/tspd SPD_INCLUDES := -Iinclude/bl32/tsp SPD_SOURCES := services/spd/tspd/tspd_common.c \ services/spd/tspd/tspd_helpers.S \ services/spd/tspd/tspd_main.c \ services/spd/tspd/tspd_pm.c # This dispatcher is paired with a Test Secure Payload source and we intend to # build the Test Secure Payload along with this dispatcher. # # In cases where an associated Secure Payload lies outside this build # system/source tree, the the dispatcher Makefile can either invoke an external # build command or assume it pre-built BL32_ROOT := bl32/tsp # Include SP's Makefile. The assumption is that the TSP's build system is # compatible with that of Trusted Firmware, and it'll add and populate necessary # build targets and variables include ${BL32_ROOT}/tsp.mk # Let the top-level Makefile know that we intend to build the SP from source NEED_BL32 := yes arm-trusted-firmware-1.0-aw-6/services/spd/tspd/tspd_common.c000066400000000000000000000117051322600646200242610ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include "tspd_private.h" /******************************************************************************* * Given a secure payload entrypoint info pointer, entry point PC, register * width, cpu id & pointer to a context data structure, this function will * initialize tsp context and entry point info for the secure payload ******************************************************************************/ void tspd_init_tsp_ep_state(struct entry_point_info *tsp_entry_point, uint32_t rw, uint64_t pc, tsp_context_t *tsp_ctx) { uint32_t ep_attr; /* Passing a NULL context is a critical programming error */ assert(tsp_ctx); assert(tsp_entry_point); assert(pc); /* * We support AArch64 TSP for now. * TODO: Add support for AArch32 TSP */ assert(rw == TSP_AARCH64); /* Associate this context with the cpu specified */ tsp_ctx->mpidr = read_mpidr_el1(); tsp_ctx->state = 0; set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); clr_std_smc_active_flag(tsp_ctx->state); cm_set_context(&tsp_ctx->cpu_ctx, SECURE); /* initialise an entrypoint to set up the CPU context */ ep_attr = SECURE | EP_ST_ENABLE; if (read_sctlr_el3() & SCTLR_EE_BIT) ep_attr |= EP_EE_BIG; SET_PARAM_HEAD(tsp_entry_point, PARAM_EP, VERSION_1, ep_attr); tsp_entry_point->pc = pc; tsp_entry_point->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); memset(&tsp_entry_point->args, 0, sizeof(tsp_entry_point->args)); } /******************************************************************************* * This function takes an SP context pointer and: * 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx. * 2. Saves the current C runtime state (callee saved registers) on the stack * frame and saves a reference to this state. * 3. Calls el3_exit() so that the EL3 system and general purpose registers * from the tsp_ctx->cpu_ctx are used to enter the secure payload image. ******************************************************************************/ uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx) { uint64_t rc; assert(tsp_ctx != NULL); assert(tsp_ctx->c_rt_ctx == 0); /* Apply the Secure EL1 system register context and switch to it */ assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); cm_el1_sysregs_context_restore(SECURE); cm_set_next_eret_context(SECURE); rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx); #if DEBUG tsp_ctx->c_rt_ctx = 0; #endif return rc; } /******************************************************************************* * This function takes an SP context pointer and: * 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx. * 2. Restores the current C runtime state (callee saved registers) from the * stack frame using the reference to this state saved in tspd_enter_sp(). * 3. It does not need to save any general purpose or EL3 system register state * as the generic smc entry routine should have saved those. ******************************************************************************/ void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret) { assert(tsp_ctx != NULL); /* Save the Secure EL1 system register context */ assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); cm_el1_sysregs_context_save(SECURE); assert(tsp_ctx->c_rt_ctx != 0); tspd_exit_sp(tsp_ctx->c_rt_ctx, ret); /* Should never reach here */ assert(0); } arm-trusted-firmware-1.0-aw-6/services/spd/tspd/tspd_helpers.S000066400000000000000000000100211322600646200244010ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include "tspd_private.h" .global tspd_enter_sp /* --------------------------------------------- * This function is called with SP_EL0 as stack. * Here we stash our EL3 callee-saved registers * on to the stack as a part of saving the C * runtime and enter the secure payload. * 'x0' contains a pointer to the memory where * the address of the C runtime context is to be * saved. * --------------------------------------------- */ func tspd_enter_sp /* Make space for the registers that we're going to save */ mov x3, sp str x3, [x0, #0] sub sp, sp, #TSPD_C_RT_CTX_SIZE /* Save callee-saved registers on to the stack */ stp x19, x20, [sp, #TSPD_C_RT_CTX_X19] stp x21, x22, [sp, #TSPD_C_RT_CTX_X21] stp x23, x24, [sp, #TSPD_C_RT_CTX_X23] stp x25, x26, [sp, #TSPD_C_RT_CTX_X25] stp x27, x28, [sp, #TSPD_C_RT_CTX_X27] stp x29, x30, [sp, #TSPD_C_RT_CTX_X29] /* --------------------------------------------- * Everything is setup now. el3_exit() will * use the secure context to restore to the * general purpose and EL3 system registers to * ERET into the secure payload. * --------------------------------------------- */ b el3_exit /* --------------------------------------------- * This function is called 'x0' pointing to a C * runtime context saved in tspd_enter_sp(). It * restores the saved registers and jumps to * that runtime with 'x0' as the new sp. This * destroys the C runtime context that had been * built on the stack below the saved context by * the caller. Later the second parameter 'x1' * is passed as return value to the caller * --------------------------------------------- */ .global tspd_exit_sp func tspd_exit_sp /* Restore the previous stack */ mov sp, x0 /* Restore callee-saved registers on to the stack */ ldp x19, x20, [x0, #(TSPD_C_RT_CTX_X19 - TSPD_C_RT_CTX_SIZE)] ldp x21, x22, [x0, #(TSPD_C_RT_CTX_X21 - TSPD_C_RT_CTX_SIZE)] ldp x23, x24, [x0, #(TSPD_C_RT_CTX_X23 - TSPD_C_RT_CTX_SIZE)] ldp x25, x26, [x0, #(TSPD_C_RT_CTX_X25 - TSPD_C_RT_CTX_SIZE)] ldp x27, x28, [x0, #(TSPD_C_RT_CTX_X27 - TSPD_C_RT_CTX_SIZE)] ldp x29, x30, [x0, #(TSPD_C_RT_CTX_X29 - TSPD_C_RT_CTX_SIZE)] /* --------------------------------------------- * This should take us back to the instruction * after the call to the last tspd_enter_sp(). * Place the second parameter to x0 so that the * caller will see it as a return value from the * original entry call * --------------------------------------------- */ mov x0, x1 ret arm-trusted-firmware-1.0-aw-6/services/spd/tspd/tspd_main.c000066400000000000000000000465111322600646200237200ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /******************************************************************************* * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a * plug-in component to the Secure Monitor, registered as a runtime service. The * SPD is expected to be a functional extension of the Secure Payload (SP) that * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting * the Trusted OS/Applications range to the dispatcher. The SPD will either * handle the request locally or delegate it to the Secure Payload. It is also * responsible for initialising and maintaining communication with the SP. ******************************************************************************/ #include #include #include #include #include #include #include #include #include #include #include #include #include "tspd_private.h" /******************************************************************************* * Address of the entrypoint vector table in the Secure Payload. It is * initialised once on the primary core after a cold boot. ******************************************************************************/ tsp_vectors_t *tsp_vectors; /******************************************************************************* * Array to keep track of per-cpu Secure Payload state ******************************************************************************/ tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; /* TSP UID */ DEFINE_SVC_UUID(tsp_uuid, 0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11, 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); int32_t tspd_init(void); /******************************************************************************* * This function is the handler registered for S-EL1 interrupts by the TSPD. It * validates the interrupt and upon success arranges entry into the TSP at * 'tsp_fiq_entry()' for handling the interrupt. ******************************************************************************/ static uint64_t tspd_sel1_interrupt_handler(uint32_t id, uint32_t flags, void *handle, void *cookie) { uint32_t linear_id; uint64_t mpidr; tsp_context_t *tsp_ctx; /* Check the security state when the exception was generated */ assert(get_interrupt_src_ss(flags) == NON_SECURE); #if IMF_READ_INTERRUPT_ID /* Check the security status of the interrupt */ assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1); #endif /* Sanity check the pointer to this cpu's context */ mpidr = read_mpidr(); assert(handle == cm_get_context(NON_SECURE)); /* Save the non-secure context before entering the TSP */ cm_el1_sysregs_context_save(NON_SECURE); /* Get a reference to this cpu's TSP context */ linear_id = platform_get_core_pos(mpidr); tsp_ctx = &tspd_sp_context[linear_id]; assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); /* * Determine if the TSP was previously preempted. Its last known * context has to be preserved in this case. * The TSP should return control to the TSPD after handling this * FIQ. Preserve essential EL3 context to allow entry into the * TSP at the FIQ entry point using the 'cpu_context' structure. * There is no need to save the secure system register context * since the TSP is supposed to preserve it during S-EL1 interrupt * handling. */ if (get_std_smc_active_flag(tsp_ctx->state)) { tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, CTX_SPSR_EL3); tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, CTX_ELR_EL3); } cm_el1_sysregs_context_restore(SECURE); cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->fiq_entry, SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)); cm_set_next_eret_context(SECURE); /* * Tell the TSP that it has to handle an FIQ synchronously. Also the * instruction in normal world where the interrupt was generated is * passed for debugging purposes. It is safe to retrieve this address * from ELR_EL3 as the secure context will not take effect until * el3_exit(). */ SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_FIQ_AND_RETURN, read_elr_el3()); } /******************************************************************************* * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type * (aarch32/aarch64) if not already known and initialises the context for entry * into the SP for its initialisation. ******************************************************************************/ int32_t tspd_setup(void) { entry_point_info_t *tsp_ep_info; uint64_t mpidr = read_mpidr(); uint32_t linear_id; linear_id = platform_get_core_pos(mpidr); /* * Get information about the Secure Payload (BL32) image. Its * absence is a critical failure. TODO: Add support to * conditionally include the SPD service */ tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE); if (!tsp_ep_info) { WARN("No TSP provided by BL2 boot loader, Booting device" " without TSP initialization. SMC`s destined for TSP" " will return SMC_UNK\n"); return 1; } /* * If there's no valid entry point for SP, we return a non-zero value * signalling failure initializing the service. We bail out without * registering any handlers */ if (!tsp_ep_info->pc) return 1; /* * We could inspect the SP image and determine it's execution * state i.e whether AArch32 or AArch64. Assuming it's AArch64 * for the time being. */ tspd_init_tsp_ep_state(tsp_ep_info, TSP_AARCH64, tsp_ep_info->pc, &tspd_sp_context[linear_id]); #if TSP_INIT_ASYNC bl31_set_next_image_type(SECURE); #else /* * All TSPD initialization done. Now register our init function with * BL31 for deferred invocation */ bl31_register_bl32_init(&tspd_init); #endif return 0; } /******************************************************************************* * This function passes control to the Secure Payload image (BL32) for the first * time on the primary cpu after a cold boot. It assumes that a valid secure * context has already been created by tspd_setup() which can be directly used. * It also assumes that a valid non-secure context has been initialised by PSCI * so it does not need to save and restore any non-secure state. This function * performs a synchronous entry into the Secure payload. The SP passes control * back to this routine through a SMC. ******************************************************************************/ int32_t tspd_init(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; entry_point_info_t *tsp_entry_point; uint64_t rc; /* * Get information about the Secure Payload (BL32) image. Its * absence is a critical failure. */ tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE); assert(tsp_entry_point); cm_init_context(mpidr, tsp_entry_point); /* * Arrange for an entry into the test secure payload. It will be * returned via TSP_ENTRY_DONE case */ rc = tspd_synchronous_sp_entry(tsp_ctx); assert(rc != 0); return rc; } /******************************************************************************* * This function is responsible for handling all SMCs in the Trusted OS/App * range from the non-secure state as defined in the SMC Calling Convention * Document. It is also responsible for communicating with the Secure payload * to delegate work and return results back to the non-secure state. Lastly it * will also return any information that the secure payload needs to do the * work assigned to it. ******************************************************************************/ uint64_t tspd_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags) { cpu_context_t *ns_cpu_context; unsigned long mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr), ns; tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; uint64_t rc; #if TSP_INIT_ASYNC entry_point_info_t *next_image_info; #endif WARN("tspd_smc_handler call\n"); /* Determine which security state this SMC originated from */ ns = is_caller_non_secure(flags); switch (smc_fid) { /* * This function ID is used by TSP to indicate that it was * preempted by a normal world IRQ. * */ case TSP_PREEMPTED: if (ns) SMC_RET1(handle, SMC_UNK); assert(handle == cm_get_context(SECURE)); cm_el1_sysregs_context_save(SECURE); /* Get a reference to the non-secure context */ ns_cpu_context = cm_get_context(NON_SECURE); assert(ns_cpu_context); /* * Restore non-secure state. There is no need to save the * secure system register context since the TSP was supposed * to preserve it during S-EL1 interrupt handling. */ cm_el1_sysregs_context_restore(NON_SECURE); cm_set_next_eret_context(NON_SECURE); SMC_RET1(ns_cpu_context, SMC_PREEMPTED); /* * This function ID is used only by the TSP to indicate that it has * finished handling a S-EL1 FIQ interrupt. Execution should resume * in the normal world. */ case TSP_HANDLED_S_EL1_FIQ: if (ns) SMC_RET1(handle, SMC_UNK); assert(handle == cm_get_context(SECURE)); /* * Restore the relevant EL3 state which saved to service * this SMC. */ if (get_std_smc_active_flag(tsp_ctx->state)) { SMC_SET_EL3(&tsp_ctx->cpu_ctx, CTX_SPSR_EL3, tsp_ctx->saved_spsr_el3); SMC_SET_EL3(&tsp_ctx->cpu_ctx, CTX_ELR_EL3, tsp_ctx->saved_elr_el3); } /* Get a reference to the non-secure context */ ns_cpu_context = cm_get_context(NON_SECURE); assert(ns_cpu_context); /* * Restore non-secure state. There is no need to save the * secure system register context since the TSP was supposed * to preserve it during S-EL1 interrupt handling. */ cm_el1_sysregs_context_restore(NON_SECURE); cm_set_next_eret_context(NON_SECURE); SMC_RET0((uint64_t) ns_cpu_context); /* * This function ID is used only by the TSP to indicate that it was * interrupted due to a EL3 FIQ interrupt. Execution should resume * in the normal world. */ case TSP_EL3_FIQ: if (ns) SMC_RET1(handle, SMC_UNK); assert(handle == cm_get_context(SECURE)); /* Assert that standard SMC execution has been preempted */ assert(get_std_smc_active_flag(tsp_ctx->state)); /* Save the secure system register state */ cm_el1_sysregs_context_save(SECURE); /* Get a reference to the non-secure context */ ns_cpu_context = cm_get_context(NON_SECURE); assert(ns_cpu_context); /* Restore non-secure state */ cm_el1_sysregs_context_restore(NON_SECURE); cm_set_next_eret_context(NON_SECURE); SMC_RET1(ns_cpu_context, TSP_EL3_FIQ); /* * This function ID is used only by the SP to indicate it has * finished initialising itself after a cold boot */ case TSP_ENTRY_DONE: WARN("tspd_smc_handler call:TSP_ENTRY_DONE\n"); if (ns) SMC_RET1(handle, SMC_UNK); /* * Stash the SP entry points information. This is done * only once on the primary cpu */ assert(tsp_vectors == NULL); tsp_vectors = (tsp_vectors_t *) x1; if (tsp_vectors) { set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); /* * TSP has been successfully initialized. Register power * managemnt hooks with PSCI */ psci_register_spd_pm_hook(&tspd_pm); /* * Register an interrupt handler for S-EL1 interrupts * when generated during code executing in the * non-secure state. */ flags = 0; set_interrupt_rm_flag(flags, NON_SECURE); rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, tspd_sel1_interrupt_handler, flags); if (rc) panic(); } #if TSP_INIT_ASYNC /* Save the Secure EL1 system register context */ assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); cm_el1_sysregs_context_save(SECURE); /* Program EL3 registers to enable entry into the next EL */ next_image_info = bl31_plat_get_next_image_ep_info(NON_SECURE); assert(next_image_info); assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr)); cm_init_context(read_mpidr_el1(), next_image_info); cm_prepare_el3_exit(NON_SECURE); SMC_RET0(cm_get_context(NON_SECURE)); #else /* * SP reports completion. The SPD must have initiated * the original request through a synchronous entry * into the SP. Jump back to the original C runtime * context. */ tspd_synchronous_sp_exit(tsp_ctx, x1); #endif /* * These function IDs is used only by the SP to indicate it has * finished: * 1. turning itself on in response to an earlier psci * cpu_on request * 2. resuming itself after an earlier psci cpu_suspend * request. */ case TSP_ON_DONE: case TSP_RESUME_DONE: /* * These function IDs is used only by the SP to indicate it has * finished: * 1. suspending itself after an earlier psci cpu_suspend * request. * 2. turning itself off in response to an earlier psci * cpu_off request. */ case TSP_OFF_DONE: case TSP_SUSPEND_DONE: case TSP_SYSTEM_OFF_DONE: case TSP_SYSTEM_RESET_DONE: if (ns) SMC_RET1(handle, SMC_UNK); /* * SP reports completion. The SPD must have initiated the * original request through a synchronous entry into the SP. * Jump back to the original C runtime context, and pass x1 as * return value to the caller */ tspd_synchronous_sp_exit(tsp_ctx, x1); /* * Request from non-secure client to perform an * arithmetic operation or response from secure * payload to an earlier request. */ case TSP_FAST_FID(TSP_ADD): case TSP_FAST_FID(TSP_SUB): case TSP_FAST_FID(TSP_MUL): case TSP_FAST_FID(TSP_DIV): case TSP_STD_FID(TSP_ADD): case TSP_STD_FID(TSP_SUB): case TSP_STD_FID(TSP_MUL): case TSP_STD_FID(TSP_DIV): if (ns) { /* * This is a fresh request from the non-secure client. * The parameters are in x1 and x2. Figure out which * registers need to be preserved, save the non-secure * state and send the request to the secure payload. */ assert(handle == cm_get_context(NON_SECURE)); /* Check if we are already preempted */ if (get_std_smc_active_flag(tsp_ctx->state)) SMC_RET1(handle, SMC_UNK); cm_el1_sysregs_context_save(NON_SECURE); /* Save x1 and x2 for use by TSP_GET_ARGS call below */ store_tsp_args(tsp_ctx, x1, x2); /* * We are done stashing the non-secure context. Ask the * secure payload to do the work now. */ /* * Verify if there is a valid context to use, copy the * operation type and parameters to the secure context * and jump to the fast smc entry point in the secure * payload. Entry into S-EL1 will take place upon exit * from this function. */ assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); /* Set appropriate entry for SMC. * We expect the TSP to manage the PSTATE.I and PSTATE.F * flags as appropriate. */ if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->fast_smc_entry); } else { set_std_smc_active_flag(tsp_ctx->state); cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->std_smc_entry); } cm_el1_sysregs_context_restore(SECURE); cm_set_next_eret_context(SECURE); SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2); } else { /* * This is the result from the secure client of an * earlier request. The results are in x1-x3. Copy it * into the non-secure context, save the secure state * and return to the non-secure state. */ assert(handle == cm_get_context(SECURE)); cm_el1_sysregs_context_save(SECURE); /* Get a reference to the non-secure context */ ns_cpu_context = cm_get_context(NON_SECURE); assert(ns_cpu_context); /* Restore non-secure state */ cm_el1_sysregs_context_restore(NON_SECURE); cm_set_next_eret_context(NON_SECURE); if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) clr_std_smc_active_flag(tsp_ctx->state); SMC_RET3(ns_cpu_context, x1, x2, x3); } break; /* * Request from non secure world to resume the preempted * Standard SMC call. */ case TSP_FID_RESUME: /* RESUME should be invoked only by normal world */ if (!ns) { assert(0); break; } /* * This is a resume request from the non-secure client. * save the non-secure state and send the request to * the secure payload. */ assert(handle == cm_get_context(NON_SECURE)); /* Check if we are already preempted before resume */ if (!get_std_smc_active_flag(tsp_ctx->state)) SMC_RET1(handle, SMC_UNK); cm_el1_sysregs_context_save(NON_SECURE); /* * We are done stashing the non-secure context. Ask the * secure payload to do the work now. */ /* We just need to return to the preempted point in * TSP and the execution will resume as normal. */ cm_el1_sysregs_context_restore(SECURE); cm_set_next_eret_context(SECURE); SMC_RET0(&tsp_ctx->cpu_ctx); /* * This is a request from the secure payload for more arguments * for an ongoing arithmetic operation requested by the * non-secure world. Simply return the arguments from the non- * secure client in the original call. */ case TSP_GET_ARGS: if (ns) SMC_RET1(handle, SMC_UNK); get_tsp_args(tsp_ctx, x1, x2); SMC_RET2(handle, x1, x2); case TOS_CALL_COUNT: /* * Return the number of service function IDs implemented to * provide service to non-secure */ SMC_RET1(handle, TSP_NUM_FID); case TOS_UID: /* Return TSP UID to the caller */ SMC_UUID_RET(handle, tsp_uuid); case TOS_CALL_VERSION: /* Return the version of current implementation */ SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR); default: break; } SMC_RET1(handle, SMC_UNK); } /* Define a SPD runtime service descriptor for fast SMC calls */ DECLARE_RT_SVC( tspd_fast, OEN_TOS_START, OEN_TOS_END, SMC_TYPE_FAST, tspd_setup, tspd_smc_handler ); /* Define a SPD runtime service descriptor for standard SMC calls */ DECLARE_RT_SVC( tspd_std, OEN_TOS_START, OEN_TOS_END, SMC_TYPE_STD, NULL, tspd_smc_handler ); arm-trusted-firmware-1.0-aw-6/services/spd/tspd/tspd_pm.c000066400000000000000000000222131322600646200234010ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include "tspd_private.h" /******************************************************************************* * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions * needed. Nothing at the moment. ******************************************************************************/ static void tspd_cpu_on_handler(uint64_t target_cpu) { } /******************************************************************************* * This cpu is being turned off. Allow the TSPD/TSP to perform any actions * needed ******************************************************************************/ static int32_t tspd_cpu_off_handler(uint64_t cookie) { int32_t rc = 0; uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); /* Program the entry point and enter the TSP */ cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); rc = tspd_synchronous_sp_entry(tsp_ctx); /* * Read the response from the TSP. A non-zero return means that * something went wrong while communicating with the TSP. */ if (rc != 0) panic(); /* * Reset TSP's context for a fresh start when this cpu is turned on * subsequently. */ set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); return 0; } /******************************************************************************* * This cpu is being suspended. S-EL1 state must have been saved in the * resident cpu (mpidr format) if it is a UP/UP migratable TSP. ******************************************************************************/ static void tspd_cpu_suspend_handler(uint64_t power_state) { int32_t rc = 0; uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); /* Program the entry point, power_state parameter and enter the TSP */ write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), CTX_GPREG_X0, power_state); cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); rc = tspd_synchronous_sp_entry(tsp_ctx); /* * Read the response from the TSP. A non-zero return means that * something went wrong while communicating with the TSP. */ if (rc != 0) panic(); /* Update its context to reflect the state the TSP is in */ set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); } /******************************************************************************* * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits * before passing control back to the Secure Monitor. Entry in S-El1 is done * after initialising minimal architectural state that guarantees safe * execution. ******************************************************************************/ static void tspd_cpu_on_finish_handler(uint64_t cookie) { int32_t rc = 0; uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; entry_point_info_t tsp_on_entrypoint; assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); tspd_init_tsp_ep_state(&tsp_on_entrypoint, TSP_AARCH64, (uint64_t) &tsp_vectors->cpu_on_entry, tsp_ctx); /* Initialise this cpu's secure context */ cm_init_context(mpidr, &tsp_on_entrypoint); /* Enter the TSP */ rc = tspd_synchronous_sp_entry(tsp_ctx); /* * Read the response from the TSP. A non-zero return means that * something went wrong while communicating with the SP. */ if (rc != 0) panic(); /* Update its context to reflect the state the SP is in */ set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); } /******************************************************************************* * This cpu has resumed from suspend. The SPD saved the TSP context when it * completed the preceding suspend call. Use that context to program an entry * into the TSP to allow it to do any remaining book keeping ******************************************************************************/ static void tspd_cpu_suspend_finish_handler(uint64_t suspend_level) { int32_t rc = 0; uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); /* Program the entry point, suspend_level and enter the SP */ write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), CTX_GPREG_X0, suspend_level); cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); rc = tspd_synchronous_sp_entry(tsp_ctx); /* * Read the response from the TSP. A non-zero return means that * something went wrong while communicating with the TSP. */ if (rc != 0) panic(); /* Update its context to reflect the state the SP is in */ set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); } /******************************************************************************* * Return the type of TSP the TSPD is dealing with. Report the current resident * cpu (mpidr format) if it is a UP/UP migratable TSP. ******************************************************************************/ static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu) { return TSP_MIGRATE_INFO; } /******************************************************************************* * System is about to be switched off. Allow the TSPD/TSP to perform * any actions needed. ******************************************************************************/ static void tspd_system_off(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); /* Program the entry point */ cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); /* Enter the TSP. We do not care about the return value because we * must continue the shutdown anyway */ tspd_synchronous_sp_entry(tsp_ctx); } /******************************************************************************* * System is about to be reset. Allow the TSPD/TSP to perform * any actions needed. ******************************************************************************/ static void tspd_system_reset(void) { uint64_t mpidr = read_mpidr(); uint32_t linear_id = platform_get_core_pos(mpidr); tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; assert(tsp_vectors); assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); /* Program the entry point */ cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); /* Enter the TSP. We do not care about the return value because we * must continue the reset anyway */ tspd_synchronous_sp_entry(tsp_ctx); } /******************************************************************************* * Structure populated by the TSP Dispatcher to be given a chance to perform any * TSP bookkeeping before PSCI executes a power mgmt. operation. ******************************************************************************/ const spd_pm_ops_t tspd_pm = { .svc_on = tspd_cpu_on_handler, .svc_off = tspd_cpu_off_handler, .svc_suspend = tspd_cpu_suspend_handler, .svc_on_finish = tspd_cpu_on_finish_handler, .svc_suspend_finish = tspd_cpu_suspend_finish_handler, .svc_migrate = NULL, .svc_migrate_info = tspd_cpu_migrate_info, .svc_system_off = tspd_system_off, .svc_system_reset = tspd_system_reset }; arm-trusted-firmware-1.0-aw-6/services/spd/tspd/tspd_private.h000066400000000000000000000210271322600646200244460ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __TSPD_PRIVATE_H__ #define __TSPD_PRIVATE_H__ #include #include #include #include #include /******************************************************************************* * Secure Payload PM state information e.g. SP is suspended, uninitialised etc * and macros to access the state information in the per-cpu 'state' flags ******************************************************************************/ #define TSP_PSTATE_OFF 0 #define TSP_PSTATE_ON 1 #define TSP_PSTATE_SUSPEND 2 #define TSP_PSTATE_SHIFT 0 #define TSP_PSTATE_MASK 0x3 #define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK) #define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \ << TSP_PSTATE_SHIFT)) #define set_tsp_pstate(st, pst) do { \ clr_tsp_pstate(st); \ st |= (pst & TSP_PSTATE_MASK) << \ TSP_PSTATE_SHIFT; \ } while (0); /* * This flag is used by the TSPD to determine if the TSP is servicing a standard * SMC request prior to programming the next entry into the TSP e.g. if TSP * execution is preempted by a non-secure interrupt and handed control to the * normal world. If another request which is distinct from what the TSP was * previously doing arrives, then this flag will be help the TSPD to either * reject the new request or service it while ensuring that the previous context * is not corrupted. */ #define STD_SMC_ACTIVE_FLAG_SHIFT 2 #define STD_SMC_ACTIVE_FLAG_MASK 1 #define get_std_smc_active_flag(state) ((state >> STD_SMC_ACTIVE_FLAG_SHIFT) \ & STD_SMC_ACTIVE_FLAG_MASK) #define set_std_smc_active_flag(state) (state |= \ 1 << STD_SMC_ACTIVE_FLAG_SHIFT) #define clr_std_smc_active_flag(state) (state &= \ ~(STD_SMC_ACTIVE_FLAG_MASK \ << STD_SMC_ACTIVE_FLAG_SHIFT)) /******************************************************************************* * Secure Payload execution state information i.e. aarch32 or aarch64 ******************************************************************************/ #define TSP_AARCH32 MODE_RW_32 #define TSP_AARCH64 MODE_RW_64 /******************************************************************************* * The SPD should know the type of Secure Payload. ******************************************************************************/ #define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP #define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP #define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP /******************************************************************************* * Secure Payload migrate type information as known to the SPD. We assume that * the SPD is dealing with an MP Secure Payload. ******************************************************************************/ #define TSP_MIGRATE_INFO TSP_TYPE_MP /******************************************************************************* * Number of cpus that the present on this platform. TODO: Rely on a topology * tree to determine this in the future to avoid assumptions about mpidr * allocation ******************************************************************************/ #define TSPD_CORE_COUNT PLATFORM_CORE_COUNT /******************************************************************************* * Constants that allow assembler code to preserve callee-saved registers of the * C runtime context while performing a security state switch. ******************************************************************************/ #define TSPD_C_RT_CTX_X19 0x0 #define TSPD_C_RT_CTX_X20 0x8 #define TSPD_C_RT_CTX_X21 0x10 #define TSPD_C_RT_CTX_X22 0x18 #define TSPD_C_RT_CTX_X23 0x20 #define TSPD_C_RT_CTX_X24 0x28 #define TSPD_C_RT_CTX_X25 0x30 #define TSPD_C_RT_CTX_X26 0x38 #define TSPD_C_RT_CTX_X27 0x40 #define TSPD_C_RT_CTX_X28 0x48 #define TSPD_C_RT_CTX_X29 0x50 #define TSPD_C_RT_CTX_X30 0x58 #define TSPD_C_RT_CTX_SIZE 0x60 #define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT) #ifndef __ASSEMBLY__ #include #include /* * The number of arguments to save during a SMC call for TSP. * Currently only x1 and x2 are used by TSP. */ #define TSP_NUM_ARGS 0x2 /* AArch64 callee saved general purpose register context structure. */ DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES); /* * Compile time assertion to ensure that both the compiler and linker * have the same double word aligned view of the size of the C runtime * register context. */ CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ assert_spd_c_rt_regs_size_mismatch); /******************************************************************************* * Structure which helps the SPD to maintain the per-cpu state of the SP. * 'saved_spsr_el3' - temporary copy to allow FIQ handling when the TSP has been * preempted. * 'saved_elr_el3' - temporary copy to allow FIQ handling when the TSP has been * preempted. * 'state' - collection of flags to track SP state e.g. on/off * 'mpidr' - mpidr to associate a context with a cpu * 'c_rt_ctx' - stack address to restore C runtime context from after * returning from a synchronous entry into the SP. * 'cpu_ctx' - space to maintain SP architectural state * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations * which will queried using the TSP_GET_ARGS SMC by TSP. ******************************************************************************/ typedef struct tsp_context { uint64_t saved_elr_el3; uint32_t saved_spsr_el3; uint32_t state; uint64_t mpidr; uint64_t c_rt_ctx; cpu_context_t cpu_ctx; uint64_t saved_tsp_args[TSP_NUM_ARGS]; } tsp_context_t; /* Helper macros to store and retrieve tsp args from tsp_context */ #define store_tsp_args(tsp_ctx, x1, x2) do {\ tsp_ctx->saved_tsp_args[0] = x1;\ tsp_ctx->saved_tsp_args[1] = x2;\ } while (0) #define get_tsp_args(tsp_ctx, x1, x2) do {\ x1 = tsp_ctx->saved_tsp_args[0];\ x2 = tsp_ctx->saved_tsp_args[1];\ } while (0) /* TSPD power management handlers */ extern const spd_pm_ops_t tspd_pm; /******************************************************************************* * Forward declarations ******************************************************************************/ struct tsp_vectors; /******************************************************************************* * Function & Data prototypes ******************************************************************************/ uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); void tspd_init_tsp_ep_state(struct entry_point_info *tsp_ep, uint32_t rw, uint64_t pc, tsp_context_t *tsp_ctx); extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; extern struct tsp_vectors *tsp_vectors; #endif /*__ASSEMBLY__*/ #endif /* __TSPD_PRIVATE_H__ */ arm-trusted-firmware-1.0-aw-6/services/std_svc/000077500000000000000000000000001322600646200214745ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/000077500000000000000000000000001322600646200224325ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_afflvl_off.c000066400000000000000000000210141322600646200257160ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include "psci_private.h" typedef int (*afflvl_off_handler_t)(aff_map_node_t *); /******************************************************************************* * The next three functions implement a handler for each supported affinity * level which is called when that affinity level is turned off. ******************************************************************************/ static int psci_afflvl0_off(aff_map_node_t *cpu_node) { int rc; assert(cpu_node->level == MPIDR_AFFLVL0); /* * Generic management: Get the index for clearing any lingering re-entry * information and allow the secure world to switch itself off */ /* * Call the cpu off handler registered by the Secure Payload Dispatcher * to let it do any bookeeping. Assume that the SPD always reports an * E_DENIED error if SP refuse to power down */ if (psci_spd_pm && psci_spd_pm->svc_off) { rc = psci_spd_pm->svc_off(0); if (rc) return rc; } /* * Arch. management. Perform the necessary steps to flush all * cpu caches. */ psci_do_pwrdown_cache_maintenance(MPIDR_AFFLVL0); if (!psci_plat_pm_ops->affinst_off) return PSCI_E_SUCCESS; /* * Plat. management: Perform platform specific actions to turn this * cpu off e.g. exit cpu coherency, program the power controller etc. */ return psci_plat_pm_ops->affinst_off(read_mpidr_el1(), cpu_node->level, psci_get_phys_state(cpu_node)); } static int psci_afflvl1_off(aff_map_node_t *cluster_node) { /* Sanity check the cluster level */ assert(cluster_node->level == MPIDR_AFFLVL1); /* * Arch. Management. Flush all levels of caches to PoC if * the cluster is to be shutdown. */ psci_do_pwrdown_cache_maintenance(MPIDR_AFFLVL1); if (!psci_plat_pm_ops->affinst_off) return PSCI_E_SUCCESS; /* * Plat. Management. Allow the platform to do its cluster * specific bookeeping e.g. turn off interconnect coherency, * program the power controller etc. */ return psci_plat_pm_ops->affinst_off(read_mpidr_el1(), cluster_node->level, psci_get_phys_state(cluster_node)); } static int psci_afflvl2_off(aff_map_node_t *system_node) { /* Cannot go beyond this level */ assert(system_node->level == MPIDR_AFFLVL2); /* * Keep the physical state of the system handy to decide what * action needs to be taken */ /* * Arch. Management. Flush all levels of caches to PoC if * the system is to be shutdown. */ psci_do_pwrdown_cache_maintenance(MPIDR_AFFLVL2); if (!psci_plat_pm_ops->affinst_off) return PSCI_E_SUCCESS; /* * Plat. Management : Allow the platform to do its bookeeping * at this affinity level */ return psci_plat_pm_ops->affinst_off(read_mpidr_el1(), system_node->level, psci_get_phys_state(system_node)); } static const afflvl_off_handler_t psci_afflvl_off_handlers[] = { psci_afflvl0_off, psci_afflvl1_off, psci_afflvl2_off, }; /******************************************************************************* * This function takes an array of pointers to affinity instance nodes in the * topology tree and calls the off handler for the corresponding affinity * levels ******************************************************************************/ static int psci_call_off_handlers(aff_map_node_t *mpidr_nodes[], int start_afflvl, int end_afflvl) { int rc = PSCI_E_INVALID_PARAMS, level; aff_map_node_t *node; for (level = start_afflvl; level <= end_afflvl; level++) { node = mpidr_nodes[level]; if (node == NULL) continue; /* * TODO: In case of an error should there be a way * of restoring what we might have torn down at * lower affinity levels. */ rc = psci_afflvl_off_handlers[level](node); if (rc != PSCI_E_SUCCESS) break; } return rc; } /******************************************************************************* * Top level handler which is called when a cpu wants to power itself down. * It's assumed that along with turning the cpu off, higher affinity levels will * be turned off as far as possible. It traverses through all the affinity * levels performing generic, architectural, platform setup and state management * e.g. for a cluster that's to be powered off, it will call the platform * specific code which will disable coherency at the interconnect level if the * cpu is the last in the cluster. For a cpu it could mean programming the power * the power controller etc. * * The state of all the relevant affinity levels is changed prior to calling the * affinity level specific handlers as their actions would depend upon the state * the affinity level is about to enter. * * The affinity level specific handlers are called in ascending order i.e. from * the lowest to the highest affinity level implemented by the platform because * to turn off affinity level X it is neccesary to turn off affinity level X - 1 * first. ******************************************************************************/ int psci_afflvl_off(int start_afflvl, int end_afflvl) { int rc = PSCI_E_SUCCESS; mpidr_aff_map_nodes_t mpidr_nodes; unsigned int max_phys_off_afflvl; /* * Collect the pointers to the nodes in the topology tree for * each affinity instance in the mpidr. If this function does * not return successfully then either the mpidr or the affinity * levels are incorrect. In either case, we cannot return back * to the caller as it would not know what to do. */ rc = psci_get_aff_map_nodes(read_mpidr_el1() & MPIDR_AFFINITY_MASK, start_afflvl, end_afflvl, mpidr_nodes); assert (rc == PSCI_E_SUCCESS); /* * This function acquires the lock corresponding to each affinity * level so that by the time all locks are taken, the system topology * is snapshot and state management can be done safely. */ psci_acquire_afflvl_locks(start_afflvl, end_afflvl, mpidr_nodes); /* * This function updates the state of each affinity instance * corresponding to the mpidr in the range of affinity levels * specified. */ psci_do_afflvl_state_mgmt(start_afflvl, end_afflvl, mpidr_nodes, PSCI_STATE_OFF); max_phys_off_afflvl = psci_find_max_phys_off_afflvl(start_afflvl, end_afflvl, mpidr_nodes); assert(max_phys_off_afflvl != PSCI_INVALID_DATA); /* Stash the highest affinity level that will enter the OFF state. */ psci_set_max_phys_off_afflvl(max_phys_off_afflvl); /* Perform generic, architecture and platform specific handling */ rc = psci_call_off_handlers(mpidr_nodes, start_afflvl, end_afflvl); /* * Invalidate the entry for the highest affinity level stashed earlier. * This ensures that any reads of this variable outside the power * up/down sequences return PSCI_INVALID_DATA. * */ psci_set_max_phys_off_afflvl(PSCI_INVALID_DATA); /* * Release the locks corresponding to each affinity level in the * reverse order to which they were acquired. */ psci_release_afflvl_locks(start_afflvl, end_afflvl, mpidr_nodes); return rc; } arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_afflvl_on.c000066400000000000000000000341441322600646200255700ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include "psci_private.h" typedef int (*afflvl_on_handler_t)(unsigned long, aff_map_node_t *, unsigned long, unsigned long); /******************************************************************************* * This function checks whether a cpu which has been requested to be turned on * is OFF to begin with. ******************************************************************************/ static int cpu_on_validate_state(aff_map_node_t *node) { unsigned int psci_state; /* Get the raw psci state */ psci_state = psci_get_state(node); if (psci_state == PSCI_STATE_ON || psci_state == PSCI_STATE_SUSPEND) return PSCI_E_ALREADY_ON; if (psci_state == PSCI_STATE_ON_PENDING) return PSCI_E_ON_PENDING; assert(psci_state == PSCI_STATE_OFF); return PSCI_E_SUCCESS; } /******************************************************************************* * Handler routine to turn a cpu on. It takes care of any generic, architectural * or platform specific setup required. * TODO: Split this code across separate handlers for each type of setup? ******************************************************************************/ static int psci_afflvl0_on(unsigned long target_cpu, aff_map_node_t *cpu_node, unsigned long ns_entrypoint, unsigned long context_id) { unsigned long psci_entrypoint; uint32_t ns_scr_el3 = read_scr_el3(); uint32_t ns_sctlr_el1 = read_sctlr_el1(); int rc; /* Sanity check to safeguard against data corruption */ assert(cpu_node->level == MPIDR_AFFLVL0); /* * Generic management: Ensure that the cpu is off to be * turned on */ rc = cpu_on_validate_state(cpu_node); if (rc != PSCI_E_SUCCESS) return rc; /* * Call the cpu on handler registered by the Secure Payload Dispatcher * to let it do any bookeeping. If the handler encounters an error, it's * expected to assert within */ if (psci_spd_pm && psci_spd_pm->svc_on) psci_spd_pm->svc_on(target_cpu); /* * Arch. management: Derive the re-entry information for * the non-secure world from the non-secure state from * where this call originated. */ rc = psci_save_ns_entry(target_cpu, ns_entrypoint, context_id, ns_scr_el3, ns_sctlr_el1); if (rc != PSCI_E_SUCCESS) return rc; /* Set the secure world (EL3) re-entry point after BL1 */ psci_entrypoint = (unsigned long) psci_aff_on_finish_entry; if (!psci_plat_pm_ops->affinst_on) return PSCI_E_SUCCESS; /* * Plat. management: Give the platform the current state * of the target cpu to allow it to perform the necessary * steps to power on. */ return psci_plat_pm_ops->affinst_on(target_cpu, psci_entrypoint, ns_entrypoint, cpu_node->level, psci_get_phys_state(cpu_node)); } /******************************************************************************* * Handler routine to turn a cluster on. It takes care or any generic, arch. * or platform specific setup required. * TODO: Split this code across separate handlers for each type of setup? ******************************************************************************/ static int psci_afflvl1_on(unsigned long target_cpu, aff_map_node_t *cluster_node, unsigned long ns_entrypoint, unsigned long context_id) { unsigned long psci_entrypoint; assert(cluster_node->level == MPIDR_AFFLVL1); /* * There is no generic and arch. specific cluster * management required */ /* State management: Is not required while turning a cluster on */ if (!psci_plat_pm_ops->affinst_on) return PSCI_E_SUCCESS; /* * Plat. management: Give the platform the current state * of the target cpu to allow it to perform the necessary * steps to power on. */ psci_entrypoint = (unsigned long) psci_aff_on_finish_entry; return psci_plat_pm_ops->affinst_on(target_cpu, psci_entrypoint, ns_entrypoint, cluster_node->level, psci_get_phys_state(cluster_node)); } /******************************************************************************* * Handler routine to turn a cluster of clusters on. It takes care or any * generic, arch. or platform specific setup required. * TODO: Split this code across separate handlers for each type of setup? ******************************************************************************/ static int psci_afflvl2_on(unsigned long target_cpu, aff_map_node_t *system_node, unsigned long ns_entrypoint, unsigned long context_id) { unsigned long psci_entrypoint; /* Cannot go beyond affinity level 2 in this psci imp. */ assert(system_node->level == MPIDR_AFFLVL2); /* * There is no generic and arch. specific system management * required */ /* State management: Is not required while turning a system on */ if (!psci_plat_pm_ops->affinst_on) return PSCI_E_SUCCESS; /* * Plat. management: Give the platform the current state * of the target cpu to allow it to perform the necessary * steps to power on. */ psci_entrypoint = (unsigned long) psci_aff_on_finish_entry; return psci_plat_pm_ops->affinst_on(target_cpu, psci_entrypoint, ns_entrypoint, system_node->level, psci_get_phys_state(system_node)); } /* Private data structure to make this handlers accessible through indexing */ static const afflvl_on_handler_t psci_afflvl_on_handlers[] = { psci_afflvl0_on, psci_afflvl1_on, psci_afflvl2_on, }; /******************************************************************************* * This function takes an array of pointers to affinity instance nodes in the * topology tree and calls the on handler for the corresponding affinity * levels ******************************************************************************/ static int psci_call_on_handlers(aff_map_node_t *target_cpu_nodes[], int start_afflvl, int end_afflvl, unsigned long target_cpu, unsigned long entrypoint, unsigned long context_id) { int rc = PSCI_E_INVALID_PARAMS, level; aff_map_node_t *node; for (level = end_afflvl; level >= start_afflvl; level--) { node = target_cpu_nodes[level]; if (node == NULL) continue; /* * TODO: In case of an error should there be a way * of undoing what we might have setup at higher * affinity levels. */ rc = psci_afflvl_on_handlers[level](target_cpu, node, entrypoint, context_id); if (rc != PSCI_E_SUCCESS) break; } return rc; } /******************************************************************************* * Generic handler which is called to physically power on a cpu identified by * its mpidr. It traverses through all the affinity levels performing generic, * architectural, platform setup and state management e.g. for a cpu that is * to be powered on, it will ensure that enough information is stashed for it * to resume execution in the non-secure security state. * * The state of all the relevant affinity levels is changed after calling the * affinity level specific handlers as their actions would depend upon the state * the affinity level is currently in. * * The affinity level specific handlers are called in descending order i.e. from * the highest to the lowest affinity level implemented by the platform because * to turn on affinity level X it is neccesary to turn on affinity level X + 1 * first. ******************************************************************************/ int psci_afflvl_on(unsigned long target_cpu, unsigned long entrypoint, unsigned long context_id, int start_afflvl, int end_afflvl) { int rc = PSCI_E_SUCCESS; mpidr_aff_map_nodes_t target_cpu_nodes; /* * Collect the pointers to the nodes in the topology tree for * each affinity instance in the mpidr. If this function does * not return successfully then either the mpidr or the affinity * levels are incorrect. */ rc = psci_get_aff_map_nodes(target_cpu, start_afflvl, end_afflvl, target_cpu_nodes); if (rc != PSCI_E_SUCCESS) return rc; /* * This function acquires the lock corresponding to each affinity * level so that by the time all locks are taken, the system topology * is snapshot and state management can be done safely. */ psci_acquire_afflvl_locks(start_afflvl, end_afflvl, target_cpu_nodes); /* Perform generic, architecture and platform specific handling. */ rc = psci_call_on_handlers(target_cpu_nodes, start_afflvl, end_afflvl, target_cpu, entrypoint, context_id); /* * This function updates the state of each affinity instance * corresponding to the mpidr in the range of affinity levels * specified. */ if (rc == PSCI_E_SUCCESS) psci_do_afflvl_state_mgmt(start_afflvl, end_afflvl, target_cpu_nodes, PSCI_STATE_ON_PENDING); /* * This loop releases the lock corresponding to each affinity level * in the reverse order to which they were acquired. */ psci_release_afflvl_locks(start_afflvl, end_afflvl, target_cpu_nodes); return rc; } /******************************************************************************* * The following functions finish an earlier affinity power on request. They * are called by the common finisher routine in psci_common.c. ******************************************************************************/ static unsigned int psci_afflvl0_on_finish(aff_map_node_t *cpu_node) { unsigned int plat_state, state, rc; assert(cpu_node->level == MPIDR_AFFLVL0); /* Ensure we have been explicitly woken up by another cpu */ state = psci_get_state(cpu_node); assert(state == PSCI_STATE_ON_PENDING); /* * Plat. management: Perform the platform specific actions * for this cpu e.g. enabling the gic or zeroing the mailbox * register. The actual state of this cpu has already been * changed. */ if (psci_plat_pm_ops->affinst_on_finish) { /* Get the physical state of this cpu */ plat_state = get_phys_state(state); rc = psci_plat_pm_ops->affinst_on_finish(read_mpidr_el1(), cpu_node->level, plat_state); assert(rc == PSCI_E_SUCCESS); } /* * Arch. management: Enable data cache and manage stack memory */ psci_do_pwrup_cache_maintenance(); /* * All the platform specific actions for turning this cpu * on have completed. Perform enough arch.initialization * to run in the non-secure address space. */ bl31_arch_setup(); /* * Call the cpu on finish handler registered by the Secure Payload * Dispatcher to let it do any bookeeping. If the handler encounters an * error, it's expected to assert within */ if (psci_spd_pm && psci_spd_pm->svc_on_finish) psci_spd_pm->svc_on_finish(0); /* * Generic management: Now we just need to retrieve the * information that we had stashed away during the cpu_on * call to set this cpu on its way. */ cm_prepare_el3_exit(NON_SECURE); /* Clean caches before re-entering normal world */ dcsw_op_louis(DCCSW); rc = PSCI_E_SUCCESS; return rc; } static unsigned int psci_afflvl1_on_finish(aff_map_node_t *cluster_node) { unsigned int plat_state; assert(cluster_node->level == MPIDR_AFFLVL1); if (!psci_plat_pm_ops->affinst_on_finish) return PSCI_E_SUCCESS; /* * Plat. management: Perform the platform specific actions * as per the old state of the cluster e.g. enabling * coherency at the interconnect depends upon the state with * which this cluster was powered up. If anything goes wrong * then assert as there is no way to recover from this * situation. */ plat_state = psci_get_phys_state(cluster_node); return psci_plat_pm_ops->affinst_on_finish(read_mpidr_el1(), cluster_node->level, plat_state); } static unsigned int psci_afflvl2_on_finish(aff_map_node_t *system_node) { unsigned int plat_state; /* Cannot go beyond this affinity level */ assert(system_node->level == MPIDR_AFFLVL2); if (!psci_plat_pm_ops->affinst_on_finish) return PSCI_E_SUCCESS; /* * Currently, there are no architectural actions to perform * at the system level. */ /* * Plat. management: Perform the platform specific actions * as per the old state of the cluster e.g. enabling * coherency at the interconnect depends upon the state with * which this cluster was powered up. If anything goes wrong * then assert as there is no way to recover from this * situation. */ plat_state = psci_get_phys_state(system_node); return psci_plat_pm_ops->affinst_on_finish(read_mpidr_el1(), system_node->level, plat_state); } const afflvl_power_on_finisher_t psci_afflvl_on_finishers[] = { psci_afflvl0_on_finish, psci_afflvl1_on_finish, psci_afflvl2_on_finish, }; arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_afflvl_suspend.c000066400000000000000000000423631322600646200266370ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include #include "psci_private.h" typedef int (*afflvl_suspend_handler_t)(aff_map_node_t *, unsigned long, unsigned long, unsigned int); /******************************************************************************* * This function saves the power state parameter passed in the current PSCI * cpu_suspend call in the per-cpu data array. ******************************************************************************/ void psci_set_suspend_power_state(unsigned int power_state) { set_cpu_data(psci_svc_cpu_data.power_state, power_state); flush_cpu_data(psci_svc_cpu_data.power_state); } /******************************************************************************* * This function gets the affinity level till which the current cpu could be * powered down during a cpu_suspend call. Returns PSCI_INVALID_DATA if the * power state is invalid. ******************************************************************************/ int psci_get_suspend_afflvl() { unsigned int power_state; power_state = get_cpu_data(psci_svc_cpu_data.power_state); return ((power_state == PSCI_INVALID_DATA) ? power_state : psci_get_pstate_afflvl(power_state)); } /******************************************************************************* * This function gets the state id of the current cpu from the power state * parameter saved in the per-cpu data array. Returns PSCI_INVALID_DATA if the * power state saved is invalid. ******************************************************************************/ int psci_get_suspend_stateid() { unsigned int power_state; power_state = get_cpu_data(psci_svc_cpu_data.power_state); return ((power_state == PSCI_INVALID_DATA) ? power_state : psci_get_pstate_id(power_state)); } /******************************************************************************* * This function gets the state id of the cpu specified by the 'mpidr' parameter * from the power state parameter saved in the per-cpu data array. Returns * PSCI_INVALID_DATA if the power state saved is invalid. ******************************************************************************/ int psci_get_suspend_stateid_by_mpidr(unsigned long mpidr) { unsigned int power_state; power_state = get_cpu_data_by_mpidr(mpidr, psci_svc_cpu_data.power_state); return ((power_state == PSCI_INVALID_DATA) ? power_state : psci_get_pstate_id(power_state)); } /******************************************************************************* * The next three functions implement a handler for each supported affinity * level which is called when that affinity level is about to be suspended. ******************************************************************************/ static int psci_afflvl0_suspend(aff_map_node_t *cpu_node, unsigned long ns_entrypoint, unsigned long context_id, unsigned int power_state) { unsigned long psci_entrypoint; uint32_t ns_scr_el3 = read_scr_el3(); uint32_t ns_sctlr_el1 = read_sctlr_el1(); int rc; /* Sanity check to safeguard against data corruption */ assert(cpu_node->level == MPIDR_AFFLVL0); /* Save PSCI power state parameter for the core in suspend context */ psci_set_suspend_power_state(power_state); /* * Generic management: Store the re-entry information for the non-secure * world and allow the secure world to suspend itself */ /* * Call the cpu suspend handler registered by the Secure Payload * Dispatcher to let it do any bookeeping. If the handler encounters an * error, it's expected to assert within */ if (psci_spd_pm && psci_spd_pm->svc_suspend) psci_spd_pm->svc_suspend(power_state); /* * Generic management: Store the re-entry information for the * non-secure world */ rc = psci_save_ns_entry(read_mpidr_el1(), ns_entrypoint, context_id, ns_scr_el3, ns_sctlr_el1); if (rc != PSCI_E_SUCCESS) return rc; /* Set the secure world (EL3) re-entry point after BL1 */ psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry; /* * Arch. management. Perform the necessary steps to flush all * cpu caches. */ psci_do_pwrdown_cache_maintenance(MPIDR_AFFLVL0); if (!psci_plat_pm_ops->affinst_suspend) return PSCI_E_SUCCESS; /* * Plat. management: Allow the platform to perform the * necessary actions to turn off this cpu e.g. set the * platform defined mailbox with the psci entrypoint, * program the power controller etc. */ return psci_plat_pm_ops->affinst_suspend(read_mpidr_el1(), psci_entrypoint, ns_entrypoint, cpu_node->level, psci_get_phys_state(cpu_node)); } static int psci_afflvl1_suspend(aff_map_node_t *cluster_node, unsigned long ns_entrypoint, unsigned long context_id, unsigned int power_state) { unsigned int plat_state; unsigned long psci_entrypoint; /* Sanity check the cluster level */ assert(cluster_node->level == MPIDR_AFFLVL1); /* * Arch. management: Flush all levels of caches to PoC if the * cluster is to be shutdown. */ psci_do_pwrdown_cache_maintenance(MPIDR_AFFLVL1); if (!psci_plat_pm_ops->affinst_suspend) return PSCI_E_SUCCESS; /* * Plat. Management. Allow the platform to do its cluster specific * bookeeping e.g. turn off interconnect coherency, program the power * controller etc. Sending the psci entrypoint is currently redundant * beyond affinity level 0 but one never knows what a platform might * do. Also it allows us to keep the platform handler prototype the * same. */ plat_state = psci_get_phys_state(cluster_node); psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry; return psci_plat_pm_ops->affinst_suspend(read_mpidr_el1(), psci_entrypoint, ns_entrypoint, cluster_node->level, plat_state); } static int psci_afflvl2_suspend(aff_map_node_t *system_node, unsigned long ns_entrypoint, unsigned long context_id, unsigned int power_state) { unsigned int plat_state; unsigned long psci_entrypoint; /* Cannot go beyond this */ assert(system_node->level == MPIDR_AFFLVL2); /* * Keep the physical state of the system handy to decide what * action needs to be taken */ plat_state = psci_get_phys_state(system_node); /* * Arch. management: Flush all levels of caches to PoC if the * system is to be shutdown. */ psci_do_pwrdown_cache_maintenance(MPIDR_AFFLVL2); /* * Plat. Management : Allow the platform to do its bookeeping * at this affinity level */ if (!psci_plat_pm_ops->affinst_suspend) return PSCI_E_SUCCESS; /* * Sending the psci entrypoint is currently redundant * beyond affinity level 0 but one never knows what a * platform might do. Also it allows us to keep the * platform handler prototype the same. */ plat_state = psci_get_phys_state(system_node); psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry; return psci_plat_pm_ops->affinst_suspend(read_mpidr_el1(), psci_entrypoint, ns_entrypoint, system_node->level, plat_state); } static const afflvl_suspend_handler_t psci_afflvl_suspend_handlers[] = { psci_afflvl0_suspend, psci_afflvl1_suspend, psci_afflvl2_suspend, }; /******************************************************************************* * This function takes an array of pointers to affinity instance nodes in the * topology tree and calls the suspend handler for the corresponding affinity * levels ******************************************************************************/ static int psci_call_suspend_handlers(aff_map_node_t *mpidr_nodes[], int start_afflvl, int end_afflvl, unsigned long entrypoint, unsigned long context_id, unsigned int power_state) { int rc = PSCI_E_INVALID_PARAMS, level; aff_map_node_t *node; for (level = start_afflvl; level <= end_afflvl; level++) { node = mpidr_nodes[level]; if (node == NULL) continue; /* * TODO: In case of an error should there be a way * of restoring what we might have torn down at * lower affinity levels. */ rc = psci_afflvl_suspend_handlers[level](node, entrypoint, context_id, power_state); if (rc != PSCI_E_SUCCESS) break; } return rc; } /******************************************************************************* * Top level handler which is called when a cpu wants to suspend its execution. * It is assumed that along with turning the cpu off, higher affinity levels * until the target affinity level will be turned off as well. It traverses * through all the affinity levels performing generic, architectural, platform * setup and state management e.g. for a cluster that's to be suspended, it will * call the platform specific code which will disable coherency at the * interconnect level if the cpu is the last in the cluster. For a cpu it could * mean programming the power controller etc. * * The state of all the relevant affinity levels is changed prior to calling the * affinity level specific handlers as their actions would depend upon the state * the affinity level is about to enter. * * The affinity level specific handlers are called in ascending order i.e. from * the lowest to the highest affinity level implemented by the platform because * to turn off affinity level X it is neccesary to turn off affinity level X - 1 * first. ******************************************************************************/ int psci_afflvl_suspend(unsigned long entrypoint, unsigned long context_id, unsigned int power_state, int start_afflvl, int end_afflvl) { int rc = PSCI_E_SUCCESS; mpidr_aff_map_nodes_t mpidr_nodes; unsigned int max_phys_off_afflvl; /* * Collect the pointers to the nodes in the topology tree for * each affinity instance in the mpidr. If this function does * not return successfully then either the mpidr or the affinity * levels are incorrect. */ rc = psci_get_aff_map_nodes(read_mpidr_el1() & MPIDR_AFFINITY_MASK, start_afflvl, end_afflvl, mpidr_nodes); if (rc != PSCI_E_SUCCESS) return rc; /* * This function acquires the lock corresponding to each affinity * level so that by the time all locks are taken, the system topology * is snapshot and state management can be done safely. */ psci_acquire_afflvl_locks(start_afflvl, end_afflvl, mpidr_nodes); /* * This function updates the state of each affinity instance * corresponding to the mpidr in the range of affinity levels * specified. */ psci_do_afflvl_state_mgmt(start_afflvl, end_afflvl, mpidr_nodes, PSCI_STATE_SUSPEND); max_phys_off_afflvl = psci_find_max_phys_off_afflvl(start_afflvl, end_afflvl, mpidr_nodes); assert(max_phys_off_afflvl != PSCI_INVALID_DATA); /* Stash the highest affinity level that will be turned off */ psci_set_max_phys_off_afflvl(max_phys_off_afflvl); /* Perform generic, architecture and platform specific handling */ rc = psci_call_suspend_handlers(mpidr_nodes, start_afflvl, end_afflvl, entrypoint, context_id, power_state); /* * Invalidate the entry for the highest affinity level stashed earlier. * This ensures that any reads of this variable outside the power * up/down sequences return PSCI_INVALID_DATA. */ psci_set_max_phys_off_afflvl(PSCI_INVALID_DATA); /* * Release the locks corresponding to each affinity level in the * reverse order to which they were acquired. */ psci_release_afflvl_locks(start_afflvl, end_afflvl, mpidr_nodes); return rc; } /******************************************************************************* * The following functions finish an earlier affinity suspend request. They * are called by the common finisher routine in psci_common.c. ******************************************************************************/ static unsigned int psci_afflvl0_suspend_finish(aff_map_node_t *cpu_node) { unsigned int plat_state, state, rc; int32_t suspend_level; uint64_t counter_freq; assert(cpu_node->level == MPIDR_AFFLVL0); /* Ensure we have been woken up from a suspended state */ state = psci_get_state(cpu_node); assert(state == PSCI_STATE_SUSPEND); /* * Plat. management: Perform the platform specific actions * before we change the state of the cpu e.g. enabling the * gic or zeroing the mailbox register. If anything goes * wrong then assert as there is no way to recover from this * situation. */ if (psci_plat_pm_ops->affinst_suspend_finish) { /* Get the physical state of this cpu */ plat_state = get_phys_state(state); rc = psci_plat_pm_ops->affinst_suspend_finish(read_mpidr_el1(), cpu_node->level, plat_state); assert(rc == PSCI_E_SUCCESS); } /* Get the index for restoring the re-entry information */ /* * Arch. management: Enable the data cache, manage stack memory and * restore the stashed EL3 architectural context from the 'cpu_context' * structure for this cpu. */ psci_do_pwrup_cache_maintenance(); /* Re-init the cntfrq_el0 register */ counter_freq = plat_get_syscnt_freq(); write_cntfrq_el0(counter_freq); /* * Call the cpu suspend finish handler registered by the Secure Payload * Dispatcher to let it do any bookeeping. If the handler encounters an * error, it's expected to assert within */ if (psci_spd_pm && psci_spd_pm->svc_suspend) { suspend_level = psci_get_suspend_afflvl(); assert (suspend_level != PSCI_INVALID_DATA); psci_spd_pm->svc_suspend_finish(suspend_level); } /* Invalidate the suspend context for the node */ psci_set_suspend_power_state(PSCI_INVALID_DATA); /* * Generic management: Now we just need to retrieve the * information that we had stashed away during the suspend * call to set this cpu on its way. */ cm_prepare_el3_exit(NON_SECURE); /* Clean caches before re-entering normal world */ dcsw_op_louis(DCCSW); rc = PSCI_E_SUCCESS; return rc; } static unsigned int psci_afflvl1_suspend_finish(aff_map_node_t *cluster_node) { unsigned int plat_state, rc = PSCI_E_SUCCESS; assert(cluster_node->level == MPIDR_AFFLVL1); /* * Plat. management: Perform the platform specific actions * as per the old state of the cluster e.g. enabling * coherency at the interconnect depends upon the state with * which this cluster was powered up. If anything goes wrong * then assert as there is no way to recover from this * situation. */ if (psci_plat_pm_ops->affinst_suspend_finish) { /* Get the physical state of this cpu */ plat_state = psci_get_phys_state(cluster_node); rc = psci_plat_pm_ops->affinst_suspend_finish(read_mpidr_el1(), cluster_node->level, plat_state); assert(rc == PSCI_E_SUCCESS); } return rc; } static unsigned int psci_afflvl2_suspend_finish(aff_map_node_t *system_node) { unsigned int plat_state, rc = PSCI_E_SUCCESS;; /* Cannot go beyond this affinity level */ assert(system_node->level == MPIDR_AFFLVL2); /* * Currently, there are no architectural actions to perform * at the system level. */ /* * Plat. management: Perform the platform specific actions * as per the old state of the cluster e.g. enabling * coherency at the interconnect depends upon the state with * which this cluster was powered up. If anything goes wrong * then assert as there is no way to recover from this * situation. */ if (psci_plat_pm_ops->affinst_suspend_finish) { /* Get the physical state of the system */ plat_state = psci_get_phys_state(system_node); rc = psci_plat_pm_ops->affinst_suspend_finish(read_mpidr_el1(), system_node->level, plat_state); assert(rc == PSCI_E_SUCCESS); } return rc; } const afflvl_power_on_finisher_t psci_afflvl_suspend_finishers[] = { psci_afflvl0_suspend_finish, psci_afflvl1_suspend_finish, psci_afflvl2_suspend_finish, }; arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_common.c000066400000000000000000000504071322600646200251120ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include #include "psci_private.h" /* * SPD power management operations, expected to be supplied by the registered * SPD on successful SP initialization */ const spd_pm_ops_t *psci_spd_pm; /******************************************************************************* * Grand array that holds the platform's topology information for state * management of affinity instances. Each node (aff_map_node) in the array * corresponds to an affinity instance e.g. cluster, cpu within an mpidr ******************************************************************************/ aff_map_node_t psci_aff_map[PSCI_NUM_AFFS] __attribute__ ((section("tzfw_coherent_mem"))); /******************************************************************************* * Pointer to functions exported by the platform to complete power mgmt. ops ******************************************************************************/ const plat_pm_ops_t *psci_plat_pm_ops; /******************************************************************************* * This function is passed an array of pointers to affinity level nodes in the * topology tree for an mpidr. It iterates through the nodes to find the highest * affinity level which is marked as physically powered off. ******************************************************************************/ uint32_t psci_find_max_phys_off_afflvl(uint32_t start_afflvl, uint32_t end_afflvl, aff_map_node_t *mpidr_nodes[]) { uint32_t max_afflvl = PSCI_INVALID_DATA; for (; start_afflvl <= end_afflvl; start_afflvl++) { if (mpidr_nodes[start_afflvl] == NULL) continue; if (psci_get_phys_state(mpidr_nodes[start_afflvl]) == PSCI_STATE_OFF) max_afflvl = start_afflvl; } return max_afflvl; } /******************************************************************************* * This function saves the highest affinity level which is in OFF state. The * affinity instance with which the level is associated is determined by the * caller. ******************************************************************************/ void psci_set_max_phys_off_afflvl(uint32_t afflvl) { set_cpu_data(psci_svc_cpu_data.max_phys_off_afflvl, afflvl); /* * Ensure that the saved value is flushed to main memory and any * speculatively pre-fetched stale copies are invalidated from the * caches of other cpus in the same coherency domain. This ensures that * the value can be safely read irrespective of the state of the data * cache. */ flush_cpu_data(psci_svc_cpu_data.max_phys_off_afflvl); } /******************************************************************************* * This function reads the saved highest affinity level which is in OFF * state. The affinity instance with which the level is associated is determined * by the caller. ******************************************************************************/ uint32_t psci_get_max_phys_off_afflvl(void) { /* * Ensure that the last update of this value in this cpu's cache is * flushed to main memory and any speculatively pre-fetched stale copies * are invalidated from the caches of other cpus in the same coherency * domain. This ensures that the value is always read from the main * memory when it was written before the data cache was enabled. */ flush_cpu_data(psci_svc_cpu_data.max_phys_off_afflvl); return get_cpu_data(psci_svc_cpu_data.max_phys_off_afflvl); } /******************************************************************************* * Routine to return the maximum affinity level to traverse to after a cpu has * been physically powered up. It is expected to be called immediately after * reset from assembler code. ******************************************************************************/ int get_power_on_target_afflvl() { int afflvl; #if DEBUG unsigned int state; aff_map_node_t *node; /* Retrieve our node from the topology tree */ node = psci_get_aff_map_node(read_mpidr_el1() & MPIDR_AFFINITY_MASK, MPIDR_AFFLVL0); assert(node); /* * Sanity check the state of the cpu. It should be either suspend or "on * pending" */ state = psci_get_state(node); assert(state == PSCI_STATE_SUSPEND || state == PSCI_STATE_ON_PENDING); #endif /* * Assume that this cpu was suspended and retrieve its target affinity * level. If it is invalid then it could only have been turned off * earlier. get_max_afflvl() will return the highest affinity level a * cpu can be turned off to. */ afflvl = psci_get_suspend_afflvl(); if (afflvl == PSCI_INVALID_DATA) afflvl = get_max_afflvl(); return afflvl; } /******************************************************************************* * Simple routine to retrieve the maximum affinity level supported by the * platform and check that it makes sense. ******************************************************************************/ int get_max_afflvl(void) { int aff_lvl; aff_lvl = plat_get_max_afflvl(); assert(aff_lvl <= MPIDR_MAX_AFFLVL && aff_lvl >= MPIDR_AFFLVL0); return aff_lvl; } /******************************************************************************* * Simple routine to set the id of an affinity instance at a given level in the * mpidr. ******************************************************************************/ unsigned long mpidr_set_aff_inst(unsigned long mpidr, unsigned char aff_inst, int aff_lvl) { unsigned long aff_shift; assert(aff_lvl <= MPIDR_AFFLVL3); /* * Decide the number of bits to shift by depending upon * the affinity level */ aff_shift = get_afflvl_shift(aff_lvl); /* Clear the existing affinity instance & set the new one*/ mpidr &= ~(MPIDR_AFFLVL_MASK << aff_shift); mpidr |= aff_inst << aff_shift; return mpidr; } /******************************************************************************* * This function sanity checks a range of affinity levels. ******************************************************************************/ int psci_check_afflvl_range(int start_afflvl, int end_afflvl) { /* Sanity check the parameters passed */ if (end_afflvl > MPIDR_MAX_AFFLVL) return PSCI_E_INVALID_PARAMS; if (start_afflvl < MPIDR_AFFLVL0) return PSCI_E_INVALID_PARAMS; if (end_afflvl < start_afflvl) return PSCI_E_INVALID_PARAMS; return PSCI_E_SUCCESS; } /******************************************************************************* * This function is passed an array of pointers to affinity level nodes in the * topology tree for an mpidr and the state which each node should transition * to. It updates the state of each node between the specified affinity levels. ******************************************************************************/ void psci_do_afflvl_state_mgmt(uint32_t start_afflvl, uint32_t end_afflvl, aff_map_node_t *mpidr_nodes[], uint32_t state) { uint32_t level; for (level = start_afflvl; level <= end_afflvl; level++) { if (mpidr_nodes[level] == NULL) continue; psci_set_state(mpidr_nodes[level], state); } } /******************************************************************************* * This function is passed an array of pointers to affinity level nodes in the * topology tree for an mpidr. It picks up locks for each affinity level bottom * up in the range specified. ******************************************************************************/ void psci_acquire_afflvl_locks(int start_afflvl, int end_afflvl, aff_map_node_t *mpidr_nodes[]) { int level; for (level = start_afflvl; level <= end_afflvl; level++) { if (mpidr_nodes[level] == NULL) continue; bakery_lock_get(&mpidr_nodes[level]->lock); } } /******************************************************************************* * This function is passed an array of pointers to affinity level nodes in the * topology tree for an mpidr. It releases the lock for each affinity level top * down in the range specified. ******************************************************************************/ void psci_release_afflvl_locks(int start_afflvl, int end_afflvl, aff_map_node_t *mpidr_nodes[]) { int level; for (level = end_afflvl; level >= start_afflvl; level--) { if (mpidr_nodes[level] == NULL) continue; bakery_lock_release(&mpidr_nodes[level]->lock); } } /******************************************************************************* * Simple routine to determine whether an affinity instance at a given level * in an mpidr exists or not. ******************************************************************************/ int psci_validate_mpidr(unsigned long mpidr, int level) { aff_map_node_t *node; node = psci_get_aff_map_node(mpidr, level); if (node && (node->state & PSCI_AFF_PRESENT)) return PSCI_E_SUCCESS; else return PSCI_E_INVALID_PARAMS; } /******************************************************************************* * This function determines the full entrypoint information for the requested * PSCI entrypoint on power on/resume and saves this in the non-secure CPU * cpu_context, ready for when the core boots. ******************************************************************************/ int psci_save_ns_entry(uint64_t mpidr, uint64_t entrypoint, uint64_t context_id, uint32_t ns_scr_el3, uint32_t ns_sctlr_el1) { uint32_t ep_attr, mode, sctlr, daif, ee; entry_point_info_t ep; sctlr = ns_scr_el3 & SCR_HCE_BIT ? read_sctlr_el2() : ns_sctlr_el1; ee = 0; ep_attr = NON_SECURE | EP_ST_DISABLE; if (sctlr & SCTLR_EE_BIT) { ep_attr |= EP_EE_BIG; ee = 1; } SET_PARAM_HEAD(&ep, PARAM_EP, VERSION_1, ep_attr); ep.pc = entrypoint; memset(&ep.args, 0, sizeof(ep.args)); ep.args.arg0 = context_id; /* * Figure out whether the cpu enters the non-secure address space * in aarch32 or aarch64 */ if (ns_scr_el3 & SCR_RW_BIT) { /* * Check whether a Thumb entry point has been provided for an * aarch64 EL */ if (entrypoint & 0x1) return PSCI_E_INVALID_PARAMS; mode = ns_scr_el3 & SCR_HCE_BIT ? MODE_EL2 : MODE_EL1; ep.spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } else { mode = ns_scr_el3 & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; /* * TODO: Choose async. exception bits if HYP mode is not * implemented according to the values of SCR.{AW, FW} bits */ daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; ep.spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); } /* initialise an entrypoint to set up the CPU context */ cm_init_context(mpidr, &ep); return PSCI_E_SUCCESS; } /******************************************************************************* * This function takes a pointer to an affinity node in the topology tree and * returns its state. State of a non-leaf node needs to be calculated. ******************************************************************************/ unsigned short psci_get_state(aff_map_node_t *node) { assert(node->level >= MPIDR_AFFLVL0 && node->level <= MPIDR_MAX_AFFLVL); /* A cpu node just contains the state which can be directly returned */ if (node->level == MPIDR_AFFLVL0) return (node->state >> PSCI_STATE_SHIFT) & PSCI_STATE_MASK; /* * For an affinity level higher than a cpu, the state has to be * calculated. It depends upon the value of the reference count * which is managed by each node at the next lower affinity level * e.g. for a cluster, each cpu increments/decrements the reference * count. If the reference count is 0 then the affinity level is * OFF else ON. */ if (node->ref_count) return PSCI_STATE_ON; else return PSCI_STATE_OFF; } /******************************************************************************* * This function takes a pointer to an affinity node in the topology tree and * a target state. State of a non-leaf node needs to be converted to a reference * count. State of a leaf node can be set directly. ******************************************************************************/ void psci_set_state(aff_map_node_t *node, unsigned short state) { assert(node->level >= MPIDR_AFFLVL0 && node->level <= MPIDR_MAX_AFFLVL); /* * For an affinity level higher than a cpu, the state is used * to decide whether the reference count is incremented or * decremented. Entry into the ON_PENDING state does not have * effect. */ if (node->level > MPIDR_AFFLVL0) { switch (state) { case PSCI_STATE_ON: node->ref_count++; break; case PSCI_STATE_OFF: case PSCI_STATE_SUSPEND: node->ref_count--; break; case PSCI_STATE_ON_PENDING: /* * An affinity level higher than a cpu will not undergo * a state change when it is about to be turned on */ return; default: assert(0); } } else { node->state &= ~(PSCI_STATE_MASK << PSCI_STATE_SHIFT); node->state |= (state & PSCI_STATE_MASK) << PSCI_STATE_SHIFT; } } /******************************************************************************* * An affinity level could be on, on_pending, suspended or off. These are the * logical states it can be in. Physically either it is off or on. When it is in * the state on_pending then it is about to be turned on. It is not possible to * tell whether that's actually happenned or not. So we err on the side of * caution & treat the affinity level as being turned off. ******************************************************************************/ unsigned short psci_get_phys_state(aff_map_node_t *node) { unsigned int state; state = psci_get_state(node); return get_phys_state(state); } /******************************************************************************* * This function takes an array of pointers to affinity instance nodes in the * topology tree and calls the physical power on handler for the corresponding * affinity levels ******************************************************************************/ static int psci_call_power_on_handlers(aff_map_node_t *mpidr_nodes[], int start_afflvl, int end_afflvl, afflvl_power_on_finisher_t *pon_handlers) { int rc = PSCI_E_INVALID_PARAMS, level; aff_map_node_t *node; for (level = end_afflvl; level >= start_afflvl; level--) { node = mpidr_nodes[level]; if (node == NULL) continue; /* * If we run into any trouble while powering up an * affinity instance, then there is no recovery path * so simply return an error and let the caller take * care of the situation. */ rc = pon_handlers[level](node); if (rc != PSCI_E_SUCCESS) break; } return rc; } /******************************************************************************* * Generic handler which is called when a cpu is physically powered on. It * traverses through all the affinity levels performing generic, architectural, * platform setup and state management e.g. for a cluster that's been powered * on, it will call the platform specific code which will enable coherency at * the interconnect level. For a cpu it could mean turning on the MMU etc. * * The state of all the relevant affinity levels is changed after calling the * affinity level specific handlers as their actions would depend upon the state * the affinity level is exiting from. * * The affinity level specific handlers are called in descending order i.e. from * the highest to the lowest affinity level implemented by the platform because * to turn on affinity level X it is neccesary to turn on affinity level X + 1 * first. ******************************************************************************/ void psci_afflvl_power_on_finish(int start_afflvl, int end_afflvl, afflvl_power_on_finisher_t *pon_handlers) { mpidr_aff_map_nodes_t mpidr_nodes; int rc; unsigned int max_phys_off_afflvl; /* * Collect the pointers to the nodes in the topology tree for * each affinity instance in the mpidr. If this function does * not return successfully then either the mpidr or the affinity * levels are incorrect. Either case is an irrecoverable error. */ rc = psci_get_aff_map_nodes(read_mpidr_el1() & MPIDR_AFFINITY_MASK, start_afflvl, end_afflvl, mpidr_nodes); if (rc != PSCI_E_SUCCESS) panic(); /* * This function acquires the lock corresponding to each affinity * level so that by the time all locks are taken, the system topology * is snapshot and state management can be done safely. */ psci_acquire_afflvl_locks(start_afflvl, end_afflvl, mpidr_nodes); max_phys_off_afflvl = psci_find_max_phys_off_afflvl(start_afflvl, end_afflvl, mpidr_nodes); assert(max_phys_off_afflvl != PSCI_INVALID_DATA); /* * Stash the highest affinity level that will come out of the OFF or * SUSPEND states. */ psci_set_max_phys_off_afflvl(max_phys_off_afflvl); /* Perform generic, architecture and platform specific handling */ rc = psci_call_power_on_handlers(mpidr_nodes, start_afflvl, end_afflvl, pon_handlers); if (rc != PSCI_E_SUCCESS) panic(); /* * This function updates the state of each affinity instance * corresponding to the mpidr in the range of affinity levels * specified. */ psci_do_afflvl_state_mgmt(start_afflvl, end_afflvl, mpidr_nodes, PSCI_STATE_ON); /* * Invalidate the entry for the highest affinity level stashed earlier. * This ensures that any reads of this variable outside the power * up/down sequences return PSCI_INVALID_DATA */ psci_set_max_phys_off_afflvl(PSCI_INVALID_DATA); /* * This loop releases the lock corresponding to each affinity level * in the reverse order to which they were acquired. */ psci_release_afflvl_locks(start_afflvl, end_afflvl, mpidr_nodes); } /******************************************************************************* * This function initializes the set of hooks that PSCI invokes as part of power * management operation. The power management hooks are expected to be provided * by the SPD, after it finishes all its initialization ******************************************************************************/ void psci_register_spd_pm_hook(const spd_pm_ops_t *pm) { psci_spd_pm = pm; } /******************************************************************************* * This function prints the state of all affinity instances present in the * system ******************************************************************************/ void psci_print_affinity_map(void) { #if LOG_LEVEL >= LOG_LEVEL_INFO aff_map_node_t *node; unsigned int idx; /* This array maps to the PSCI_STATE_X definitions in psci.h */ static const char *psci_state_str[] = { "ON", "OFF", "ON_PENDING", "SUSPEND" }; INFO("PSCI Affinity Map:\n"); for (idx = 0; idx < PSCI_NUM_AFFS ; idx++) { node = &psci_aff_map[idx]; if (!(node->state & PSCI_AFF_PRESENT)) { continue; } INFO(" AffInst: Level %u, MPID 0x%lx, State %s\n", node->level, node->mpidr, psci_state_str[psci_get_state(node)]); } #endif } arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_entry.S000066400000000000000000000127111322600646200247370ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include .globl psci_aff_on_finish_entry .globl psci_aff_suspend_finish_entry .globl psci_power_down_wfi /* ----------------------------------------------------- * This cpu has been physically powered up. Depending * upon whether it was resumed from suspend or simply * turned on, call the common power on finisher with * the handlers (chosen depending upon original state). * ----------------------------------------------------- */ func psci_aff_on_finish_entry adr x23, psci_afflvl_on_finishers b psci_aff_common_finish_entry psci_aff_suspend_finish_entry: adr x23, psci_afflvl_suspend_finishers psci_aff_common_finish_entry: #if !RESET_TO_BL31 /* --------------------------------------------- * Enable the instruction cache, stack pointer * and data access alignment checks. Also, set * the EL3 exception endianess to little-endian. * It can be assumed that BL3-1 entrypoint code * will do this when RESET_TO_BL31 is set. The * same assumption cannot be made when another * boot loader executes before BL3-1 in the warm * boot path e.g. BL1. * --------------------------------------------- */ mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) mrs x0, sctlr_el3 orr x0, x0, x1 msr sctlr_el3, x0 isb #endif /* --------------------------------------------- * Initialise the pcpu cache pointer for the CPU * --------------------------------------------- */ bl init_cpu_data_ptr /* --------------------------------------------- * Initialize the cpu_ops pointer. * --------------------------------------------- */ bl init_cpu_ops /* --------------------------------------------- * Set the exception vectors * --------------------------------------------- */ adr x0, runtime_exceptions msr vbar_el3, x0 isb /* --------------------------------------------- * Enable the SError interrupt now that the * exception vectors have been setup. * --------------------------------------------- */ msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Use SP_EL0 for the C runtime stack. * --------------------------------------------- */ msr spsel, #0 /* -------------------------------------------- * Give ourselves a stack whose memory will be * marked as Normal-IS-WBWA when the MMU is * enabled. * -------------------------------------------- */ mrs x0, mpidr_el1 bl platform_set_stack /* -------------------------------------------- * Enable the MMU with the DCache disabled. It * is safe to use stacks allocated in normal * memory as a result. All memory accesses are * marked nGnRnE when the MMU is disabled. So * all the stack writes will make it to memory. * All memory accesses are marked Non-cacheable * when the MMU is enabled but D$ is disabled. * So used stack memory is guaranteed to be * visible immediately after the MMU is enabled * Enabling the DCache at the same time as the * MMU can lead to speculatively fetched and * possibly stale stack memory being read from * other caches. This can lead to coherency * issues. * -------------------------------------------- */ mov x0, #DISABLE_DCACHE bl bl31_plat_enable_mmu /* --------------------------------------------- * Call the finishers starting from affinity * level 0. * --------------------------------------------- */ bl get_power_on_target_afflvl mov x2, x23 mov x1, x0 mov x0, #MPIDR_AFFLVL0 bl psci_afflvl_power_on_finish b el3_exit /* -------------------------------------------- * This function is called to indicate to the * power controller that it is safe to power * down this cpu. It should not exit the wfi * and will be released from reset upon power * up. 'wfi_spill' is used to catch erroneous * exits from wfi. * -------------------------------------------- */ func psci_power_down_wfi dsb sy // ensure write buffer empty wfi_spill: wfi b wfi_spill arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_helpers.S000066400000000000000000000126531322600646200252450ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include .globl psci_do_pwrdown_cache_maintenance .globl psci_do_pwrup_cache_maintenance /* ----------------------------------------------------------------------- * void psci_do_pwrdown_cache_maintenance(uint32_t affinity level); * * This function performs cache maintenance if the specified affinity * level is the equal to the level of the highest affinity instance which * will be/is physically powered off. The levels of cache affected are * determined by the affinity level which is passed as the argument i.e. * level 0 results in a flush of the L1 cache. Both the L1 and L2 caches * are flushed for a higher affinity level. * * Additionally, this function also ensures that stack memory is correctly * flushed out to avoid coherency issues due to a change in its memory * attributes after the data cache is disabled. * ----------------------------------------------------------------------- */ func psci_do_pwrdown_cache_maintenance stp x29, x30, [sp,#-16]! stp x19, x20, [sp,#-16]! mov x19, x0 bl psci_get_max_phys_off_afflvl #if ASM_ASSERTION cmp x0, #PSCI_INVALID_DATA ASM_ASSERT(ne) #endif cmp x0, x19 b.ne 1f /* --------------------------------------------- * Determine to how many levels of cache will be * subject to cache maintenance. Affinity level * 0 implies that only the cpu is being powered * down. Only the L1 data cache needs to be * flushed to the PoU in this case. For a higher * affinity level we are assuming that a flush * of L1 data and L2 unified cache is enough. * This information should be provided by the * platform. * --------------------------------------------- */ cmp x0, #MPIDR_AFFLVL0 b.eq do_core_pwr_dwn bl prepare_cluster_pwr_dwn b do_stack_maintenance do_core_pwr_dwn: bl prepare_core_pwr_dwn /* --------------------------------------------- * Do stack maintenance by flushing the used * stack to the main memory and invalidating the * remainder. * --------------------------------------------- */ do_stack_maintenance: mrs x0, mpidr_el1 bl platform_get_stack /* --------------------------------------------- * Calculate and store the size of the used * stack memory in x1. * --------------------------------------------- */ mov x19, x0 mov x1, sp sub x1, x0, x1 mov x0, sp bl flush_dcache_range /* --------------------------------------------- * Calculate and store the size of the unused * stack memory in x1. Calculate and store the * stack base address in x0. * --------------------------------------------- */ sub x0, x19, #PLATFORM_STACK_SIZE sub x1, sp, x0 bl inv_dcache_range 1: ldp x19, x20, [sp], #16 ldp x29, x30, [sp], #16 ret /* ----------------------------------------------------------------------- * void psci_do_pwrup_cache_maintenance(void); * * This function performs cache maintenance after this cpu is powered up. * Currently, this involves managing the used stack memory before turning * on the data cache. * ----------------------------------------------------------------------- */ func psci_do_pwrup_cache_maintenance stp x29, x30, [sp,#-16]! /* --------------------------------------------- * Ensure any inflight stack writes have made it * to main memory. * --------------------------------------------- */ dmb st /* --------------------------------------------- * Calculate and store the size of the used * stack memory in x1. Calculate and store the * stack base address in x0. * --------------------------------------------- */ mrs x0, mpidr_el1 bl platform_get_stack mov x1, sp sub x1, x0, x1 mov x0, sp bl inv_dcache_range /* --------------------------------------------- * Enable the data cache. * --------------------------------------------- */ mrs x0, sctlr_el3 orr x0, x0, #SCTLR_C_BIT msr sctlr_el3, x0 isb ldp x29, x30, [sp], #16 ret arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_main.c000066400000000000000000000205131322600646200245410ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include "psci_private.h" /******************************************************************************* * PSCI frontend api for servicing SMCs. Described in the PSCI spec. ******************************************************************************/ int psci_cpu_on(unsigned long target_cpu, unsigned long entrypoint, unsigned long context_id) { int rc; unsigned int start_afflvl, end_afflvl; /* Determine if the cpu exists of not */ rc = psci_validate_mpidr(target_cpu, MPIDR_AFFLVL0); if (rc != PSCI_E_SUCCESS) { goto exit; } /* * To turn this cpu on, specify which affinity * levels need to be turned on */ start_afflvl = MPIDR_AFFLVL0; end_afflvl = get_max_afflvl(); rc = psci_afflvl_on(target_cpu, entrypoint, context_id, start_afflvl, end_afflvl); exit: return rc; } unsigned int psci_version(void) { return PSCI_MAJOR_VER | PSCI_MINOR_VER; } int psci_cpu_suspend(unsigned int power_state, unsigned long entrypoint, unsigned long context_id) { int rc; unsigned int target_afflvl, pstate_type; /* Check SBZ bits in power state are zero */ if (psci_validate_power_state(power_state)) return PSCI_E_INVALID_PARAMS; /* Sanity check the requested state */ target_afflvl = psci_get_pstate_afflvl(power_state); if (target_afflvl > MPIDR_MAX_AFFLVL) return PSCI_E_INVALID_PARAMS; /* Determine the 'state type' in the 'power_state' parameter */ pstate_type = psci_get_pstate_type(power_state); /* * Ensure that we have a platform specific handler for entering * a standby state. */ if (pstate_type == PSTATE_TYPE_STANDBY) { if (!psci_plat_pm_ops->affinst_standby) return PSCI_E_INVALID_PARAMS; rc = psci_plat_pm_ops->affinst_standby(power_state); assert(rc == PSCI_E_INVALID_PARAMS || rc == PSCI_E_SUCCESS); return rc; } /* * Do what is needed to enter the power down state. Upon success, * enter the final wfi which will power down this cpu else return * an error. */ rc = psci_afflvl_suspend(entrypoint, context_id, power_state, MPIDR_AFFLVL0, target_afflvl); if (rc == PSCI_E_SUCCESS) { /* * Perform any platform specific, late power-down actions. * In case this ever returns (it does not need to), fall * through to the normal WFI sequence. */ if (psci_plat_pm_ops->core_power_down_wfi) { unsigned long mpidr = read_mpidr_el1(); psci_plat_pm_ops->core_power_down_wfi(mpidr); } psci_power_down_wfi(); } assert(rc == PSCI_E_INVALID_PARAMS); return rc; } int psci_cpu_off(void) { int rc; int target_afflvl = get_max_afflvl(); /* * Traverse from the highest to the lowest affinity level. When the * lowest affinity level is hit, all the locks are acquired. State * management is done immediately followed by cpu, cluster ... * ..target_afflvl specific actions as this function unwinds back. */ rc = psci_afflvl_off(MPIDR_AFFLVL0, target_afflvl); /* * Check if all actions needed to safely power down this cpu have * successfully completed. Enter a wfi loop which will allow the * power controller to physically power down this cpu. */ if (rc == PSCI_E_SUCCESS) { /* * Perform any platform specific, late power-down actions. * In case this ever returns (it does not need to), fall * through to the normal WFI sequence. */ if (psci_plat_pm_ops->core_power_down_wfi) { unsigned long mpidr = read_mpidr_el1(); psci_plat_pm_ops->core_power_down_wfi(mpidr); } psci_power_down_wfi(); } /* * The only error cpu_off can return is E_DENIED. So check if that's * indeed the case. */ assert (rc == PSCI_E_DENIED); return rc; } int psci_affinity_info(unsigned long target_affinity, unsigned int lowest_affinity_level) { int rc = PSCI_E_INVALID_PARAMS; unsigned int aff_state; aff_map_node_t *node; if (lowest_affinity_level > get_max_afflvl()) return rc; node = psci_get_aff_map_node(target_affinity, lowest_affinity_level); if (node && (node->state & PSCI_AFF_PRESENT)) { /* * TODO: For affinity levels higher than 0 i.e. cpu, the * state will always be either ON or OFF. Need to investigate * how critical is it to support ON_PENDING here. */ aff_state = psci_get_state(node); /* A suspended cpu is available & on for the OS */ if (aff_state == PSCI_STATE_SUSPEND) { aff_state = PSCI_STATE_ON; } rc = aff_state; } return rc; } /* Unimplemented */ int psci_migrate(unsigned int target_cpu) { return PSCI_E_NOT_SUPPORTED; } /* Unimplemented */ unsigned int psci_migrate_info_type(void) { return PSCI_TOS_NOT_PRESENT_MP; } unsigned long psci_migrate_info_up_cpu(void) { /* * Return value of this currently unsupported call depends upon * what psci_migrate_info_type() returns. */ return PSCI_E_SUCCESS; } /******************************************************************************* * PSCI top level handler for servicing SMCs. ******************************************************************************/ uint64_t psci_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags) { if (is_caller_secure(flags)) SMC_RET1(handle, SMC_UNK); if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { /* 32-bit PSCI function, clear top parameter bits */ x1 = (uint32_t)x1; x2 = (uint32_t)x2; x3 = (uint32_t)x3; switch (smc_fid) { case PSCI_VERSION: SMC_RET1(handle, psci_version()); case PSCI_CPU_OFF: SMC_RET1(handle, psci_cpu_off()); case PSCI_CPU_SUSPEND_AARCH32: SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3)); case PSCI_CPU_ON_AARCH32: SMC_RET1(handle, psci_cpu_on(x1, x2, x3)); case PSCI_AFFINITY_INFO_AARCH32: SMC_RET1(handle, psci_affinity_info(x1, x2)); case PSCI_MIG_AARCH32: SMC_RET1(handle, psci_migrate(x1)); case PSCI_MIG_INFO_TYPE: SMC_RET1(handle, psci_migrate_info_type()); case PSCI_MIG_INFO_UP_CPU_AARCH32: SMC_RET1(handle, psci_migrate_info_up_cpu()); case PSCI_SYSTEM_OFF: psci_system_off(); /* We should never return from psci_system_off() */ case PSCI_SYSTEM_RESET: psci_system_reset(); /* We should never return from psci_system_reset() */ default: break; } } else { /* 64-bit PSCI function */ switch (smc_fid) { case PSCI_CPU_SUSPEND_AARCH64: SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3)); case PSCI_CPU_ON_AARCH64: SMC_RET1(handle, psci_cpu_on(x1, x2, x3)); case PSCI_AFFINITY_INFO_AARCH64: SMC_RET1(handle, psci_affinity_info(x1, x2)); case PSCI_MIG_AARCH64: SMC_RET1(handle, psci_migrate(x1)); case PSCI_MIG_INFO_UP_CPU_AARCH64: SMC_RET1(handle, psci_migrate_info_up_cpu()); default: break; } } WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid); SMC_RET1(handle, SMC_UNK); } arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_private.h000066400000000000000000000131341322600646200252750ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __PSCI_PRIVATE_H__ #define __PSCI_PRIVATE_H__ #include #include #include /* for PLATFORM_NUM_AFFS */ #include /* Number of affinity instances whose state this psci imp. can track */ #ifdef PLATFORM_NUM_AFFS #define PSCI_NUM_AFFS PLATFORM_NUM_AFFS #else #define PSCI_NUM_AFFS (2 * PLATFORM_CORE_COUNT) #endif /******************************************************************************* * The following two data structures hold the topology tree which in turn tracks * the state of the all the affinity instances supported by the platform. ******************************************************************************/ typedef struct aff_map_node { unsigned long mpidr; unsigned short ref_count; unsigned char state; unsigned char level; bakery_lock_t lock; } aff_map_node_t; typedef struct aff_limits_node { int min; int max; } aff_limits_node_t; typedef aff_map_node_t (*mpidr_aff_map_nodes_t[MPIDR_MAX_AFFLVL + 1]); typedef unsigned int (*afflvl_power_on_finisher_t)(aff_map_node_t *); /******************************************************************************* * Data prototypes ******************************************************************************/ extern const plat_pm_ops_t *psci_plat_pm_ops; extern aff_map_node_t psci_aff_map[PSCI_NUM_AFFS]; /******************************************************************************* * SPD's power management hooks registered with PSCI ******************************************************************************/ extern const spd_pm_ops_t *psci_spd_pm; /******************************************************************************* * Function prototypes ******************************************************************************/ /* Private exported functions from psci_common.c */ int get_max_afflvl(void); unsigned short psci_get_state(aff_map_node_t *node); unsigned short psci_get_phys_state(aff_map_node_t *node); void psci_set_state(aff_map_node_t *node, unsigned short state); unsigned long mpidr_set_aff_inst(unsigned long, unsigned char, int); int psci_validate_mpidr(unsigned long, int); int get_power_on_target_afflvl(void); void psci_afflvl_power_on_finish(int, int, afflvl_power_on_finisher_t *); int psci_save_ns_entry(uint64_t mpidr, uint64_t entrypoint, uint64_t context_id, uint32_t caller_scr_el3, uint32_t caller_sctlr_el1); int psci_check_afflvl_range(int start_afflvl, int end_afflvl); void psci_do_afflvl_state_mgmt(uint32_t start_afflvl, uint32_t end_afflvl, aff_map_node_t *mpidr_nodes[], uint32_t state); void psci_acquire_afflvl_locks(int start_afflvl, int end_afflvl, aff_map_node_t *mpidr_nodes[]); void psci_release_afflvl_locks(int start_afflvl, int end_afflvl, mpidr_aff_map_nodes_t mpidr_nodes); void psci_print_affinity_map(void); void psci_set_max_phys_off_afflvl(uint32_t afflvl); uint32_t psci_find_max_phys_off_afflvl(uint32_t start_afflvl, uint32_t end_afflvl, aff_map_node_t *mpidr_nodes[]); /* Private exported functions from psci_setup.c */ int psci_get_aff_map_nodes(unsigned long mpidr, int start_afflvl, int end_afflvl, aff_map_node_t *mpidr_nodes[]); aff_map_node_t *psci_get_aff_map_node(unsigned long, int); /* Private exported functions from psci_affinity_on.c */ int psci_afflvl_on(unsigned long, unsigned long, unsigned long, int, int); /* Private exported functions from psci_affinity_off.c */ int psci_afflvl_off(int, int); /* Private exported functions from psci_affinity_suspend.c */ int psci_afflvl_suspend(unsigned long, unsigned long, unsigned int, int, int); unsigned int psci_afflvl_suspend_finish(int, int); void psci_set_suspend_power_state(unsigned int power_state); /* Private exported functions from psci_helpers.S */ void psci_do_pwrdown_cache_maintenance(uint32_t affinity_level); void psci_do_pwrup_cache_maintenance(void); /* Private exported functions from psci_system_off.c */ void __dead2 psci_system_off(void); void __dead2 psci_system_reset(void); #endif /* __PSCI_PRIVATE_H__ */ arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_setup.c000066400000000000000000000322521322600646200247600ustar00rootroot00000000000000/* * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include #include #include #include "psci_private.h" /******************************************************************************* * Per cpu non-secure contexts used to program the architectural state prior * return to the normal world. * TODO: Use the memory allocator to set aside memory for the contexts instead * of relying on platform defined constants. Using PSCI_NUM_AFFS will be an * overkill. ******************************************************************************/ static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT]; /******************************************************************************* * In a system, a certain number of affinity instances are present at an * affinity level. The cumulative number of instances across all levels are * stored in 'psci_aff_map'. The topology tree has been flattenned into this * array. To retrieve nodes, information about the extents of each affinity * level i.e. start index and end index needs to be present. 'psci_aff_limits' * stores this information. ******************************************************************************/ static aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1]; /******************************************************************************* * Routines for retrieving the node corresponding to an affinity level instance * in the mpidr. The first one uses binary search to find the node corresponding * to the mpidr (key) at a particular affinity level. The second routine decides * extents of the binary search at each affinity level. ******************************************************************************/ static int psci_aff_map_get_idx(unsigned long key, int min_idx, int max_idx) { int mid; /* * Terminating condition: If the max and min indices have crossed paths * during the binary search then the key has not been found. */ if (max_idx < min_idx) return PSCI_E_INVALID_PARAMS; /* * Bisect the array around 'mid' and then recurse into the array chunk * where the key is likely to be found. The mpidrs in each node in the * 'psci_aff_map' for a given affinity level are stored in an ascending * order which makes the binary search possible. */ mid = min_idx + ((max_idx - min_idx) >> 1); /* Divide by 2 */ if (psci_aff_map[mid].mpidr > key) return psci_aff_map_get_idx(key, min_idx, mid - 1); else if (psci_aff_map[mid].mpidr < key) return psci_aff_map_get_idx(key, mid + 1, max_idx); else return mid; } aff_map_node_t *psci_get_aff_map_node(unsigned long mpidr, int aff_lvl) { int rc; /* Right shift the mpidr to the required affinity level */ mpidr = mpidr_mask_lower_afflvls(mpidr, aff_lvl); rc = psci_aff_map_get_idx(mpidr, psci_aff_limits[aff_lvl].min, psci_aff_limits[aff_lvl].max); if (rc >= 0) return &psci_aff_map[rc]; else return NULL; } /******************************************************************************* * This function populates an array with nodes corresponding to a given range of * affinity levels in an mpidr. It returns successfully only when the affinity * levels are correct, the mpidr is valid i.e. no affinity level is absent from * the topology tree & the affinity instance at level 0 is not absent. ******************************************************************************/ int psci_get_aff_map_nodes(unsigned long mpidr, int start_afflvl, int end_afflvl, aff_map_node_t *mpidr_nodes[]) { int rc = PSCI_E_INVALID_PARAMS, level; aff_map_node_t *node; rc = psci_check_afflvl_range(start_afflvl, end_afflvl); if (rc != PSCI_E_SUCCESS) return rc; for (level = start_afflvl; level <= end_afflvl; level++) { /* * Grab the node for each affinity level. No affinity level * can be missing as that would mean that the topology tree * is corrupted. */ node = psci_get_aff_map_node(mpidr, level); if (node == NULL) { rc = PSCI_E_INVALID_PARAMS; break; } /* * Skip absent affinity levels unless it's afffinity level 0. * An absent cpu means that the mpidr is invalid. Save the * pointer to the node for the present affinity level */ if (!(node->state & PSCI_AFF_PRESENT)) { if (level == MPIDR_AFFLVL0) { rc = PSCI_E_INVALID_PARAMS; break; } mpidr_nodes[level] = NULL; } else mpidr_nodes[level] = node; } return rc; } /******************************************************************************* * Function which initializes the 'aff_map_node' corresponding to an affinity * level instance. Each node has a unique mpidr, level and bakery lock. The data * field is opaque and holds affinity level specific data e.g. for affinity * level 0 it contains the index into arrays that hold the secure/non-secure * state for a cpu that's been turned on/off ******************************************************************************/ static void psci_init_aff_map_node(unsigned long mpidr, int level, unsigned int idx) { unsigned char state; uint32_t linear_id; psci_aff_map[idx].mpidr = mpidr; psci_aff_map[idx].level = level; bakery_lock_init(&psci_aff_map[idx].lock); /* * If an affinity instance is present then mark it as OFF to begin with. */ state = plat_get_aff_state(level, mpidr); psci_aff_map[idx].state = state; if (level == MPIDR_AFFLVL0) { /* * Mark the cpu as OFF. Higher affinity level reference counts * have already been memset to 0 */ if (state & PSCI_AFF_PRESENT) psci_set_state(&psci_aff_map[idx], PSCI_STATE_OFF); /* * Associate a non-secure context with this affinity * instance through the context management library. */ linear_id = platform_get_core_pos(mpidr); assert(linear_id < PLATFORM_CORE_COUNT); /* Invalidate the suspend context for the node */ set_cpu_data_by_index(linear_id, psci_svc_cpu_data.power_state, PSCI_INVALID_DATA); /* * There is no state associated with the current execution * context so ensure that any reads of the highest affinity * level in a powered down state return PSCI_INVALID_DATA. */ set_cpu_data_by_index(linear_id, psci_svc_cpu_data.max_phys_off_afflvl, PSCI_INVALID_DATA); cm_set_context_by_mpidr(mpidr, (void *) &psci_ns_context[linear_id], NON_SECURE); } return; } /******************************************************************************* * Core routine used by the Breadth-First-Search algorithm to populate the * affinity tree. Each level in the tree corresponds to an affinity level. This * routine's aim is to traverse to the target affinity level and populate nodes * in the 'psci_aff_map' for all the siblings at that level. It uses the current * affinity level to keep track of how many levels from the root of the tree * have been traversed. If the current affinity level != target affinity level, * then the platform is asked to return the number of children that each * affinity instance has at the current affinity level. Traversal is then done * for each child at the next lower level i.e. current affinity level - 1. * * CAUTION: This routine assumes that affinity instance ids are allocated in a * monotonically increasing manner at each affinity level in a mpidr starting * from 0. If the platform breaks this assumption then this code will have to * be reworked accordingly. ******************************************************************************/ static unsigned int psci_init_aff_map(unsigned long mpidr, unsigned int affmap_idx, int cur_afflvl, int tgt_afflvl) { unsigned int ctr, aff_count; assert(cur_afflvl >= tgt_afflvl); /* * Find the number of siblings at the current affinity level & * assert if there are none 'cause then we have been invoked with * an invalid mpidr. */ aff_count = plat_get_aff_count(cur_afflvl, mpidr); assert(aff_count); if (tgt_afflvl < cur_afflvl) { for (ctr = 0; ctr < aff_count; ctr++) { mpidr = mpidr_set_aff_inst(mpidr, ctr, cur_afflvl); affmap_idx = psci_init_aff_map(mpidr, affmap_idx, cur_afflvl - 1, tgt_afflvl); } } else { for (ctr = 0; ctr < aff_count; ctr++, affmap_idx++) { mpidr = mpidr_set_aff_inst(mpidr, ctr, cur_afflvl); psci_init_aff_map_node(mpidr, cur_afflvl, affmap_idx); } /* affmap_idx is 1 greater than the max index of cur_afflvl */ psci_aff_limits[cur_afflvl].max = affmap_idx - 1; } return affmap_idx; } /******************************************************************************* * This function initializes the topology tree by querying the platform. To do * so, it's helper routines implement a Breadth-First-Search. At each affinity * level the platform conveys the number of affinity instances that exist i.e. * the affinity count. The algorithm populates the psci_aff_map recursively * using this information. On a platform that implements two clusters of 4 cpus * each, the populated aff_map_array would look like this: * * <- cpus cluster0 -><- cpus cluster1 -> * --------------------------------------------------- * | 0 | 1 | 0 | 1 | 2 | 3 | 0 | 1 | 2 | 3 | * --------------------------------------------------- * ^ ^ * cluster __| cpu __| * limit limit * * The first 2 entries are of the cluster nodes. The next 4 entries are of cpus * within cluster 0. The last 4 entries are of cpus within cluster 1. * The 'psci_aff_limits' array contains the max & min index of each affinity * level within the 'psci_aff_map' array. This allows restricting search of a * node at an affinity level between the indices in the limits array. ******************************************************************************/ int32_t psci_setup(void) { unsigned long mpidr = read_mpidr(); int afflvl, affmap_idx, max_afflvl; aff_map_node_t *node; psci_plat_pm_ops = NULL; /* Find out the maximum affinity level that the platform implements */ max_afflvl = get_max_afflvl(); assert(max_afflvl <= MPIDR_MAX_AFFLVL); /* * This call traverses the topology tree with help from the platform and * populates the affinity map using a breadth-first-search recursively. * We assume that the platform allocates affinity instance ids from 0 * onwards at each affinity level in the mpidr. FIRST_MPIDR = 0.0.0.0 */ affmap_idx = 0; for (afflvl = max_afflvl; afflvl >= MPIDR_AFFLVL0; afflvl--) { affmap_idx = psci_init_aff_map(FIRST_MPIDR, affmap_idx, max_afflvl, afflvl); } /* * Set the bounds for the affinity counts of each level in the map. Also * flush out the entire array so that it's visible to subsequent power * management operations. The 'psci_aff_map' array is allocated in * coherent memory so does not need flushing. The 'psci_aff_limits' * array is allocated in normal memory. It will be accessed when the mmu * is off e.g. after reset. Hence it needs to be flushed. */ for (afflvl = MPIDR_AFFLVL0; afflvl < max_afflvl; afflvl++) { psci_aff_limits[afflvl].min = psci_aff_limits[afflvl + 1].max + 1; } flush_dcache_range((unsigned long) psci_aff_limits, sizeof(psci_aff_limits)); /* * Mark the affinity instances in our mpidr as ON. No need to lock as * this is the primary cpu. */ mpidr &= MPIDR_AFFINITY_MASK; for (afflvl = MPIDR_AFFLVL0; afflvl <= max_afflvl; afflvl++) { node = psci_get_aff_map_node(mpidr, afflvl); assert(node); /* Mark each present node as ON. */ if (node->state & PSCI_AFF_PRESENT) psci_set_state(node, PSCI_STATE_ON); } platform_setup_pm(&psci_plat_pm_ops); assert(psci_plat_pm_ops); return 0; } arm-trusted-firmware-1.0-aw-6/services/std_svc/psci/psci_system_off.c000066400000000000000000000051131322600646200257720ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include "psci_private.h" void psci_system_off(void) { /* Check platform support */ if (!psci_plat_pm_ops->system_off) { ERROR("Platform has not exported a PSCI System Off hook.\n"); panic(); } psci_print_affinity_map(); /* Notify the Secure Payload Dispatcher */ if (psci_spd_pm && psci_spd_pm->svc_system_off) { psci_spd_pm->svc_system_off(); } /* Call the platform specific hook */ psci_plat_pm_ops->system_off(); /* This function does not return. We should never get here */ } void psci_system_reset(void) { /* Check platform support */ if (!psci_plat_pm_ops->system_reset) { ERROR("Platform has not exported a PSCI System Reset hook.\n"); panic(); } psci_print_affinity_map(); /* Notify the Secure Payload Dispatcher */ if (psci_spd_pm && psci_spd_pm->svc_system_reset) { psci_spd_pm->svc_system_reset(); } /* Call the platform specific hook */ psci_plat_pm_ops->system_reset(); /* This function does not return. We should never get here */ } arm-trusted-firmware-1.0-aw-6/services/std_svc/std_svc_setup.c000066400000000000000000000063351322600646200245340ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include #include #include /* Standard Service UUID */ DEFINE_SVC_UUID(std_svc_uid, 0x108d905b, 0xf863, 0x47e8, 0xae, 0x2d, 0xc0, 0xfb, 0x56, 0x41, 0xf6, 0xe2); /* Setup Standard Services */ static int32_t std_svc_setup(void) { /* * PSCI is the only specification implemented as a Standard Service. * Invoke PSCI setup from here */ return psci_setup(); } /* * Top-level Standard Service SMC handler. This handler will in turn dispatch * calls to PSCI SMC handler */ uint64_t std_svc_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4, void *cookie, void *handle, uint64_t flags) { /* * Dispatch PSCI calls to PSCI SMC handler and return its return * value */ if (is_psci_fid(smc_fid)) { return psci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); } switch (smc_fid) { case ARM_STD_SVC_CALL_COUNT: /* * Return the number of Standard Service Calls. PSCI is the only * standard service implemented; so return number of PSCI calls */ SMC_RET1(handle, PSCI_NUM_CALLS); case ARM_STD_SVC_UID: /* Return UID to the caller */ SMC_UUID_RET(handle, std_svc_uid); case ARM_STD_SVC_VERSION: /* Return the version of current implementation */ SMC_RET2(handle, STD_SVC_VERSION_MAJOR, STD_SVC_VERSION_MINOR); default: WARN("Unimplemented Standard Service Call: 0x%x \n", smc_fid); SMC_RET1(handle, SMC_UNK); } } /* Register Standard Service Calls as runtime service */ DECLARE_RT_SVC( std_svc, OEN_STD_START, OEN_STD_END, SMC_TYPE_FAST, std_svc_setup, std_svc_smc_handler ); arm-trusted-firmware-1.0-aw-6/tools/000077500000000000000000000000001322600646200173445ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/tools/fip_create/000077500000000000000000000000001322600646200214455ustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/tools/fip_create/Makefile000066400000000000000000000041151322600646200231060ustar00rootroot00000000000000# # Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: # # Redistributions of source code must retain the above copyright notice, this # list of conditions and the following disclaimer. # # Redistributions in binary form must reproduce the above copyright notice, # this list of conditions and the following disclaimer in the documentation # and/or other materials provided with the distribution. # # Neither the name of ARM nor the names of its contributors may be used # to endorse or promote products derived from this software without specific # prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE # POSSIBILITY OF SUCH DAMAGE. # PROJECT = fip_create OBJECTS = fip_create.o CFLAGS = -Wall -Werror -pedantic -std=c99 ifeq (${DEBUG},1) CFLAGS += -g -O0 -DDEBUG else CFLAGS += -O2 endif # Make soft links and include from local directory otherwise wrong headers # could get pulled in from firmware tree. INCLUDE_PATHS = -I. CC := gcc RM := rm -rf .PHONY: all clean all: ${PROJECT} ${PROJECT}: ${OBJECTS} Makefile @echo " LD $@" ${Q}${CC} ${OBJECTS} -o $@ -static %.o: %.c %.h Makefile @echo " CC $<" ${Q}${CC} -c ${CFLAGS} ${INCLUDE_PATHS} $< -o $@ clean: ${Q}${RM} ${PROJECT} ${Q}${RM} ${OBJECTS} arm-trusted-firmware-1.0-aw-6/tools/fip_create/fip_create.c000066400000000000000000000433151322600646200237200ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include /* getopt_long() is a GNU extention */ #include #include #include #include #include #include "fip_create.h" #include "firmware_image_package.h" /* Values returned by getopt() as part of the command line parsing */ #define OPT_TOC_ENTRY 0 #define OPT_DUMP 1 #define OPT_HELP 2 file_info_t files[MAX_FILES]; unsigned file_info_count = 0; uuid_t uuid_null = {0}; /* * TODO: Add ability to specify and flag different file types. * Add flags to the toc_entry? * const char* format_type_str[] = { "RAW", "ELF", "PIC" }; */ /* The images used depends on the platform. */ static entry_lookup_list_t toc_entry_lookup_list[] = { { "Trusted Boot Firmware BL2", UUID_TRUSTED_BOOT_FIRMWARE_BL2, "bl2", NULL, FLAG_FILENAME }, { "SCP Firmware BL3-0", UUID_SCP_FIRMWARE_BL30, "bl30", NULL, FLAG_FILENAME}, { "EL3 Runtime Firmware BL3-1", UUID_EL3_RUNTIME_FIRMWARE_BL31, "bl31", NULL, FLAG_FILENAME}, { "Secure Payload BL3-2 (Trusted OS)", UUID_SECURE_PAYLOAD_BL32, "bl32", NULL, FLAG_FILENAME}, { "Non-Trusted Firmware BL3-3", UUID_NON_TRUSTED_FIRMWARE_BL33, "bl33", NULL, FLAG_FILENAME}, { NULL, {0}, 0 } }; /* Return 0 for equal uuids */ static inline int compare_uuids(const uuid_t *uuid1, const uuid_t *uuid2) { return memcmp(uuid1, uuid2, sizeof(uuid_t)); } static inline void copy_uuid(uuid_t *to_uuid, const uuid_t *from_uuid) { memcpy(to_uuid, from_uuid, sizeof(uuid_t)); } static void print_usage(void) { entry_lookup_list_t *entry = toc_entry_lookup_list; printf("Usage: fip_create [options] FIP_FILENAME\n\n"); printf("\tThis tool is used to create a Firmware Image Package.\n\n"); printf("Options:\n"); printf("\t--help: Print this help message and exit\n"); printf("\t--dump: Print contents of FIP\n\n"); printf("\tComponents that can be added/updated:\n"); for (; entry->command_line_name != NULL; entry++) { printf("\t--%s%s\t\t%s", entry->command_line_name, (entry->flags & FLAG_FILENAME) ? " FILENAME" : "", entry->name); printf("\n"); } } static entry_lookup_list_t *get_entry_lookup_from_uuid(const uuid_t *uuid) { unsigned int lookup_index = 0; while (toc_entry_lookup_list[lookup_index].command_line_name != NULL) { if (compare_uuids(&toc_entry_lookup_list[lookup_index].name_uuid, uuid) == 0) { return &toc_entry_lookup_list[lookup_index]; } lookup_index++; } return NULL; } static file_info_t *find_file_info_from_uuid(const uuid_t *uuid) { int index; for (index = 0; index < file_info_count; index++) { if (compare_uuids(&files[index].name_uuid, uuid) == 0) { return &files[index]; } } return NULL; } static int add_file_info_entry(entry_lookup_list_t *lookup_entry, char *filename) { file_info_t *file_info_entry; int error; struct stat file_status; bool is_new_entry = false; /* Check if the file already exists in the array */ file_info_entry = find_file_info_from_uuid(&lookup_entry->name_uuid); if (file_info_entry == NULL) { /* The file does not exist in the current list; take the next * one available in the file_info list. 'file_info_count' is * incremented in case of successful update at the end of the * function. */ file_info_entry = &files[file_info_count]; is_new_entry = true; /* Copy the uuid for the new entry */ copy_uuid(&file_info_entry->name_uuid, &lookup_entry->name_uuid); } /* Get the file information for entry */ error = stat(filename, &file_status); if (error != 0) { printf("Error: Cannot get information for file \"%s\": %s\n", filename, strerror(errno)); return errno; } file_info_entry->filename = filename; file_info_entry->size = (unsigned int)file_status.st_size; file_info_entry->entry = lookup_entry; /* Increment the file_info counter on success if it is new file entry */ if (is_new_entry) { file_info_count++; /* Ensure we do not overflow */ if (file_info_count > MAX_FILES) { printf("ERROR: Too many files in Package\n"); return 1; } } return 0; } static int write_memory_to_file(const uint8_t *start, const char *filename, unsigned int size) { FILE *stream; unsigned int bytes_written; /* Write the packed file out to the filesystem */ stream = fopen(filename, "r+"); if (stream == NULL) { stream = fopen(filename, "w"); if (stream == NULL) { printf("Error: Cannot create output file \"%s\": %s\n", filename, strerror(errno)); return errno; } else { printf("Creating \"%s\"\n", filename); } } else { printf("Updating \"%s\"\n", filename); } bytes_written = fwrite(start, sizeof(uint8_t), size, stream); fclose(stream); if (bytes_written != size) { printf("Error: Incorrect write for file \"%s\": Size=%u," "Written=%u bytes.\n", filename, size, bytes_written); return EIO; } return 0; } static int read_file_to_memory(void *memory, const file_info_t *info) { FILE *stream; unsigned int bytes_read; /* If the file_info is defined by its filename we need to load it */ if (info->filename) { /* Read image from filesystem */ stream = fopen(info->filename, "r"); if (stream == NULL) { printf("Error: Cannot open file \"%s\": %s\n", info->filename, strerror(errno)); return errno; } bytes_read = (unsigned int)fread(memory, sizeof(uint8_t), info->size, stream); fclose(stream); if (bytes_read != info->size) { printf("Error: Incomplete read for file \"%s\":" "Size=%u, Read=%u bytes.\n", info->filename, info->size, bytes_read); return EIO; } } else { if (info->image_buffer == NULL) { printf("ERROR: info->image_buffer = NULL\n"); return EIO; } /* Copy the file_info buffer (extracted from the existing * image package) into the new buffer. */ memcpy(memory, info->image_buffer, info->size); } return 0; } /* Create the image package file */ static int pack_images(const char *fip_filename) { int status; uint8_t *fip_base_address; void *entry_address; fip_toc_header_t *toc_header; fip_toc_entry_t *toc_entry; unsigned int entry_index; unsigned int toc_size; unsigned int fip_size; unsigned int entry_offset_address; unsigned int payload_size = 0; /* Validate filename */ if ((fip_filename == NULL) || (strcmp(fip_filename, "") == 0)) { return EINVAL; } /* Payload size calculation */ for (entry_index = 0; entry_index < file_info_count; entry_index++) { payload_size += files[entry_index].size; } /* Allocate memory for entire package, including the final null entry */ toc_size = (sizeof(fip_toc_header_t) + (sizeof(fip_toc_entry_t) * (file_info_count + 1))); fip_size = toc_size + payload_size; fip_base_address = malloc(fip_size); if (fip_base_address == NULL) { printf("Error: Can't allocate enough memory to create package." "Process aborted.\n"); return ENOMEM; } memset(fip_base_address, 0, fip_size); /* Create ToC Header */ toc_header = (fip_toc_header_t *)fip_base_address; toc_header->name = TOC_HEADER_NAME; toc_header->serial_number = TOC_HEADER_SERIAL_NUMBER; toc_header->flags = 0; toc_entry = (fip_toc_entry_t *)(fip_base_address + sizeof(fip_toc_header_t)); /* Calculate the starting address of the first image, right after the * toc header. */ entry_offset_address = toc_size; entry_index = 0; /* Create the package in memory. */ for (entry_index = 0; entry_index < file_info_count; entry_index++) { entry_address = (fip_base_address + entry_offset_address); status = read_file_to_memory(entry_address, &files[entry_index]); if (status != 0) { printf("Error: While reading \"%s\" from filesystem.\n", files[entry_index].filename); return status; } copy_uuid(&toc_entry->uuid, &files[entry_index].name_uuid); toc_entry->offset_address = entry_offset_address; toc_entry->size = files[entry_index].size; toc_entry->flags = 0; entry_offset_address += toc_entry->size; toc_entry++; } /* Add a null uuid entry to mark the end of toc entries */ copy_uuid(&toc_entry->uuid, &uuid_null); toc_entry->offset_address = entry_offset_address; toc_entry->size = 0; toc_entry->flags = 0; /* Save the package to file */ status = write_memory_to_file(fip_base_address, fip_filename, fip_size); if (status != 0) { printf("Error: Failed while writing package to file \"%s\" " "with status=%d.\n", fip_filename, status); return status; } return 0; } static void dump_toc(void) { unsigned int index = 0; unsigned int image_offset; unsigned int image_size = 0; image_offset = sizeof(fip_toc_header_t) + (sizeof(fip_toc_entry_t) * (file_info_count + 1)); printf("Firmware Image Package ToC:\n"); printf("---------------------------\n"); for (index = 0; index < file_info_count; index++) { if (files[index].entry) { printf("- %s: ", files[index].entry->name); } else { printf("- Unknown entry: "); } image_size = files[index].size; printf("offset=0x%X, size=0x%X\n", image_offset, image_size); image_offset += image_size; if (files[index].filename) { printf(" file: '%s'\n", files[index].filename); } } printf("---------------------------\n"); } /* Read and load existing package into memory. */ static int parse_fip(const char *fip_filename) { FILE *fip; char *fip_buffer; char *fip_buffer_end; int fip_size, read_fip_size; fip_toc_header_t *toc_header; fip_toc_entry_t *toc_entry; bool found_last_toc_entry = false; file_info_t *file_info_entry; int status = -1; struct stat st; fip = fopen(fip_filename, "r"); if (fip == NULL) { /* If the fip does not exist just return, it should not be * considered as an error. The package will be created later */ status = 0; goto parse_fip_return; } if (stat(fip_filename, &st) != 0) { status = errno; goto parse_fip_fclose; } else { fip_size = (int)st.st_size; } /* Allocate a buffer to read the package */ fip_buffer = (char *)malloc(fip_size); if (fip_buffer == NULL) { printf("ERROR: Cannot allocate %d bytes.\n", fip_size); status = errno; goto parse_fip_fclose; } fip_buffer_end = fip_buffer + fip_size; /* Read the file */ read_fip_size = fread(fip_buffer, sizeof(char), fip_size, fip); if (read_fip_size != fip_size) { printf("ERROR: Cannot read the FIP.\n"); status = EIO; goto parse_fip_free; } fclose(fip); fip = NULL; /* The package must at least contain the ToC Header */ if (fip_size < sizeof(fip_toc_header_t)) { printf("ERROR: Given FIP is smaller than the ToC header.\n"); status = EINVAL; goto parse_fip_free; } /* Set the ToC Header at the base of the buffer */ toc_header = (fip_toc_header_t *)fip_buffer; /* The first toc entry should be just after the ToC header */ toc_entry = (fip_toc_entry_t *)(toc_header + 1); /* While the ToC entry is contained into the buffer */ int cnt = 0; while (((char *)toc_entry + sizeof(fip_toc_entry_t)) < fip_buffer_end) { cnt++; /* Check if the ToC Entry is the last one */ if (compare_uuids(&toc_entry->uuid, &uuid_null) == 0) { found_last_toc_entry = true; status = 0; break; } /* Add the entry into file_info */ /* Get the new entry in the array and clear it */ file_info_entry = &files[file_info_count++]; memset(file_info_entry, 0, sizeof(file_info_t)); /* Copy the info from the ToC entry */ copy_uuid(&file_info_entry->name_uuid, &toc_entry->uuid); file_info_entry->image_buffer = fip_buffer + toc_entry->offset_address; file_info_entry->size = toc_entry->size; /* Check if there is a corresponding entry in lookup table */ file_info_entry->entry = get_entry_lookup_from_uuid(&toc_entry->uuid); /* Go to the next ToC entry */ toc_entry++; } if (!found_last_toc_entry) { printf("ERROR: Given FIP does not have an end ToC entry.\n"); status = EINVAL; goto parse_fip_free; } else { /* All is well, we should not free any of the loaded images */ goto parse_fip_fclose; } parse_fip_free: if (fip_buffer != NULL) { free(fip_buffer); fip_buffer = NULL; } parse_fip_fclose: if (fip != NULL) { fclose(fip); } parse_fip_return: return status; } /* Parse all command-line options and return the FIP name if present. */ static char *get_filename(int argc, char **argv, struct option *options) { int c; char *filename = NULL; /* Reset option pointer so we parse all args. starts at 1. * The filename is the only argument that does not have an option flag. */ optind = 1; while (1) { c = getopt_long(argc, argv, "", options, NULL); if (c == -1) break; if (c == '?') { /* Failed to parse an option. Fail. */ return NULL; } } /* Only one argument left then it is the filename. * We dont expect any other options */ if (optind + 1 == argc) filename = argv[optind]; return filename; } /* Work through command-line options */ static int parse_cmdline(int argc, char **argv, struct option *options, int *do_pack) { int c; int status = 0; int option_index = 0; entry_lookup_list_t *lookup_entry; int do_dump = 0; /* restart parse to process all options. starts at 1. */ optind = 1; while (1) { c = getopt_long(argc, argv, "", options, &option_index); if (c == -1) break; switch (c) { case OPT_TOC_ENTRY: if (optarg) { /* Does the option expect a filename. */ lookup_entry = &toc_entry_lookup_list[option_index]; if (lookup_entry->flags & FLAG_FILENAME) { status = add_file_info_entry(lookup_entry, optarg); if (status != 0) { printf("Failed to process %s\n", options[option_index].name); break; } else { /* Update package */ *do_pack = 1; } } } break; case OPT_DUMP: do_dump = 1; continue; case OPT_HELP: print_usage(); exit(0); default: /* Unrecognised options are caught in get_filename() */ break; } } /* Do not dump toc if we have an error as it could hide the error */ if ((status == 0) && (do_dump)) { dump_toc(); } return status; } int main(int argc, char **argv) { int i; int status; char *fip_filename; int do_pack = 0; /* Clear file list table. */ memset(files, 0, sizeof(files)); /* Initialise for getopt_long(). * Use image table as defined at top of file to get options. * Add 'dump' option, 'help' option and end marker. */ static struct option long_options[(sizeof(toc_entry_lookup_list)/ sizeof(entry_lookup_list_t)) + 2]; for (i = 0; /* -1 because we dont want to process end marker in toc table */ i < sizeof(toc_entry_lookup_list)/sizeof(entry_lookup_list_t) - 1; i++) { long_options[i].name = toc_entry_lookup_list[i].command_line_name; /* The only flag defined at the moment is for a FILENAME */ long_options[i].has_arg = toc_entry_lookup_list[i].flags ? 1 : 0; long_options[i].flag = 0; long_options[i].val = OPT_TOC_ENTRY; } /* Add '--dump' option */ long_options[i].name = "dump"; long_options[i].has_arg = 0; long_options[i].flag = 0; long_options[i].val = OPT_DUMP; /* Add '--help' option */ long_options[++i].name = "help"; long_options[i].has_arg = 0; long_options[i].flag = 0; long_options[i].val = OPT_HELP; /* Zero the last entry (required) */ long_options[++i].name = 0; long_options[i].has_arg = 0; long_options[i].flag = 0; long_options[i].val = 0; #ifdef DEBUG /* Print all supported options */ for (i = 0; i < sizeof(long_options)/sizeof(struct option); i++) { printf("long opt (%d) : name = %s\n", i, long_options[i].name); } #endif /* DEBUG */ /* As the package may already exist and is to be updated we need to get * the filename from the arguments and load from it. * NOTE: As this is the first function to look at the program arguments * it causes a failure if bad options were provided. */ fip_filename = get_filename(argc, argv, long_options); /* Try to open the file and load it into memory */ if (fip_filename != NULL) { status = parse_fip(fip_filename); if (status != 0) { return status; } } /* Work through provided program arguments and perform actions */ status = parse_cmdline(argc, argv, long_options, &do_pack); if (status != 0) { return status; }; if (fip_filename == NULL) { printf("ERROR: Missing FIP filename\n"); print_usage(); return 0; } /* Processed all command line options. Create/update the package if * required. */ if (do_pack) { status = pack_images(fip_filename); if (status != 0) { printf("Failed to create package (status = %d).\n", status); } } return status; } arm-trusted-firmware-1.0-aw-6/tools/fip_create/fip_create.h000066400000000000000000000041711322600646200237220ustar00rootroot00000000000000/* * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #ifndef __FIP_CREATE_H__ #define __FIP_CREATE_H__ #include #include #define MAX_FILES 10 /* TODO: Update this number as required */ #define TOC_HEADER_SERIAL_NUMBER 0x12345678 #define FLAG_FILENAME (1 << 0) typedef struct entry_lookup_list { const char *name; uuid_t name_uuid; const char *command_line_name; struct file_info *info; unsigned int flags; } entry_lookup_list_t; typedef struct file_info { uuid_t name_uuid; const char *filename; unsigned int size; void *image_buffer; entry_lookup_list_t *entry; } file_info_t; #endif /* __FIP_CREATE_H__ */ arm-trusted-firmware-1.0-aw-6/tools/fip_create/firmware_image_package.h000077700000000000000000000000001322600646200364052../../include/common/firmware_image_package.hustar00rootroot00000000000000arm-trusted-firmware-1.0-aw-6/tools/fip_create/uuid.h000077700000000000000000000000001322600646200300462../../include/stdlib/sys/uuid.hustar00rootroot00000000000000